JP7701602B2 - Semiconductor device, manufacturing method thereof, and electronic device - Google Patents

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device.

In nitride semiconductor devices such as high electron mobility transistors (HEMTs), a technique is known in which a main electrode region where an electrode is formed is formed as an additional active layer portion by protruding it from the active layer main body of the substrate in order to obtain a low resistance value between the substrate and the electrode formed thereon. In relation to this technique, a method has been proposed in which an opening for the region where the main electrode region is to be formed and a dummy opening are opened in a mask layer formed on the active layer main body, and an additional active layer portion is grown in the opening for the region where the main electrode region is to be formed by utilizing the local loading effect. With this technique, it is believed that film growth does not occur in the dummy opening due to the local loading effect.

JP 2008-85215 A

As a method for reducing the resistance between a semiconductor layer in an active region in which a transistor element is provided and an electrode that is ohmically connected to the semiconductor layer in a semiconductor device, there is a method of providing a semiconductor region between the semiconductor layer and the electrode that contains a dopant of a specific conductivity type to reduce resistance. Such a semiconductor region is formed, for example, by providing a mask with an opening on the semiconductor layer and growing (regrowing) a semiconductor crystal in the opening using a metal organic chemical vapor deposition (MOCVD) method. An electrode that is ohmically connected is connected to the semiconductor region formed on the semiconductor layer.

In the formation of a semiconductor region using the MOCVD method, atoms of the main raw material of the semiconductor region to be formed are supplied not only to the semiconductor layer in the opening of the mask, but also to the mask outside the opening. The atoms of the main raw material supplied onto the mask may diffuse onto the mask. When the atoms of the main raw material diffusing onto the mask move to the opening, they may be consumed in the growth of the semiconductor region on the semiconductor layer. When the atoms of the main raw material diffusing onto the mask move to the opening and are consumed in the growth of the semiconductor region, the growth rate of the semiconductor region grown in the opening becomes faster than when the atoms of the main raw material diffusing onto the mask do not move to the opening. When the growth rate of the semiconductor region becomes faster, the amount of atoms of the dopant raw material taken in decreases, and the resistance of the semiconductor region to be formed may become higher. In this way, if the amount of dopant fluctuates due to the difference in the growth rate of the semiconductor region caused by the influence of the atoms of the main raw material diffusing onto the mask, there is a risk that a semiconductor device in which the resistance of the semiconductor region connected to the electrode is sufficiently reduced cannot be stably realized.

In one aspect, the present invention aims to stably realize a semiconductor device having a low-resistance semiconductor region connected to an electrode.

In one aspect, there is provided a semiconductor device including: a semiconductor layer including an electron supply layer and an electron transit layer ; an active region provided in the semiconductor layer; an inactive region provided in the semiconductor layer and adjacent to the active region; an n-type first semiconductor region provided on a first surface side of the semiconductor layer in the active region, which is on the electron supply layer side ; an n-type second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, spaced apart from the active region and within a distance of 500 μm from the first semiconductor region; and a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region.

In another aspect, a method for manufacturing the semiconductor device as described above and an electronic device including the semiconductor device as described above are provided.

In one aspect, it becomes possible to stably realize a semiconductor device having a low-resistance semiconductor region connected to an electrode.

1A and 1B are diagrams illustrating an example of a semiconductor device. 1A to 1C are diagrams illustrating an example of a method for forming a regrowth region. 11A and 11B are diagrams illustrating differences in growth rate of regrowth regions. FIG. 13 is a diagram showing an example of the relationship between the growth rate of a regrowth region and the on-resistance of a transistor element. 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment; FIG. 13 is a diagram (part 1) illustrating an example of a semiconductor device according to a second embodiment; FIG. 13 is a diagram (part 2) illustrating an example of a semiconductor device according to a second embodiment; 10A to 10C are diagrams illustrating an example of a method for forming a semiconductor device according to a second embodiment; 13A to 13C are diagrams illustrating an example of a method for forming a semiconductor device according to a second embodiment; 13A to 13C are diagrams illustrating an example of a method for forming a semiconductor device according to a second embodiment; 13A to 13C are diagrams illustrating an example of a method for forming a semiconductor device according to a second embodiment (part 4); 5A to 5C are diagrams illustrating an example of a method for forming a semiconductor device according to a second embodiment; 6A to 6C are diagrams illustrating an example of a method for forming a semiconductor device according to a second embodiment; FIG. 7 is a diagram illustrating an example of a method for forming a semiconductor device according to a second embodiment; FIG. 8 is a diagram illustrating an example of a method for forming a semiconductor device according to a second embodiment; FIG. 11 is a diagram showing an example of the relationship between the growth rate of a regrowth region and the on-resistance of a transistor element according to the second embodiment. 13A to 13C are diagrams illustrating a modified example of the semiconductor device according to the second embodiment; FIG. 13 is a diagram (part 2) illustrating a modified example of the semiconductor device according to the second embodiment; FIG. 13 is a diagram (part 3) illustrating a modified example of the semiconductor device according to the second embodiment; FIG. 13 is a diagram (part 1) illustrating an example of a semiconductor device according to a third embodiment; FIG. 13 is a diagram (part 2) illustrating an example of a semiconductor device according to a third embodiment; FIG. 13 is a diagram (part 1) illustrating an example of a semiconductor device according to a fourth embodiment; FIG. 13 is a diagram (part 2) illustrating an example of a semiconductor device according to a fourth embodiment; 13A to 13C are diagrams illustrating an example of a semiconductor package according to a fifth embodiment. FIG. 13 is a diagram illustrating an example of a power factor correction circuit according to a sixth embodiment. FIG. 23 is a diagram illustrating an example of a power supply device according to a seventh embodiment. FIG. 23 is a diagram illustrating an example of an amplifier according to an eighth embodiment.

The so-called selective regrowth ohmic contact technology is known as a technology for reducing the resistance between a semiconductor layer and an electrode to achieve an ohmic connection. In this technology, a low-resistance semiconductor region containing a dopant of a specific conductivity type is selectively grown (regrowth) in a specific portion of the semiconductor layer, and an electrode is connected onto the semiconductor region to achieve an ohmic connection between the electrode and the semiconductor layer. The semiconductor region provided between the semiconductor layer and the electrode is also called a regrowth region, regrowth layer, etc.

By the way, one type of semiconductor device is known to use a nitride semiconductor. Semiconductor devices using nitride semiconductors are being developed as high-voltage, high-power devices by utilizing characteristics such as a high saturation electron velocity and a wide band gap. As a semiconductor device using a nitride semiconductor, many reports have been made on field effect transistors (FETs), for example, HEMTs. As one type of HEMT, a HEMT is known that uses an AlGaN (aluminum gallium nitride) layer as an electron supply layer (also called a "barrier layer") and a GaN (gallium nitride) layer as an electron transport layer (also called a "channel layer"). In such a HEMT, a high concentration of two-dimensional electron gas (2DEG) is generated in the GaN layer near the junction interface with the AlGaN layer due to spontaneous polarization of the AlGaN layer and piezoelectric polarization generated in the AlGaN layer due to strain caused by the lattice constant difference with the GaN layer, thereby realizing a high-power device. For this reason, HEMTs using GaN-based nitride semiconductors are expected to be used in high-output amplifiers for communications and other applications.

Figure 1 is a diagram explaining an example of a semiconductor device. Figure 1(A) shows a schematic cross-sectional view of a main part of a first example of a semiconductor device. Figure 1(B) shows a schematic cross-sectional view of a main part of a second example of a semiconductor device.

The semiconductor device 100A shown in FIG. 1A is an example of a HEMT. The semiconductor device 100A includes a semiconductor layer 110, and a gate electrode 120, a source electrode 130, and a drain electrode 140 provided thereon.

The semiconductor layer 110 includes an electron transit layer 111 and an electron supply layer 112. For example, GaN is used for the electron transit layer 111, and AlGaN is used for the electron supply layer 112. 2DEG1a is generated near the junction interface between the electron transit layer 111 and the electron supply layer 112. The 2DEG1a is generated in an active region 160 defined by an inactive region 150 provided in the semiconductor layer 110. The inactive region 150 is a region formed as an element isolation region by ion implantation of Ar (argon) into the semiconductor layer 110, or the like. The active region 160 is a region formed as an element region defined by such an element isolation region.

The gate electrode 120 is provided on the electron supply layer 112 of the semiconductor layer 110 in the active region 160. The gate electrode 120 is provided on the electron supply layer 112 so as to function as a Schottky electrode. The source electrode 130 and the drain electrode 140 are provided on the electron supply layer 112 of the semiconductor layer 110 in the active region 160 so as to sandwich the gate electrode 120. The source electrode 130 and the drain electrode 140 are formed on the electron supply layer 112 so as to function as ohmic electrodes.

During operation of the semiconductor device 100A, a predetermined voltage is supplied between the source electrode 130 and the drain electrode 140, and a predetermined gate voltage is supplied to the gate electrode 120. A channel through which carrier electrons are transported is formed in the electron transit layer 111 between the source electrode 130 and the drain electrode 140, realizing the transistor function of the semiconductor device 100A.

In the semiconductor device 100A, the electron supply layer 112 is interposed between the channel, i.e., the 2DEG1a generated in the electron transit layer 111 near the junction interface with the electron supply layer 112, and the source electrode 130 and the drain electrode 140 provided on the electron supply layer 112. In the semiconductor device 100A, the resistance R1 between the 2DEG1a and the source electrode 130 and the drain electrode 140 is relatively high. Therefore, in the semiconductor device 100A, the on-resistance between the source electrode 130 and the drain electrode 140 via the channel of the transistor element provided therein is relatively high. If the on-resistance becomes high, the increase in the current between the source electrode 130 and the drain electrode 140 of the semiconductor device 100A is suppressed, and the increase in the output of the semiconductor device 100A is suppressed.

Therefore, the selective regrowth ohmic contact technique described above is employed to connect the source electrode 130 and the drain electrode 140 to the semiconductor layer 110 .
The semiconductor device 100B shown in Fig. 1B is an example of a HEMT that employs selective regrowth ohmic contact technology. The semiconductor device 100B has a configuration in which an n-type semiconductor region 181 and an n-type semiconductor region 182 (regrowth regions) are provided in recesses 171 and 172 provided in the semiconductor layer 110, respectively, and a source electrode 130 and a drain electrode 140 are connected to the n-type semiconductor region 181 and the n-type semiconductor region 182, respectively. The semiconductor device 100B differs from the semiconductor device 100A in that it has such a configuration.

In the semiconductor device 100B, the recesses 171 and 172 are provided, for example, so that they penetrate the electron supply layer 112 to reach the electron transit layer 111, and the bottom surfaces of the recesses 171 and 172 are located deeper than the 2DEG 1a generated in the electron transit layer 111. In the recesses 171 and 172, for example, the n-type semiconductor region 181 and the n-type semiconductor region 182 are grown (regrown) and formed, respectively, using the MOCVD method. For example, the n-type semiconductor region 181 and the n-type semiconductor region 182 are made of n-type GaN. The source electrode 130 and the drain electrode 140 are connected to the formed n-type semiconductor region 181 and the n-type semiconductor region 182, respectively.

In the semiconductor device 100B, the 2DEG1a of the channel generated in the electron transit layer 111 is connected to the relatively low-resistance n-type semiconductor region 181 and n-type semiconductor region 182, and the resistance R2 between the 2DEG1a and the n-type semiconductor region 181 and n-type semiconductor region 182 is relatively low. The source electrode 130 and drain electrode 140 are connected to the relatively low-resistance n-type semiconductor region 181 and n-type semiconductor region 182, respectively. This makes the resistance between the 2DEG1a and the source electrode 130 and drain electrode 140 relatively low. Therefore, in the semiconductor device 100B, the on-resistance between the source electrode 130 and drain electrode 140 through the channel of the transistor element included therein is relatively low. The low on-resistance allows for a large current between the source electrode 130 and drain electrode 140 of the semiconductor device 100B, and enables the semiconductor device 100B to have a high output.

Here, an example of a method for forming regrown regions such as the n-type semiconductor regions 181 and 182 will be described with reference to FIG.
2A to 2D are diagrams for explaining an example of a method for forming a regrowth region, each of which shows a schematic cross-sectional view of a main part in each step of forming a regrowth region.

First, as shown in FIG. 2(A), a semiconductor layer 110 is prepared in which an electron supply layer 112 is provided on an electron transit layer 111, and a mask 190 having an opening 190a is formed on the electron supply layer 112.

The semiconductor layer 110 is prepared, for example, by growing an electron supply layer 112 such as AlGaN on an electron transit layer 111 such as GaN grown on a base substrate (not shown) using the MOCVD method. In the semiconductor layer 110, an inactive region 150 is formed by ion implantation of Ar, and an active region 160 defined by the inactive region 150 is formed. A mask 190 is formed on such a semiconductor layer 110.

For the mask 190, an insulating film such as SiN (silicon nitride) is used. For example, the mask 190 made of SiN or the like is formed on the electron supply layer 112 using a plasma CVD method or the like. An opening 190a is formed in the mask 190 by photolithography and dry etching such as RIE (Reactive Ion Etching) using F (fluorine)-based gas, corresponding to the portion of the semiconductor layer 110 that forms the re-growth region. The opening 190a is formed in the portion of the semiconductor layer 110 in the active region 160.

2B, the portion of the semiconductor layer 110 exposed from the opening 190a of the mask 190 is removed by a dry etching technique such as RIE using Cl (chlorine)-based gas, forming a recess 170 (corresponding to the recess 171 or recess 172 in FIG. 1B above). The recess 170 is formed, for example, so as to penetrate the electron supply layer 112 of the semiconductor layer 110 to reach the electron transit layer 111, and so that the bottom surface of the recess 170 is located deeper than the 2DEG 1a generated in the electron transit layer 111.

2C, an n-type semiconductor region 180 (corresponding to the n-type semiconductor region 181 or the n-type semiconductor region 182 in FIG. 1B) such as n-type GaN is regrown as a regrown region in the recess 170 formed in the semiconductor layer 110 by, for example, MOCVD. For example, when n-type GaN is regrown as the n-type semiconductor region 180, trimethylgallium (TMGa) and NH ₃ (ammonia) are used as main raw materials in the MOCVD method, and SiH ₄ (silane) or GeH ₄ (germane) is used as an n-type dopant raw material.

Then, as shown in FIG. 2(D), the mask 190 on the semiconductor layer 110 is removed by a wet etching technique using HF (hydrogen fluoride) or the like. This results in a structure in which an n-type semiconductor region 180 is formed as a re-grown region in the recess 170 formed in the semiconductor layer 110 of the active region 160.

However, when forming such a regrowth region, the growth rate of the n-type semiconductor region 180 may differ depending on the arrangement of the opening 190a of the mask 190 or the recess 170 formed therein. This point will be explained with reference to FIG. 3.

3 is a diagram for explaining the difference in growth rate of the re-grown region, which is a schematic plan view of a main part of a semiconductor layer on which a mask is formed.
3, that is, a mask 190 formed on a semiconductor layer 110 includes a region 191 where the openings 190a are relatively dense and a region 192 where the openings 190a are relatively sparse. In the semiconductor layer 110 in the region 191 where the openings 190a of the mask 190 are relatively dense, the recesses 170 are formed relatively densely. On the other hand, in the semiconductor layer 110 in the region 192 where the openings 190a of the mask 190 are relatively sparse, the recesses 170 are formed relatively sparsely. The mask 190 including the regions 191 and 192 is formed, and an n-type semiconductor region 180 such as n-type GaN is formed on the semiconductor layer 110 in which the recesses 170 are formed in the openings 190a by using the MOCVD method as described above.

At that time, the main raw material atoms 183 of the n-type semiconductor region 180, for example, Ga (gallium) atoms, are supplied onto the semiconductor layer 110 in the opening 190a of the mask 190, as well as onto the mask 190 outside the opening 190a. The main raw material atoms 183 supplied onto the mask 190 can diffuse onto the mask 190. When the main raw material atoms 183 diffusing onto the mask 190 move to the opening 190a, they can be consumed for the regrowth of the n-type semiconductor region 180 formed in the recess 170 of the semiconductor layer 110. When the main raw material atoms 183 diffusing onto the mask 190 move to the opening 190a and are consumed for the regrowth of the n-type semiconductor region 180, the growth rate of the n-type semiconductor region 180 regrown in the opening 190a becomes faster than when the atoms 183 do not move to the opening 190a.

In the region 192 where the openings 190a of the mask 190 are relatively sparse, the mask 190 is present over a relatively large area around the openings 190a, so the amount of the main raw material atoms 183 that diffuse over the mask 190 and move to the openings 190a is likely to be relatively large. In the region 192 where the openings 190a are relatively sparse, the number of openings 190a per unit area is small, so the amount of the main raw material atoms 183 that reach each opening 190a is likely to be large. As a result, in the region 192 where the openings 190a are relatively sparse, the growth rate of the n-type semiconductor region 180 that is regrown in the recess 170 is likely to be faster than in the region 191 where the openings 190a are relatively dense.

When the growth rate of the n-type semiconductor region 180 is increased, the amount of atoms of the dopant raw material, such as Si (silicon) atoms and Ge (germanium) atoms, that are incorporated decreases, and the resistance of the resulting n-type semiconductor region 180 tends to be high. That is, the n-type semiconductor region 180 that is regrown in the region 192 where the openings 190a of the mask 190 are relatively sparse tends to be regrown at a faster growth rate and tends to have a higher resistance than the n-type semiconductor region 180 that is regrown in the region 191 where the openings 190a are relatively dense.

When the n-type semiconductor region 180 is regrowthed by MOCVD, in addition to the main raw material atoms 183 such as Ga atoms, atoms of the dopant raw material such as Si atoms and Ge atoms may be supplied onto the mask 190. However, compared to the main raw material atoms 183, the atoms of the dopant raw material have a shorter residence (adsorption) time on the mask 190 and a shorter diffusion distance. Therefore, the probability that the atoms of the dopant raw material supplied onto the mask 190 reach the opening 190a and are consumed in the regrowth there is relatively low. As a result, in the n-type semiconductor region 180 in which the growth rate is increased by the movement of the main raw material atoms 183 supplied and diffused onto the mask 190 to the opening 190a, the amount of atoms of the dopant raw material taken in is reduced, and the resistance is likely to be high.

FIG. 4 is a diagram showing an example of the relationship between the growth rate of the re-grown region and the on-resistance of a transistor element.
In Fig. 4, the horizontal axis represents the growth rate [nm/min] of the n-type semiconductor region (regrowth region) provided in the active region and connected to the electrode (ohmic electrode) of the transistor element, and the vertical axis represents the on-resistance [Ω·mm] of the transistor element. As shown in Fig. 4, it is recognized that the on-resistance of the transistor element tends to increase as the growth rate of the n-type semiconductor region increases.

As described above, when forming a regrowth region using the MOCVD method, due to the influence of the atoms of the main raw material diffusing on the mask, differences in the growth rate of the n-type semiconductor region formed as a regrowth region in the semiconductor layer at the opening of the mask may occur. Note that such differences in the growth rate of the n-type semiconductor region may occur not only between different n-type semiconductor regions formed in one semiconductor layer, but also between n-type semiconductor regions formed in different semiconductor layers. When differences in the growth rate of the n-type semiconductor region occur, the amount of n-type dopant incorporated varies, causing differences in the resistance of the formed n-type semiconductor region. As a result, it may not be possible to stably realize a semiconductor device having a sufficiently low-resistance n-type semiconductor region connected to electrodes such as a source electrode and a drain electrode.

In view of the above, a method as shown in the following embodiment is used to suppress differences in the growth rate of the semiconductor region that is regrown in the semiconductor layer for electrode connection, and to stably realize a semiconductor device having a low-resistance semiconductor region that is connected to an electrode.

[First embodiment]
Fig. 5 is a diagram for explaining an example of a semiconductor device according to the first embodiment. Fig. 5 is a schematic cross-sectional view of a main part of the example of the semiconductor device according to the first embodiment.

The semiconductor device 1 shown in FIG. 5 is an example of a HEMT. The semiconductor device 1 includes a semiconductor layer 10, an n-type semiconductor region 21 and an n-type semiconductor region 22 provided in the active region AR1, as well as a gate electrode 30, a source electrode 40, and a drain electrode 50. The semiconductor device 1 further includes an n-type semiconductor region 61 and an n-type semiconductor region 62 provided in an inactive region AR2 of the semiconductor layer 10.

The semiconductor layer 10 includes an electron transit layer 11 and an electron supply layer 12. For example, GaN is used for the electron transit layer 11, and AlGaN is used for the electron supply layer 12. 2DEG1a is generated near the junction interface between the electron transit layer 11 and the electron supply layer 12. The 2DEG1a is generated in an active region AR1 defined by an inactive region AR2 provided in the semiconductor layer 10. The inactive region AR2 is a region formed as an element isolation region by ion implantation of Ar into the semiconductor layer 10, or the like. The active region AR1 is a region formed as an element region defined by such an element isolation region.

The n-type semiconductor region 21 and the n-type semiconductor region 22 are provided in recesses 71 and 72, respectively, provided on one surface 10a (the surface on the electron supply layer 12 side) of the semiconductor layer 10 in the active region AR1. The recesses 71 and 72 are provided, for example, so that they penetrate the electron supply layer 12 to reach the electron transit layer 11, and the bottom surfaces of the recesses 71 and 72 are located deeper than the 2DEG 1a generated in the electron transit layer 11. The n-type semiconductor region 21 and the n-type semiconductor region 22 are regrown and formed in the recesses 71 and 72, for example, by using the MOCVD method. For example, n-type GaN is used for the n-type semiconductor region 21 and the n-type semiconductor region 22. The n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 are also referred to as regrown regions, regrown layers, etc.

The gate electrode 30 is provided on the surface 10a side of the semiconductor layer 10 in the active region AR1. In the example of FIG. 5, the gate electrode 30 is provided on the surface 10a (electron supply layer 12) of the semiconductor layer 10. The gate electrode 30 is located between the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1, and is provided so as not to be connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 (and the source electrode 40 and the drain electrode 50 provided thereon). Metals such as Ni (nickel) and Au (gold) are used for the gate electrode 30. The gate electrode 30 is provided so as to function as a Schottky electrode.

The source electrode 40 and the drain electrode 50 are provided on the surface 10a side of the semiconductor layer 10 so as to sandwich the gate electrode 30. The source electrode 40 is located on the n-type semiconductor region 21 provided in the recess 71 of the semiconductor layer 10 and is provided so as to be connected to the n-type semiconductor region 21. The drain electrode 50 is located on the n-type semiconductor region 22 provided in the recess 72 of the semiconductor layer 10 and is provided so as to be connected to the n-type semiconductor region 22. The source electrode 40 and the drain electrode 50 are made of a metal such as Ti (titanium) or Al (aluminum). The source electrode 40 and the drain electrode 50 are provided so as to function as ohmic electrodes.

During operation of the semiconductor device 1, a predetermined voltage is supplied between the source electrode 40 and the drain electrode 50, and a predetermined gate voltage is supplied to the gate electrode 30. A channel through which carrier electrons are transported is formed in the electron transit layer 11 between the source electrode 40 and the drain electrode 50, and the transistor function of the semiconductor device 1 is realized.

In the semiconductor device 1, the 2DEG1a of the channel generated in the electron transit layer 11 is connected to the relatively low-resistance n-type semiconductor region 21 and n-type semiconductor region 22, and the resistance between the 2DEG1a and the n-type semiconductor region 21 and n-type semiconductor region 22 is reduced. The source electrode 40 and drain electrode 50 are connected to the relatively low-resistance n-type semiconductor region 21 and n-type semiconductor region 22, respectively. This makes the resistance between the 2DEG1a and the source electrode 40 and drain electrode 50 relatively low. Therefore, in the semiconductor device 1, the on-resistance between the source electrode 40 and drain electrode 50 via the channel of the element (transistor element) having the transistor function is relatively low. The lower on-resistance enables a large current between the source electrode 40 and drain electrode 50 of the semiconductor device 1, and enables the semiconductor device 1 to have a high output.

In the semiconductor device 1, an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided in an inactive region AR2 that is adjacent to and defines an active region AR1 in which a transistor element is formed. The n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are made of n-type GaN, for example, as are the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1. The n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are also referred to as a dummy re-growth region, a dummy re-growth layer, or the like.

The n-type semiconductor region 61 and the n-type semiconductor region 62 are respectively provided in recesses 81 and 82 provided on the surface 10a side of the semiconductor layer 10 in the inactive region AR2. The recesses 81 and 82 are provided intermittently or continuously, for example, so as to surround the active region AR1. The recesses 81 and 82 are provided, for example, at the same or equal depth as the recesses 71 and 72 in which the n-type semiconductor region 21 and the n-type semiconductor region 22 are respectively provided. The n-type semiconductor region 61 and the n-type semiconductor region 62 are regrown and formed in such recesses 81 and 82, for example, by using the MOCVD method. At this time, the n-type semiconductor region 61 and the n-type semiconductor region 62 are formed simultaneously with the n-type semiconductor region 21 and the n-type semiconductor region 22. As described below, with respect to the surface 10a of the semiconductor layer 10, the end faces 61a and 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 on the surface 10a side are positioned higher than the end faces 21a and 22a of the n-type semiconductor region 21 and the n-type semiconductor region 22 on the surface 10a side.

The n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are provided so as to be located away from the active region AR1. That is, the n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the semiconductor layer 10 so as not to contact the active region AR1 (and the n-type semiconductor region 21 and the n-type semiconductor region 22 provided therein). It is preferable that the n-type semiconductor region 61 and the n-type semiconductor region 62 (recess 81 and recess 82) are provided at a position in the inactive region AR2 adjacent to the active region AR1 where the distance D1 from the active region AR1 is 50 μm or more. This is because if the n-type semiconductor region 61 and the n-type semiconductor region 62 are located in a range where the distance D1 from the active region AR1 is less than 50 μm, the following may occur. That is, the operation of the transistor element may be affected by electrical interactions (such as capacitive coupling) between the n-type semiconductor region 61 and the n-type semiconductor region 62 in the semiconductor layer 10 and the n-type semiconductor region 21 and the n-type semiconductor region 22 and the 2DEG 1a in the active region AR1. However, as described below, it is preferable that the n-type semiconductor region 61 and the n-type semiconductor region 62 are provided at a distance of 500 μm or less from the n-type semiconductor region 21 and the n-type semiconductor region 22 (recesses 71 and 72) provided in the active region AR1, that is, the distance D1 from the active region AR1 in the example of FIG. 5.

When the n-type semiconductor region 21 and n-type semiconductor region 22 and the n-type semiconductor region 61 and n-type semiconductor region 62 of the semiconductor device 1 having the above configuration are regrown by MOCVD, a mask having a group of openings is formed on the surface 10a of the semiconductor layer 10 at the portion where they are regrown. Recesses 71 and 72 and recesses 81 and 82 are formed in the group of openings of this mask, and the n-type semiconductor region 21 and n-type semiconductor region 22 and the n-type semiconductor region 61 and n-type semiconductor region 62 are regrown in these, respectively. The atoms of the main raw material (Ga atoms, etc.) of the n-type semiconductor region 21 and n-type semiconductor region 22 and the n-type semiconductor region 61 and n-type semiconductor region 62 are supplied onto the mask in addition to the recesses 71 and 72 and recesses 81 and 82. The atoms of the main raw material supplied onto the mask can diffuse onto the mask.

Incidentally, the atoms of the dopant material have a shorter residence time on the mask and a shorter diffusion distance than the atoms of the main material, and therefore do not diffuse on the mask as much as the atoms of the main material do.
The atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 move to the openings of the mask corresponding to the recesses 81 and 82 provided in the inactive region AR2, and are easily consumed in the regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62. As a result, the atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 are prevented from moving to the openings of the mask corresponding to the recesses 71 and 72 provided in the active region AR1, and are prevented from being consumed in the regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22. Therefore, the growth rates of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 are prevented from becoming faster due to the influence of the atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2, and are stabilized.

In order to make the atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 more likely to be consumed in the regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62 and less likely to be consumed in the regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22, the arrangement of the opening group of the mask is adjusted. As a result, the arrangement of the recesses 71 and 72 and the recesses 81 and 82 formed in the semiconductor layer 10 is adjusted. It is preferable that the recesses 81 and 82 (n-type semiconductor region 61 and n-type semiconductor region 62) are provided at a position within 500 μm of the recesses 71 and 72 (n-type semiconductor region 21 and n-type semiconductor region 22). This is because if the distance of the recesses 81 and 82 from the recesses 71 and 72 exceeds 500 μm, the following is likely to occur. That is, the atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 move to the openings in the mask corresponding to the recesses 71 and 72, and are consumed in the regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22, which tends to accelerate their growth rate.

The atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 are more likely to be consumed in the regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62, and less likely to be consumed in the regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22. Therefore, the growth rate of the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 is relatively faster than the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1. As a result, the end faces 61a and 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 on the face 10a side are higher than the end faces 21a and 22a of the n-type semiconductor region 21 and the n-type semiconductor region 22 on the face 10a side with respect to the face 10a of the semiconductor layer 10.

As described above, the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 are prevented from increasing in growth rate, and are stabilized. As a result, the amount of dopant taken up by the n-type semiconductor region 21 and the n-type semiconductor region 22 is prevented from decreasing, and the resistance of the n-type semiconductor region 21 and the n-type semiconductor region 22 is prevented from increasing. This allows a semiconductor device 1 to be stably realized, which has the n-type semiconductor region 21 and the n-type semiconductor region 22, which are connected to the source electrode 40 and the drain electrode 50 and have sufficiently low resistance.

The n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2, which have a faster growth rate than the n-type semiconductor region 21 and n-type semiconductor region 22 provided in the active region AR1, incorporate less dopant than the n-type semiconductor region 21 and n-type semiconductor region 22.

As described above, the method of providing an n-type semiconductor region (dummy regrowth region) in an inactive region to suppress the growth rate of an n-type semiconductor region (regrowth region) provided in an active region is effective when the n-type semiconductor regions provided in the active region are sparsely arranged (when the growth rate tends to be fast). However, this method is also applicable when the n-type semiconductor regions provided in the active region are densely arranged. By providing an n-type semiconductor region in an inactive region, it is possible to suppress and stabilize the growth rate of the n-type semiconductor region provided in the active region not only when the n-type semiconductor regions provided in the active region are sparsely arranged, but also when they are dense.

In addition, by providing an n-type semiconductor region (dummy regrowth region) in the inactive region, it is possible to stabilize the growth rate of multiple n-type semiconductor regions (regrowth regions) provided in the active region and suppress the difference in growth rate that occurs between different n-type semiconductor regions provided in the active region. Furthermore, it is possible to suppress the difference in growth rate that occurs not only between n-type semiconductor regions provided in the active region of one semiconductor layer, but also between n-type semiconductor regions provided in the active regions of different semiconductor layers.

[Second embodiment]
6 and 7 are diagrams for explaining an example of a semiconductor device according to the second embodiment. Fig. 6 is a schematic plan view of a main part of the semiconductor device according to the second embodiment. Fig. 7 is a schematic cross-sectional view of a main part of the semiconductor device according to the second embodiment. Fig. 7 is a schematic cross-sectional view taken along line VII-VII of Fig. 6.

The semiconductor device 1A shown in Figures 6 and 7 is an example of a HEMT. As shown in Figures 6 and 7, the semiconductor device 1A includes a semiconductor layer 10A, an n-type semiconductor region 21 and an n-type semiconductor region 22 (regrowth region) provided in the active region AR1, as well as a gate electrode 30, a source electrode 40, and a drain electrode 50. The semiconductor device 1A further includes an n-type semiconductor region 61 and an n-type semiconductor region 62 (dummy regrowth region) provided in the inactive region AR2 of the semiconductor layer 10A.

As shown in FIG. 7, the semiconductor layer 10A of the semiconductor device 1A includes a substrate 13, an initial layer 14, an electron transit layer 11, a spacer layer 15, and an electron supply layer 12.
Here, a substrate such as SiC (silicon carbide), Si, sapphire, GaN, AlN (aluminum nitride), diamond, etc. is used as the substrate 13. The substrate 13 may have a single-layer structure of one type of substrate, or a laminate structure of two or more types of substrates.

The initial layer 14 is provided on one surface 13a of the substrate 13. The initial layer 14 is made of a nitride semiconductor such as AlN, GaN, or AlGaN. The initial layer 14 may be a single-layer structure of one type of nitride semiconductor, or a layered structure of two or more types of nitride semiconductors.

The electron transit layer 11 is provided on the surface 14a of the initial layer 14 opposite the substrate 13 side. The electron transit layer 11 is made of a nitride semiconductor such as GaN or AlGaN. The electron transit layer 11 may be a single-layer structure of one type of nitride semiconductor, or a laminate structure of two or more types of nitride semiconductors. For example, the electron transit layer 11 is made of i-type GaN.

The spacer layer 15 is provided on the surface 11a of the electron transit layer 11 opposite the initial layer 14. The spacer layer 15 is made of a nitride semiconductor such as AlN or AlGaN. The spacer layer 15 may be a single-layer structure of one type of nitride semiconductor, or a laminate structure of two or more types of nitride semiconductors.

The electron supply layer 12 is provided on the surface 15a of the spacer layer 15 opposite the electron transit layer 11. The electron supply layer 12 is made of a nitride semiconductor such as AlGaN, InAlN (indium aluminum nitride), InAlGaN (indium aluminum gallium nitride), AlN, or ScAlN (scandium aluminum nitride). The electron supply layer 12 may be a single-layer structure of one type of nitride semiconductor, or a laminate structure of two or more types of nitride semiconductors.

In the semiconductor device 1A, 2DEG1a is generated near the junction interface between the electron transit layer 11 and the spacer layer 15. The 2DEG1a is generated in an active region AR1 defined by an inactive region AR2 provided in the semiconductor layer 10A. The inactive region AR2 is a region formed as an element isolation region by ion implantation of Ar into the semiconductor layer 10A or the like. The active region AR1 is a region formed as an element region defined by such an element isolation region. The inactive region AR2 is provided adjacent to the active region AR1 so as to surround the active region AR1. A transistor element having a transistor function is formed in the active region AR1 in which the 2DEG1a is generated.

The semiconductor layer 10A is formed, for example, by using the MOCVD method, by growing an initial layer 14 on the surface 13a of the substrate 13, growing an electron transit layer 11 on the surface 14a, growing a spacer layer 15 on the surface 11a, and growing an electron supply layer 12 on the surface 15a.

Although not shown here, the semiconductor layer 10A may further include other layers, such as a cap layer made of a nitride semiconductor such as GaN, provided on the surface 12a of the electron supply layer 12 opposite the spacer layer 15.

An n-type semiconductor region 21 and an n-type semiconductor region 22 are provided on the surface 10a (surface 12a of the electron supply layer 12 in this example) side of the semiconductor layer 10A in the active region AR1. The n-type semiconductor region 21 and the n-type semiconductor region 22 are provided in recesses 71 and 72 provided on the surface 10a side of the semiconductor layer 10A in the active region AR1, respectively. For example, as shown in FIG. 7, the recesses 71 and 72 are provided so that they penetrate the electron supply layer 12 and the spacer layer 15 to reach the electron transit layer 11, and the bottom surfaces of the recesses 71 and 72 are located deeper than the 2DEG 1a generated in the electron transit layer 11. The n-type semiconductor region 21 and the n-type semiconductor region 22 are regrown and formed in the recesses 71 and 72, respectively, by using, for example, the MOCVD method. For example, n-type GaN is used for the n-type semiconductor region 21 and the n-type semiconductor region 22.

The gate electrode 30 is provided on the surface 10a side of the semiconductor layer 10A. In the example of FIG. 6 and FIG. 7, the gate electrode 30 is provided on the surface 10a (electron supply layer 12) of the semiconductor layer 10A in the active region AR1 and the inactive region AR2. The gate electrode 30 is provided so that a part of it is located between the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1, and is not connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 (as well as the source electrode 40 and the drain electrode 50 provided thereon). Metals such as Ni and Au are used for the gate electrode 30. The gate electrode 30 is provided so as to function as a Schottky electrode. Note that a gate insulating film (not shown) using an oxide, nitride, oxynitride, or the like may be interposed between the gate electrode 30 and the surface 10a of the semiconductor layer 10A.

The source electrode 40 and the drain electrode 50 are provided on the surface 10a side of the semiconductor layer 10A so as to sandwich the gate electrode 30. The source electrode 40 is provided so that a part of it is located on the n-type semiconductor region 21 provided in the recess 71 of the semiconductor layer 10A and is connected to the n-type semiconductor region 21. The drain electrode 50 is provided so that a part of it is located on the n-type semiconductor region 22 provided in the recess 72 of the semiconductor layer 10A and is connected to the n-type semiconductor region 22. The source electrode 40 and the drain electrode 50 are made of a metal such as Ti or Al. The source electrode 40 and the drain electrode 50 are provided so as to function as ohmic electrodes.

During operation of the semiconductor device 1A, a predetermined voltage is supplied between the source electrode 40 and the drain electrode 50, and a predetermined gate voltage is supplied to the gate electrode 30. A channel through which carrier electrons are transported is formed in the electron transit layer 11 between the source electrode 40 and the drain electrode 50, realizing the transistor function of the semiconductor device 1A.

In the semiconductor device 1A, the 2DEG1a of the channel generated in the electron transit layer 11 is connected to the relatively low-resistance n-type semiconductor region 21 and n-type semiconductor region 22, and the resistance between the 2DEG1a and the n-type semiconductor region 21 and n-type semiconductor region 22 is reduced. As a result, in the semiconductor device 1A, the resistance between the 2DEG1a and the source electrode 40 and the drain electrode 50 connected via the n-type semiconductor region 21 and n-type semiconductor region 22 is reduced, and the on-resistance of the transistor element is reduced. In the semiconductor device 1A, the n-type semiconductor region 21 and n-type semiconductor region 22 are provided so as to penetrate the electron supply layer 12 and further penetrate the spacer layer 15 and be connected to the 2DEG1a of the electron transit layer 11. Even if the spacer layer 15 is interposed between the 2DEG 1a and the surface 10a of the semiconductor layer 10A in addition to the electron supply layer 12, the n-type semiconductor region 21 and the n-type semiconductor region 22 effectively reduce the resistance between the 2DEG 1a and the source electrode 40 and the drain electrode 50.

In the semiconductor device 1, an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided in an inactive region AR2 that is adjacent to and defines an active region AR1 in which a transistor element is formed. The n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are made of, for example, n-type GaN, similar to the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1.

The n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in recesses 81 and 82, respectively, provided on the surface 10a side of the semiconductor layer 10A in the inactive region AR2. The recesses 81 and 82 are provided, for example, so as to surround the active region AR1. In the example of FIG. 6 and FIG. 7, the recesses 81 and 82, which are U-shaped in plan view, are provided on both sides of the active region AR1 in the inactive region AR2. The recesses 81 and 82 are provided, for example, as shown in FIG. 7, to the same or equivalent depth as the recesses 71 and 72 in which the n-type semiconductor region 21 and the n-type semiconductor region 22 are provided, respectively.

In these recesses 81 and 82, n-type semiconductor regions 61 and 62 are regrown and formed, respectively, using, for example, the MOCVD method. At this time, the n-type semiconductor regions 61 and 62 are formed simultaneously with the n-type semiconductor regions 21 and 22. With respect to the face 10a of the semiconductor layer 10A, the end faces 61a and 62a of the n-type semiconductor regions 61 and 62 on the face 10a side are positioned higher than the end faces 21a and 22a of the n-type semiconductor regions 21 and 22 on the face 10a side.

The n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2 are provided so as to be located away from the active region AR1. The n-type semiconductor region 61 and the n-type semiconductor region 62 (recesses 81 and 82) are preferably provided in the inactive region AR2 adjacent to the active region AR1 at a position 50 μm or more away from the active region AR1. This is to suppress the electrical action (capacitive coupling, etc.) between the n-type semiconductor region 61 and the n-type semiconductor region 62 in the semiconductor layer 10A and the n-type semiconductor region 21 and the n-type semiconductor region 22 and the 2DEG1a in the active region AR1, and to suppress the influence of the electrical action on the operation of the transistor element. However, as described below, it is preferable that the n-type semiconductor region 61 and the n-type semiconductor region 62 (recesses 81 and 82) are provided at a position within 500 μm of the n-type semiconductor region 21 and the n-type semiconductor region 22 (recesses 71 and 72) provided in the active region AR1.

The n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the inactive region AR2 so as not to come into contact with the gate electrode 30. This reduces the effect of the n-type semiconductor region 61 and the n-type semiconductor region 62 on the gate electrode 30, and reduces the effect of the effect on the gate electrode 30 on the operation of the transistor element.

In the semiconductor device 1A having the above configuration, the n-type semiconductor region 21 and the n-type semiconductor region 22 connected to the source electrode 40 and the drain electrode 50 are provided in the active region AR1, and the n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the inactive region AR2. By providing the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 together with the n-type semiconductor region 61 and the n-type semiconductor region 62 during regrowth is prevented from increasing. Details of the regrowth will be described later. By preventing the growth rate from increasing during regrowth, the amount of dopant taken into the n-type semiconductor region 21 and the n-type semiconductor region 22 is prevented from decreasing, and the resistance of the n-type semiconductor region 21 and the n-type semiconductor region 22 is prevented from increasing. As a result, the semiconductor device 1A having the n-type semiconductor region 21 and the n-type semiconductor region 22, which are connected to the source electrode 40 and the drain electrode 50 and have sufficiently low resistance, is stably realized.

Next, a method for forming the semiconductor device 1A having the above configuration will be described.
8 to 15 are diagrams for explaining an example of a method for forming a semiconductor device according to the second embodiment. Hereinafter, an example of each process for forming a semiconductor device will be described in order with reference to FIGS.

Figure 8 is a diagram showing an example of a semiconductor layer preparation process. Figure 8(A) shows a schematic plan view of a main part of an example of a semiconductor layer preparation process. Figure 8(B) shows a schematic cross-sectional view of a main part of an example of a semiconductor layer preparation process. Figure 8(B) is a schematic cross-sectional view taken along line VIII-VIII of Figure 8(A).

For example, a semiconductor layer 10A as shown in FIG. 8(A) and FIG. 8(B) is prepared. For example, using the MOCVD method, an initial layer 14 is grown on the surface 13a of a substrate 13, an electron transit layer 11 is grown on the surface 14a, a spacer layer 15 is grown on the surface 11a, and an electron supply layer 12 is grown on the surface 15a. A 2DEG 1a is generated near the junction interface between the electron transit layer 11 and the spacer layer 15.

Figure 9 shows an example of a process for forming an inactive region and an active region. Figure 9(A) shows a schematic plan view of a main part of an example of a process for forming an inactive region and an active region. Figure 9(B) shows a schematic cross-sectional view of a main part of an example of a process for forming an inactive region and an active region. Figure 9(B) is a schematic cross-sectional view taken along line IX-IX of Figure 9(A).

After the semiconductor layer 10A is prepared, for example, as shown in FIG. 9(A) and FIG. 9(B), an inactive region AR2 is formed, thereby forming an active region AR1 defined by the formed inactive region AR2.

For example, a resist pattern (not shown) having openings in the portions of the semiconductor layer 10A that form the inactive regions AR2 is formed on the surface 10a of the semiconductor layer 10A by photolithography. Then, Ar ions are implanted into the portions of the semiconductor layer 10A exposed through the openings of the resist pattern. Inactive regions AR2 are formed in the portions of the semiconductor layer 10A where Ar ions are implanted. The Ar ions are implanted so as to extend to a position deeper than the 2DEG1a generated in the electron transit layer 11. In the portions of the semiconductor layer 10A where Ar ions are not implanted, active regions AR1 defined by the inactive regions AR2 are formed. After Ar ions are implanted, the resist pattern is removed using an organic solvent or the like.

In addition, instead of Ar ion implantation, the portions of the semiconductor layer 10A exposed through the openings in the resist pattern can be removed by dry etching using a Cl-based gas, such as RIE, to form inactive regions.

Figure 10 shows an example of a mask formation process. Figure 10(A) shows a schematic plan view of the main parts of an example of the mask formation process. Figure 10(B) shows a schematic cross-sectional view of the main parts of an example of the mask formation process. Figure 10(B) is a schematic cross-sectional view taken along line X-X of Figure 10(A).

After the inactive region AR2 and the active region AR1 are formed, for example, as shown in FIG. 10(A) and FIG. 10(B), a mask 90 having a group of openings 90a is formed on the surface 10a of the semiconductor layer 10A at a predetermined portion of the semiconductor layer 10A. The group of openings 90a of the mask 90 is provided in the portion of the semiconductor layer 10A where the n-type semiconductor region 21 and the n-type semiconductor region 22 (or the recesses 71 and 72) provided in the active region AR1 are to be formed. The group of openings 90a of the mask 90 is further provided in the portion of the semiconductor layer 10A where the n-type semiconductor region 61 and the n-type semiconductor region 62 (or the recesses 81 and 82) provided in the inactive region AR2 are to be formed.

For the mask 90, an insulating film such as SiN is used. For example, an insulating film such as SiN is formed on the surface 10a of the semiconductor layer 10A by using a plasma CVD method. Next, a resist pattern (not shown) having openings corresponding to the portions of the semiconductor layer 10A where the n-type semiconductor regions 21 and 22 are to be formed and the portions where the n-type semiconductor regions 61 and 62 are to be formed is formed on the insulating film by photolithography. Then, the insulating film exposed from the openings of the resist pattern is removed by dry etching such as RIE using an F-based gas. As a result, a group of openings 90a of the mask 90 is formed as shown in FIG. 10(A) and FIG. 10(B).

Although not shown here, the resist pattern used when forming the group of openings 90a may remain on the mask 90 after the group of openings 90a is formed.
11A and 11B are diagrams showing an example of a recess forming step. Fig. 11A is a schematic plan view of a main part of an example of the recess forming step. Fig. 11B is a schematic cross-sectional view of a main part of an example of the recess forming step. Fig. 11B is a schematic cross-sectional view taken along line XI-XI of Fig. 11A.

After forming the mask 90 having the openings 90a, as shown in FIGS. 11(A) and 11(B), the portions of the semiconductor layer 10A exposed from the openings 90a are removed by dry etching such as RIE using Cl-based gas. As a result, recesses 71 and 72 that communicate with the openings 90a of the mask 90 are formed on the surface 10a side of the semiconductor layer 10A in the active region AR1. Recesses 81 and 82 that communicate with the openings 90a of the mask 90 are formed on the surface 10a side of the semiconductor layer 10A in the inactive region AR2.

The recesses 71 and 72 in the active region AR1 are formed so that they penetrate the electron supply layer 12 and spacer layer 15 of the semiconductor layer 10A to reach the electron transit layer 11, and the bottom surfaces of the recesses 71 and 72 are located deeper than the 2DEG 1a generated in the electron transit layer 11. As an example, the recesses 71 and 72 are formed so that their bottom surfaces are located at a depth of 60 nm or less from the surface 11a of the electron transit layer 11 toward the initial layer 14 side. The recesses 81 and 82 in the inactive region AR2 are formed at the same time as the recesses 71 and 72 in the active region AR1, at the same or the same depth, so that they penetrate the electron supply layer 12 and spacer layer 15 of the semiconductor layer 10A in the inactive region AR2 to reach the electron transit layer 11.

After recesses 71 and 72 and recesses 81 and 82 are formed, if the resist pattern used to form the openings 90a remains on the mask 90, the resist pattern is removed using an organic solvent or the like.

Figure 12 shows an example of a process for forming an n-type semiconductor region. Figure 12(A) shows a schematic plan view of a main part of an example of a process for forming an n-type semiconductor region. Figure 12(B) shows a schematic cross-sectional view of a main part of an example of a process for forming an n-type semiconductor region. Figure 12(B) is a schematic cross-sectional view taken along line XII-XII of Figure 12(A).

After the recesses 71 and 72 and the recesses 81 and 82 are formed, the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are formed therein, respectively, as shown in FIG. 12(A) and FIG. 12(B).

For example, using the MOCVD method, n-type semiconductor regions 21 and 22 and n-type semiconductor regions 61 and 62 are regrown in recesses 71 and 72 and recesses 81 and 82 exposed from the openings 90a of the mask 90. For example, n-type GaN is regrown as n-type semiconductor regions 21 and 22 and n-type semiconductor regions 61 and 62. N-type semiconductor regions 21 and 22 and n-type semiconductor regions 61 and 62 are regrown in recesses 71 and 72 and recesses 81 and 82 in the same regrowth process using the MOCVD method.

When the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are regrown using the MOCVD method, the atoms of the main raw materials are supplied to the recesses 71 and 72, the recesses 81 and 82, and also onto the mask 90.

Incidentally, the atoms of the dopant material have a shorter residence time on the mask and a shorter diffusion distance than the atoms of the main material, and therefore do not diffuse on the mask as much as the atoms of the main material do.
Atoms of the main raw material supplied onto the mask 90 corresponding to the inactive region AR2 and diffusing thereon move to the openings 90a of the mask 90 corresponding to the recesses 81 and 82 of the inactive region AR2, and are easily consumed in the regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62. As a result, it is possible to prevent the atoms of the main raw material diffusing on the mask 90 corresponding to the inactive region AR2 from moving to the openings 90a of the mask 90 corresponding to the recesses 71 and 72 of the active region AR1 and being consumed in the regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22. Therefore, it is possible to prevent the growth rates of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 from becoming faster due to the influence of the atoms of the main raw material diffusing on the mask 90 corresponding to the inactive region AR2.

In order to make the atoms of the main raw material diffusing on the mask 90 corresponding to the inactive region AR2 more likely to be consumed in the regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62 and less likely to be consumed in the regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22, the arrangement of the openings 90a group is adjusted (FIG. 10). As a result, the arrangement of the recesses 71 and 72 and the recesses 81 and 82 is adjusted (FIG. 11). It is preferable that the recesses 81 and 82 (n-type semiconductor region 61 and n-type semiconductor region 62) are provided at a position within 500 μm of the recesses 71 and 72 (n-type semiconductor region 21 and n-type semiconductor region 22). This is because if the distance of the recesses 81 and 82 from the recesses 71 and 72 exceeds 500 μm, the following is likely to occur. That is, the atoms of the main raw material diffusing on the mask 90 corresponding to the inactive region AR2 move to the openings 90a corresponding to the recesses 71 and 72, and are consumed in the regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22, which tends to speed up their growth rate.

From this perspective, the arrangement of the openings 90a of the mask 90 is adjusted, and the arrangements of the recesses 71 and 72 and the recesses 81 and 82 are adjusted. In the recesses 71 and 72 and the recesses 81 and 82 whose arrangements have been adjusted, the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are regrown, respectively, in the same regrowth process using the MOCVD method. This prevents the growth rate of the n-type semiconductor regions 21 and 22 provided in the active region AR1 from increasing due to the influence of the atoms of the main material diffusing on the mask 90 corresponding to the inactive region AR2, and stabilizes it.

The atoms of the main raw material diffusing on the mask 90 corresponding to the inactive region AR2 are more likely to be consumed in the regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62, and less likely to be consumed in the regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22. Therefore, the growth rate of the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 is relatively faster than the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1. As a result, the end faces 61a and 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 on the face 10a side are higher than the end faces 21a and 22a of the n-type semiconductor region 21 and the n-type semiconductor region 22 on the face 10a side with respect to the face 10a of the semiconductor layer 10A.

As described above, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 is prevented from increasing and stabilized, thereby preventing a decrease in the amount of dopant taken up by the n-type semiconductor region 21 and the n-type semiconductor region 22. By preventing a decrease in the amount of dopant taken up, the resistance of the n-type semiconductor region 21 and the n-type semiconductor region 22 is prevented from increasing. As a result, the n-type semiconductor region 21 and the n-type semiconductor region 22 having a sufficiently low resistance are formed stably.

The n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2, which have a faster growth rate than the n-type semiconductor region 21 and n-type semiconductor region 22 provided in the active region AR1, incorporate less dopant than the n-type semiconductor region 21 and n-type semiconductor region 22.

Figure 13 shows an example of a mask removal process. Figure 13(A) shows a schematic plan view of the main parts of an example of the mask removal process. Figure 13(B) shows a schematic cross-sectional view of the main parts of an example of the mask removal process. Figure 13(B) is a schematic cross-sectional view taken along line XIII-XIII in Figure 13(A).

After the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are formed, the mask 90 is removed as shown in FIG. 13(A) and FIG. 13(B). For example, the mask 90 is removed by wet etching using HF or the like.

Figure 14 shows an example of a process for forming a source electrode and a drain electrode. Figure 14(A) shows a schematic plan view of a main part of an example of a process for forming a source electrode and a drain electrode. Figure 14(B) shows a schematic cross-sectional view of a main part of an example of a process for forming a source electrode and a drain electrode. Figure 14(B) is a schematic cross-sectional view taken along line XIV-XIV of Figure 14(A).

After removing the mask 90, the source electrode 40 and the drain electrode 50 are formed as shown in FIG. 14(A) and FIG. 14(B). For example, a resist pattern (not shown) having openings at the portions where the source electrode 40 and the drain electrode 50 are to be formed is first formed by photolithography. The openings of this resist pattern are provided so as to lead to the n-type semiconductor region 21 and the n-type semiconductor region 22 regrown in the recesses 71 and 72 of the semiconductor layer 10A of the active region AR1, respectively. After forming the resist pattern, a metal is evaporated on the resist pattern and in the openings by vacuum evaporation. As an example, Ti is evaporated to a thickness of 2 nm to 50 nm, and Al is evaporated thereon to a thickness of 100 nm to 300 nm. After the evaporation of the metal, the resist pattern is removed together with the metal evaporated thereon by lift-off technology. As a result, the source electrode 40 and the drain electrode 50 connected to the n-type semiconductor region 21 and the n-type semiconductor region 22, respectively, are formed. Then, a heat treatment (alloying process) is performed in a nitrogen atmosphere at 500°C to 900°C to establish an ohmic connection between the source electrode 40 and the drain electrode 50.

Note that as long as a portion of the source electrode 40 and the drain electrode 50 is connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1, the other portion may be located in the inactive region AR2.

Figure 15 shows an example of a process for forming a gate electrode. Figure 15(A) shows a schematic plan view of a main part of an example of a process for forming a gate electrode. Figure 15(B) shows a schematic cross-sectional view of a main part of an example of a process for forming a gate electrode. Figure 15(B) is a schematic cross-sectional view taken along line XV-XV of Figure 15(A).

After the source electrode 40 and the drain electrode 50 are formed, the gate electrode 30 is formed as shown in FIG. 15(A) and FIG. 15(B). For example, a resist pattern (not shown) having an opening at the portion where the gate electrode 30 is to be formed is first formed by photolithography. The opening of this resist pattern is provided so as to lead to the semiconductor layer 10A (if a gate insulating film is formed, the gate insulating film) of the active region AR1 between the source electrode 40 and the drain electrode 50. After the resist pattern is formed, a metal is evaporated on the resist pattern and in the opening by vacuum evaporation. As an example, Ni is evaporated to a thickness of 5 nm to 30 nm, and Au is evaporated thereon to a thickness of 100 nm to 300 nm. After the evaporation of the metal, the resist pattern is removed together with the evaporated metal by lift-off technology. As a result, the gate electrode 30 is formed. After the gate electrode 30 is formed, a heat treatment may be performed.

The gate electrode 30 is not limited to being provided within the active region AR1, but may be extended outward from the active region AR1 with a part of it being provided in the inactive region AR2.
Furthermore, when a gate insulating film is interposed between the gate electrode 30 and the semiconductor layer 10A, the gate insulating film is formed before the gate electrode 30 is formed.

Through the above steps, a semiconductor device 1A having a configuration as shown in FIGS. 15(A) and 15(B) is formed.
In the semiconductor device 1A, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 is suppressed from increasing (FIG. 12). As a result, the amount of dopant taken into the n-type semiconductor region 21 and the n-type semiconductor region 22 is suppressed from decreasing, and the resistance of the n-type semiconductor region 21 and the n-type semiconductor region 22 is suppressed from increasing due to the decrease in the amount of dopant taken. As a result, the n-type semiconductor region 21 and the n-type semiconductor region 22 having a sufficiently low resistance are stably formed. The source electrode 40 and the drain electrode 50 are respectively connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 having a sufficiently low resistance, and the resistance between them and the 2DEG 1a is reduced. As a result, the semiconductor device 1A is realized to have a large current and a high output. According to the above method, the semiconductor device 1A having the n-type semiconductor region 21 and the n-type semiconductor region 22 having a sufficiently low resistance and connected to the source electrode 40 and the drain electrode 50 is stably realized.

FIG. 16 is a diagram showing an example of the relationship between the growth rate of the re-growth region and the on-resistance of a transistor element according to the second embodiment.
In Fig. 16, the horizontal axis represents the growth rate [nm/min] of the n-type semiconductor region (regrowth region) provided in the active region and connected to the electrode (ohmic electrode) of the transistor element, and the vertical axis represents the on-resistance [Ω·mm] of the transistor element. Part P of Fig. 16 shows an example of the relationship between the growth rate of the n-type semiconductor region (regrowth region) in the active region and the on-resistance of the transistor element when an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. For comparison, part Q of Fig. 16 shows an example of the relationship between the growth rate of the n-type semiconductor region in the active region and the on-resistance of the transistor element when no n-type semiconductor region is provided in the inactive region.

As shown in FIG. 16, when an n-type semiconductor region in the inactive region is provided together with an n-type semiconductor region in the active region (part P), the growth rate of the n-type semiconductor region in the active region is reduced compared to when it is not provided (part Q), and the on-resistance of the transistor element is stabilized at a low value. With the above method, the growth rate of the n-type semiconductor region in the active region is prevented from increasing, and the resistance of the n-type semiconductor region is prevented from increasing due to the increased growth rate, making it possible to stably realize a semiconductor device equipped with a transistor element with a low on-resistance.

Next, modified examples will be described.
17 to 19 are diagrams for explaining modified examples of the semiconductor device according to the second embodiment. Figures 17(A) and 17(B) each show a schematic plan view of a main part of an example of the semiconductor device according to the modified example, and Figures 18(A), 18(B), and 19 each show a schematic cross-sectional view of a main part of an example of the semiconductor device according to the modified example.

The semiconductor device 1Aa shown in FIG. 17(A) differs from the semiconductor device 1A (FIG. 6, etc.) in that the n-type semiconductor region 61 provided in the inactive region AR2 is divided into a plurality of segments 61b, and the n-type semiconductor region 62 is divided into a plurality of segments 62b. The segments 61b and 62b in the inactive region AR2 are formed by adjusting the arrangement of the openings 90a of the mask 90 in the process shown in FIG. 10, and then performing the process shown in the example of the process shown in FIG. 11 to FIG. 13. After the segments 61b and 62b are formed, the source electrode 40, the drain electrode 50, and the gate electrode 30 are formed according to the process shown in FIG. 14 and FIG. 15. For example, the semiconductor device 1Aa is obtained in this manner.

In the semiconductor device 1Aa, in a regrowth process using the MOCVD method, n-type semiconductor regions (dummy regrowth regions) are formed in the segments 61b and 62b of the inactive region AR2 along with the n-type semiconductor regions 21 and 22 of the active region AR1. By forming n-type semiconductor regions in the segments 61b and 62b of the inactive region AR2, the growth rates of the n-type semiconductor regions 21 and 22 of the active region AR1 that are regrown together with them are prevented from increasing, and their resistance is prevented from increasing.

As in semiconductor device 1Aa, the inactive area AR2 may be provided with an n-type semiconductor region 61 in which a group of segments 61b divided into a plurality of parts are intermittently arranged, or may be provided with an n-type semiconductor region 62 in which a group of segments 62b divided into a plurality of parts are intermittently arranged.

The semiconductor device 1Ab shown in FIG. 17(B) differs from the semiconductor device 1A (FIG. 6, etc.) in that the inactive region AR2 is provided with a continuous n-type semiconductor region 63 that seamlessly surrounds the active region AR1. The n-type semiconductor region 63 in the inactive region AR2 is formed by adjusting the arrangement of the opening 90a of the mask 90 accordingly in the process of FIG. 10, and then performing the process according to the example of the process of FIG. 11 to FIG. 13. After the n-type semiconductor region 63 is formed, the source electrode 40, the drain electrode 50, and the gate electrode 30 are formed according to the example of the process of FIG. 14 and FIG. 15. For example, the semiconductor device 1Ab is obtained in this manner.

In the semiconductor device 1Ab, a continuous n-type semiconductor region 63 (dummy regrowth region) is formed in the inactive region AR2 together with the n-type semiconductor region 21 and n-type semiconductor region 22 in the active region AR1 in a regrowth process using the MOCVD method. By forming the n-type semiconductor region 63 in the inactive region AR2, the growth rates of the n-type semiconductor region 21 and n-type semiconductor region 22 in the active region AR1 that are regrown together with the n-type semiconductor region 63 are prevented from increasing, and the resistances thereof are prevented from increasing.

In the semiconductor device 1Ab in which a continuous n-type semiconductor region 63 surrounding the active region AR1 is provided in the inactive region AR2, for example, as shown in FIG. 17B, the layout may require the gate electrode 30 to intersect with the n-type semiconductor region 63 in a planar view. In such a case, an insulating layer may be provided at least at the intersection with the gate electrode 30 on the n-type semiconductor region 63, so that the insulating layer is interposed between the n-type semiconductor region 63 and the gate electrode 30. This prevents contact between the n-type semiconductor region 63 and the gate electrode 30. By preventing contact between the n-type semiconductor region 63 and the gate electrode 30, the effect of the n-type semiconductor region 63 on the gate electrode 30 is suppressed, and the effect of the effect on the gate electrode 30 on the operation of the transistor element is suppressed.

The same can be done for the source electrode 40 and the drain electrode 50. That is, when the layout requires that the source electrode 40 and the drain electrode 50 cross the n-type semiconductor region 63 while avoiding contact in a planar view, an insulating layer can be interposed between the source electrode 40 and the drain electrode 50 and the n-type semiconductor region 63. This suppresses the effect of the n-type semiconductor region 63 on the source electrode 40 and the drain electrode 50.

The semiconductor device 1Ac shown in FIG. 18A has a configuration in which a trench 64 is provided between the n-type semiconductor region 21 of the active region AR1 and the n-type semiconductor region 61 of the inactive region AR2. Furthermore, the semiconductor device 1Ac has a configuration in which a trench 65 is provided between the n-type semiconductor region 22 of the active region AR1 and the n-type semiconductor region 62 of the inactive region AR2. FIG. 18A shows an example in which the trenches 64 and 65 are provided to divide the inactive region AR2. The semiconductor device 1Ac differs from the semiconductor device 1A (FIG. 7, etc.) in that it has such a configuration. The trenches 64 and 65 can be formed after any of the steps of FIG. 8 to FIG. 15. For example, after the inactive region AR2 is formed in the step of FIG. 9, a predetermined portion of the inactive region AR2 is removed by dry etching using RIE or the like using a Cl-based gas, and the trenches 64 and 65 are formed. For example, in this manner, semiconductor device 1Ac is obtained.

In the semiconductor device 1Ac, in a regrowth process using the MOCVD method, the n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2 are formed together with the n-type semiconductor region 21 and n-type semiconductor region 22 in the active region AR1. By forming the n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2, the growth rates of the n-type semiconductor region 21 and n-type semiconductor region 22 in the active region AR1 that are regrown together with them are prevented from increasing, and their resistance is prevented from increasing.

In the semiconductor device 1Ac, a trench 64 is provided between the n-type semiconductor region 21 and the n-type semiconductor region 61, and a trench 65 is provided between the n-type semiconductor region 22 and the n-type semiconductor region 62. This effectively suppresses electrical interactions (such as capacitive coupling) between the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2 and the n-type semiconductor region 21 and the n-type semiconductor region 22 and the 2DEG1a in the active region AR1.

The semiconductor device 1Ad shown in FIG. 18(B) differs from the semiconductor device 1A (FIG. 7, etc.) in that a recess 66 is formed in the inactive region AR2 surrounding the active region AR1, and the n-type semiconductor region 61 and the n-type semiconductor region 62 are provided at the bottom of the recess 66. The recess 66 is formed, for example, in the process of FIG. 9, by removing the portion of the semiconductor layer 10A exposed from the opening of the resist pattern (not shown) by dry etching using RIE or the like using a Cl-based gas, instead of ion implantation of Ar. The recess 66 is formed so that its bottom is located deeper than the 2DEG 1a generated in the electron transit layer 11.

The semiconductor layer 10A in which the recess 66 is formed is subjected to the steps shown in the steps of FIGS. 10 to 15. That is, a mask 90 is formed, recesses 71 and 72 in the active region AR1 and recesses 81 and 82 in the recess 66 in the inactive region AR2 are formed, and n-type semiconductor regions 21 and 22 and n-type semiconductor regions 61 and 62 are formed. Then, the mask 90 is removed, the source electrode 40 and the drain electrode 50 are formed, and the gate electrode 30 is formed, to obtain the semiconductor device 1Ad.

In the semiconductor device 1Ad, in a regrowth process using the MOCVD method, the n-type semiconductor region 61 and n-type semiconductor region 62 in the recess 66 of the inactive region AR2 are formed together with the n-type semiconductor region 21 and n-type semiconductor region 22 in the active region AR1. By forming the n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and n-type semiconductor region 22 in the active region AR1 that are regrown together with them is prevented from increasing, and the resistance of these regions is prevented from increasing.

In the semiconductor device 1Ad, the n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the recess 66 of the inactive region AR2. Therefore, in the semiconductor device 1Ad, the n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 and the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1 are prevented from facing each other's side surfaces and from facing each other over a large area. This effectively prevents electrical interactions (such as capacitive coupling) between the n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 and the n-type semiconductor region 21 and the n-type semiconductor region 22 and the 2DEG1a of the active region AR1.

The semiconductor device 1Ae shown in FIG. 19 has a configuration in which n-type semiconductor regions 21 and 22, as well as n-type semiconductor regions 61 and 62, are provided on the surface 10a of the semiconductor layer 10A. In the semiconductor device 1Ae, the semiconductor layer 10A does not have the recesses 71 and 72, and the recesses 81 and 82 described above. The semiconductor device 1Ae differs from the semiconductor device 1A (FIG. 7, etc.) in having such a configuration.

For example, after the mask 90 is formed according to the example of the process of FIG. 10, the recesses 71 and 72 and the recesses 81 and 82 shown in the process of FIG. 11 are not formed, and the regrowth is performed using the MOCVD method according to the example of the process of FIG. 12. That is, the n-type semiconductor region 21 and the n-type semiconductor region 22, and the n-type semiconductor region 61 and the n-type semiconductor region 62 are regrown on the surface 10a of the semiconductor layer 10A using the MOCVD method. Then, for the semiconductor layer 10A thus regrown on the surface 10a, the mask 90 is removed, the source electrode 40 and the drain electrode 50 are formed, and the gate electrode 30 is formed according to the example of the process of FIG. 13 to FIG. 15, and the semiconductor device 1Ae is obtained.

In the semiconductor device 1Ae, in a regrowth process using the MOCVD method, n-type semiconductor region 21 and n-type semiconductor region 22 are formed on surface 10a of semiconductor layer 10A in active region AR1. At the same time, n-type semiconductor region 61 and n-type semiconductor region 62 are formed on surface 10a of semiconductor layer 10A in inactive region AR2. By forming n-type semiconductor region 61 and n-type semiconductor region 62 in inactive region AR2, the growth rates of n-type semiconductor region 21 and n-type semiconductor region 22 in active region AR1, which are regrown together with them, are prevented from increasing, and their resistance is prevented from increasing.

As in semiconductor device 1Ae, n-type semiconductor region 21 and n-type semiconductor region 22 and n-type semiconductor region 61 and n-type semiconductor region 62 do not necessarily need to be provided in recesses 71 and 72 and recesses 81 and 82. If source electrode 40 and drain electrode 50 connected to n-type semiconductor region 21 and n-type semiconductor region 22, respectively, provided on face 10a of semiconductor layer 10A are connected to 2DEG 1a with sufficiently low resistance, a configuration like semiconductor device 1Ae may be adopted.

[Third embodiment]
Figures 20 and 21 are diagrams for explaining an example of a semiconductor device according to the third embodiment. Figure 20 is a schematic plan view of a main part of the semiconductor device according to the third embodiment. Figure 21 is a schematic cross-sectional view of a main part of the semiconductor device according to the third embodiment. Figure 21 is a schematic cross-sectional view taken along line XXI-XXI of Figure 20.

20 and 21 is an example of a HEMT. The semiconductor device 1B has a configuration in which a source electrode 40 connected to an n-type semiconductor region 21 provided in the active region AR1 extends to the inactive region AR2 and is connected to an n-type semiconductor region 61 provided in the inactive region AR2. As an example, the source electrode 40 is provided so as to cover the n-type semiconductor region 61 and to overlap a portion of the source electrode 40 with the n-type semiconductor region 61 in a planar view. Similarly, the semiconductor device 1B has a configuration in which a drain electrode 50 connected to an n-type semiconductor region 22 provided in the active region AR1 extends to the inactive region AR2 and is connected to an n-type semiconductor region 62 provided in the inactive region AR2. As an example, the drain electrode 50 is provided so as to cover the n-type semiconductor region 62 and to overlap a portion of the drain electrode 50 with the n-type semiconductor region 62 in a planar view. Semiconductor device 1B differs from semiconductor device 1A (FIGS. 6 and 7, etc.) described in the second embodiment above in that it has this configuration.

In the formation of semiconductor device 1B, in the process of FIG. 14 described in the second embodiment above, the source electrode 40 is formed so as to be connected to both the n-type semiconductor region 21 of the active region AR1 and the n-type semiconductor region 61 of the inactive region AR2. The drain electrode 50 is formed so as to be connected to both the n-type semiconductor region 22 of the active region AR1 and the n-type semiconductor region 62 of the inactive region AR2. The other processes are performed according to the examples of the processes of FIGS. 8 to 13 and 15 described in the second embodiment above. By this method, the semiconductor device 1B shown in FIGS. 20 and 21 is obtained.

In addition, with respect to the surface 10a of the semiconductor layer 10A, the end faces 61a and 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 are located higher than the end faces 21a and 22a of the n-type semiconductor region 21 and the n-type semiconductor region 22.

20 shows, as an example, a semiconductor device 1B in which the source electrode 40 covers the entire n-type semiconductor region 61 of the inactive region AR2 in a planar view, and the drain electrode 50 covers the entire n-type semiconductor region 62 of the inactive region AR2 in a planar view. Alternatively, the source electrode 40 may be laid out to cover a portion of the n-type semiconductor region 61 of the inactive region AR2 in a planar view, and the drain electrode 50 may be laid out to cover a portion of the n-type semiconductor region 62 of the inactive region AR2 in a planar view.

In the semiconductor device 1B, as described in the second embodiment above, in a regrowth process using the MOCVD method, the n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2 are formed together with the n-type semiconductor region 21 and n-type semiconductor region 22 in the active region AR1. By forming the n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and n-type semiconductor region 22 in the active region AR1 that are regrown together with them is prevented from increasing, and the resistance of these regions is prevented from increasing.

Furthermore, in the semiconductor device 1B, the source electrode 40 covers all or part of the n-type semiconductor region 61 in the inactive region AR2 and is connected to the n-type semiconductor region 61. The drain electrode 50 covers all or part of the n-type semiconductor region 62 in the inactive region AR2 and is connected to the n-type semiconductor region 62.

Here, the n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 are provided at a position spaced apart from the active region AR1, for example, at a position spaced apart by 50 μm or more. Therefore, the n-type semiconductor region 61 of the inactive region AR2 connected to the source electrode 40 is prevented from affecting the operation of the transistor element of the active region AR1 due to electrical interaction with the n-type semiconductor region 21 and 2DEG1a of the active region AR1 in the semiconductor layer 10A. Similarly, the n-type semiconductor region 62 of the inactive region AR2 connected to the drain electrode 50 is prevented from affecting the operation of the transistor element of the active region AR1 due to electrical interaction with the n-type semiconductor region 22 and 2DEG1a of the active region AR1 in the semiconductor layer 10A. In the semiconductor device 1B, such electrical effects can be suppressed, and the source electrode 40 can be laid out to cover all or part of the n-type semiconductor region 61, and the drain electrode 50 can be laid out to cover all or part of the n-type semiconductor region 62. By adopting a configuration such as that of the semiconductor device 1B, it is possible to increase the degree of freedom in the layout of the source electrode 40 and the drain electrode 50, and the degree of freedom in the pattern design.

The n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the inactive region AR2 so as not to come into contact with the gate electrode 30. This reduces the effect of the n-type semiconductor region 61 and the n-type semiconductor region 62 on the gate electrode 30, and reduces the effect of the effect on the gate electrode 30 on the operation of the transistor element.

[Fourth embodiment]
Figures 22 and 23 are diagrams for explaining an example of a semiconductor device according to the fourth embodiment. Figure 22 is a schematic plan view of a main part of the semiconductor device according to the fourth embodiment. Figure 23 is a schematic cross-sectional view of a main part of the semiconductor device according to the fourth embodiment. Figure 23 is a schematic cross-sectional view taken along line XXIII-XXIII of Figure 22.

22 and 23 is an example of a HEMT. The semiconductor device 1C includes a pair of source electrodes 40, a drain electrode 50 provided between the source electrodes 40, and a gate electrode 30 having a gate finger portion 31 provided between the drain electrode 50 and each source electrode 40. A part of the source electrodes 40, a part of the drain electrode 50, and a part of the gate finger portion 31 (FIG. 22) are provided in the active region AR1. The source electrodes 40 are connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1, and further extend to the inactive region AR2 and are connected to the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2. As an example, the source electrodes 40 are provided so as to cover the n-type semiconductor region 61 and the n-type semiconductor region 62, respectively, and to overlap the n-type semiconductor region 61 and the n-type semiconductor region 62 in a plan view. The drain electrode 50 is connected to the n-type semiconductor region 23 provided in the active region AR1, and is further provided so as to extend into the inactive region AR2 (FIG. 22). The semiconductor device 1C differs from the semiconductor device 1A described in the second embodiment above (FIGS. 6 and 7, etc.) in that it has such a configuration.

In the formation of the semiconductor device 1C, in the steps of FIG. 10 to FIG. 13 described in the second embodiment, the n-type semiconductor region 21, the n-type semiconductor region 22, and the n-type semiconductor region 23 are formed in the active region AR1, and the n-type semiconductor region 61 and the n-type semiconductor region 62 are formed in the inactive region AR2. That is, a mask 90 having a group of openings 90a corresponding to these is formed, the recesses 71, 72, and 73 in the active region AR1, and the recesses 81 and 82 in the inactive region AR2 are formed, and a re-growth step using the MOCVD method is performed. Thereafter, the mask 90 is removed. Next, according to the example of the steps of FIG. 14 and FIG. 15 described in the second embodiment, a group of source electrodes 40 and a drain electrode 50 are formed so as to have a pattern as shown in FIG. 22 and FIG. 23, and further, a gate electrode 30 having a gate finger portion 31 is formed. By such a method, the semiconductor device 1C shown in FIG. 22 and FIG. 23 is obtained.

In addition, with respect to the surface 10a of the semiconductor layer 10A, the end faces 61a and 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 are positioned higher than the end faces 21a, 22a, and 23a of the n-type semiconductor region 21, the n-type semiconductor region 22, and the n-type semiconductor region 23.

In addition, one of the source electrodes 40 may be laid out so as to cover a portion of the n-type semiconductor region 61 of the inactive region AR2 in a plan view, and the other of the source electrodes 40 may be laid out so as to cover a portion of the n-type semiconductor region 62. This allows for greater freedom in layout and pattern design, making it possible to provide the source electrodes 40.

In the semiconductor device 1C, in a regrowth process using the MOCVD method, the n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2 are formed together with the n-type semiconductor region 21, n-type semiconductor region 22, and n-type semiconductor region 23 in the active region AR1. By forming the n-type semiconductor region 61 and n-type semiconductor region 62 in the inactive region AR2, the growth rates of the n-type semiconductor region 21, n-type semiconductor region 22, and n-type semiconductor region 23 in the active region AR1 that are regrown together with them are prevented from increasing, and their resistance is prevented from increasing.

The semiconductor device 1C is applied to source-grounded transistors, discrete devices, monolithic microwave integrated circuits (MMICs), etc., in which the source electrodes 40 are grounded (GND). The n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 are provided at a position separated from the gate electrode 30 and the drain electrode 50 used as a signal transmission line, and are separated from the gate electrode 30 and the drain electrode 50. The n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the inactive region AR2 directly below the source electrodes 40 used as GND or in a part of the inactive region AR2, or in other inactive regions AR2 in which passive elements, etc. are not provided. The n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 are provided at a position spaced apart from the active region AR1, for example, at a position spaced apart by 50 μm or more, and electrical interaction with the n-type semiconductor region 21 and the 2DEG 1a of the active region AR1 in the semiconductor layer 10A is suppressed. This suppresses the effect on the operation and signal transmission of the transistor element due to the provision of the n-type semiconductor region 61 and the n-type semiconductor region 62, which suppresses an increase in the growth rate of the n-type semiconductor region 21, the n-type semiconductor region 22, and the n-type semiconductor region 23 of the active region AR1.

The first to fourth embodiments have been described above.
The semiconductor devices 1, 1A, 1B, 1C, etc. having the configurations described in the first to fourth embodiments can be applied to various electronic devices. As an example, the application of the semiconductor device having the configurations described above to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier will be described below.

[Fifth embodiment]
Here, an example of application of a semiconductor device having the above-mentioned configuration to a semiconductor package will be described as the fifth embodiment.

Figure 24 is a diagram for explaining an example of a semiconductor package according to the fifth embodiment. Figure 24 shows a schematic plan view of a main part of an example of a semiconductor package according to the fifth embodiment.

The semiconductor package 200 shown in FIG. 24 is an example of a discrete package. The semiconductor package 200 includes the semiconductor device 1A described in the second embodiment above, a lead frame 210 on which the semiconductor device 1A is mounted, and a resin 220 that seals them.

The semiconductor device 1A is mounted on the die pad 210a of the lead frame 210 using, for example, a die attach material or the like (not shown). The semiconductor device 1A is provided with a pad 30a connected to the gate electrode 30, a pad 40a connected to the source electrode 40, and a pad 50a connected to the drain electrode 50. The pads 30a, 40a, and 50a are respectively connected to the gate lead 211, source lead 212, and drain lead 213 of the lead frame 210 using wires 230 such as Au or Al. The lead frame 210, the semiconductor device 1A mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that each part of the gate lead 211, source lead 212, and drain lead 213 is exposed.

An external connection electrode connected to the source electrode 40 may be provided on the surface of the semiconductor device 1A opposite to the surface on which the pad 30a connected to the gate electrode 30 and the pad 50a connected to the drain electrode 50 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder.

For example, the semiconductor device 1A described in the second embodiment is used to obtain a semiconductor package 200 having such a configuration.
As described above, in the semiconductor device 1A (FIGS. 6 and 7, etc.), an n-type semiconductor region (regrowth region) connected to an electrode (source electrode 40 or drain electrode 50) is provided in the active region, and further, an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. By providing an n-type semiconductor region in the inactive region, the growth rate of the n-type semiconductor region provided in the active region is prevented from increasing. As a result, the amount of dopant taken into the n-type semiconductor region provided in the active region is prevented from decreasing, and the resistance of the n-type semiconductor region is prevented from increasing due to the reduced amount of dopant taken in, and an n-type semiconductor region with sufficiently low resistance is stably formed in the active region. This stably realizes the semiconductor device 1A having an n-type semiconductor region with sufficiently low resistance connected to an electrode in the active region. A high-performance semiconductor package 200 is realized by using such a semiconductor device 1A.

Although the semiconductor device 1A is taken as an example here, it is possible to obtain a semiconductor package in a similar manner using other semiconductor devices 1, 1B, 1C, etc.
Sixth embodiment
Here, an example of application of the semiconductor device having the above-mentioned configuration to a power factor correction circuit will be described as the sixth embodiment.

Fig. 25 is a diagram for explaining an example of a power factor correction circuit according to the sixth embodiment. Fig. 25 shows an equivalent circuit diagram of an example of the power factor correction circuit according to the sixth embodiment.
The power factor correction (PFC) circuit 300 shown in FIG. 25 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

In the PFC circuit 300, the drain electrode of the switch element 310 is connected to the anode terminal of the diode 320 and one terminal of the choke coil 330. The source electrode of the switch element 310 is connected to one terminal of the capacitor 340 and one terminal of the capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to the cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out from between both terminals of the capacitor 350.

For example, the semiconductor devices 1, 1A, 1B, 1C, etc. are used for the switch element 310 of the PFC circuit 300 having such a configuration.
As described above, in the semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrowth region) connected to an electrode is provided in the active region, and further, an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. By providing an n-type semiconductor region in the inactive region, the growth rate of the n-type semiconductor region provided in the active region is prevented from increasing. As a result, the amount of dopant taken into the n-type semiconductor region provided in the active region is prevented from decreasing, and the resistance of the n-type semiconductor region is prevented from increasing due to the reduced amount of dopant taken in, and an n-type semiconductor region with sufficiently low resistance is stably formed in the active region. This allows the semiconductor devices 1, 1A, 1B, 1C, etc., having an n-type semiconductor region with sufficiently low resistance connected to an electrode in the active region to be stably realized. Such semiconductor devices 1, 1A, 1B, 1C, etc. are used to realize a high-performance PFC circuit 300.

[Seventh embodiment]
Here, an example of application of a semiconductor device having the above-mentioned configuration to a power supply device will be described as the seventh embodiment.

Fig. 26 is a diagram for explaining an example of a power supply device according to the seventh embodiment. Fig. 26 shows an equivalent circuit diagram of the example of the power supply device according to the seventh embodiment.
The power supply device 400 shown in FIG. 26 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

The primary side circuit 410 includes the PFC circuit 300 as described in the third embodiment above, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of switch elements, four in this example: a switch element 441, a switch element 442, a switch element 443, and a switch element 444.

The secondary side circuit 420 includes a plurality of switch elements, three of which are a switch element 421 , a switch element 422 and a switch element 423 , as an example.
For example, the semiconductor devices 1, 1A, 1B, 1C, etc. are used for the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 of the power supply device 400 having such a configuration, and for the switch elements 441 to 444 of the full bridge inverter circuit 440. For example, normal MIS (Metal Insulator Semiconductor) type FETs using silicon are used for the switch elements 421 to 423 of the secondary side circuit 420 of the power supply device 400.

As described above, in the semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrowth region) connected to an electrode is provided in the active region, and further, an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. By providing an n-type semiconductor region in the inactive region, the growth rate of the n-type semiconductor region provided in the active region is prevented from increasing. As a result, the amount of dopant taken into the n-type semiconductor region provided in the active region is prevented from decreasing, and the resistance is prevented from increasing due to the reduced amount of dopant taken in, and an n-type semiconductor region with sufficiently low resistance is stably formed in the active region. This allows the semiconductor devices 1, 1A, 1B, 1C, etc., having an n-type semiconductor region with sufficiently low resistance connected to an electrode in the active region to be stably realized. Such semiconductor devices 1, 1A, 1B, 1C, etc. are used to realize a high-performance power supply device 400.

[Eighth embodiment]
Here, an example of application of the semiconductor device having the above-mentioned configuration to an amplifier will be described as the eighth embodiment.

Fig. 27 is a diagram for explaining an example of an amplifier according to the eighth embodiment. Fig. 27 shows an equivalent circuit diagram of the example of the amplifier according to the eighth embodiment.
The amplifier 500 shown in FIG. 27 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

The digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the input signal SI, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal obtained by mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier and a high-output amplifier.

The power amplifier 540 of the amplifier 500 having such a configuration uses the semiconductor device 1, 1A, 1B, 1C, or the like.
As described above, in the semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrowth region) connected to an electrode is provided in the active region, and further, an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. By providing an n-type semiconductor region in the inactive region, the growth rate of the n-type semiconductor region provided in the active region is suppressed from increasing. As a result, the amount of dopant taken in the n-type semiconductor region provided in the active region is suppressed from decreasing, and the resistance is suppressed from increasing due to the decrease in the amount of dopant taken in, and an n-type semiconductor region with sufficiently low resistance is stably formed in the active region. As a result, the semiconductor devices 1, 1A, 1B, 1C, etc. having an n-type semiconductor region with sufficiently low resistance connected to an electrode in the active region are stably realized. Such semiconductor devices 1, 1A, 1B, 1C, etc. are used to realize a high-performance amplifier 500.

Various electronic devices to which the semiconductor devices 1, 1A, 1B, 1C, etc. are applied (such as the semiconductor package 200, PFC circuit 300, power supply device 400, and amplifier 500 described in the fifth to eighth embodiments) can be mounted in various electronic devices or electronic devices. For example, they can be mounted in various electronic devices or electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing equipment, transmitters, receivers, and radar devices.

The following supplementary notes are further provided with respect to the above-described embodiment.
(Supplementary Note 1) A semiconductor layer;
an active region provided in the semiconductor layer;
an inactive region in the semiconductor layer adjacent to the active region;
a first semiconductor region provided on a first surface side of the semiconductor layer in the active region;
a second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region;
a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region.

(Additional Note 2) The first semiconductor region is provided in a first recess provided on the first surface side of the semiconductor layer in the active region,
The semiconductor device described in appendix 1, wherein the second semiconductor region is provided in a second recess provided on the first surface side of the semiconductor layer in the inactive region.

(Additional Note 3) The semiconductor layer is
an electron supply layer provided on the first surface side;
an electron transit layer provided on the side of the electron supply layer opposite to the first surface side,
3. The semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region penetrate the electron supply layer and reach the electron transit layer.

(Supplementary Note 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the second semiconductor region is located away from the active region.
(Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the second semiconductor region is provided at a position that is 50 μm or more away from the active region.

(Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the second semiconductor region is provided at a position within 500 μm of the first semiconductor region.
(Appendix 7) A semiconductor device as described in any one of Appendices 1 to 6, characterized in that, with respect to the first surface of the semiconductor layer, a first end face of the first semiconductor region on the first surface side of the semiconductor layer is located lower than a second end face of the second semiconductor region on the first surface side of the semiconductor layer.

(Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the first electrode is connected to the first semiconductor region and the second semiconductor region.
(Supplementary Note 9) The semiconductor device described in any one of Supplementary Notes 1 to 8, further comprising a second electrode provided on the first surface side of the semiconductor layer, at least a portion of which is located in the active region, and which is separated from the first semiconductor region and the second semiconductor region.

(Supplementary Note 10) A step of forming an active region and an inactive region adjacent to the active region in a semiconductor layer;
forming a first semiconductor region on a first surface side of the semiconductor layer in the active region;
forming a second semiconductor region on the first surface side of the semiconductor layer in the inactive region;
forming a first electrode connected to the first semiconductor region on the first surface side of the semiconductor layer.

(Additional Note 11) In the step of forming the first semiconductor region and the step of forming the second semiconductor region,
forming a mask on the first surface side of the semiconductor layer, the mask having a first opening portion communicating with the active region and a second opening portion communicating with the inactive region;
11. The method for manufacturing a semiconductor device according to claim 10, further comprising growing the first semiconductor region and the second semiconductor region in the first opening and the second opening of the mask, respectively, by metal organic chemical vapor deposition.

(Additional Note 12) After forming the mask, the semiconductor layer in the first opening and the second opening is partially removed to form a first recess communicating with the first opening and a second recess communicating with the second opening in the semiconductor layer;
12. The method for manufacturing a semiconductor device described in Appendix 11, characterized in that when growing the first semiconductor region and the second semiconductor region in the first opening and the second opening, respectively, the first semiconductor region and the second semiconductor region are grown in the first recess communicating with the first opening, and the second recess communicating with the second opening, respectively.

(Supplementary Note 13) A semiconductor layer,
an active region provided in the semiconductor layer;
an inactive region in the semiconductor layer adjacent to the active region;
a first semiconductor region provided on a first surface side of the semiconductor layer in the active region;
a second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region;
a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region.

1, 1A, 1Aa, 1Ab, 1Ac, 1Ad, 1Ae, 1B, 1C, 100A, 100B Semiconductor device 1a 2DEG
10, 10A, 110 Semiconductor layer 10a, 11a, 12a, 13a, 14a, 15a Surface 11, 111 Electron transit layer 12, 112 Electron supply layer 13 Substrate 14 Initial layer 15 Spacer layer 21, 22, 23, 61, 62, 63, 180, 181, 182 n-type semiconductor region 21a, 22a, 23a, 61a, 62a End surface 30, 120 Gate electrode 30a, 40a, 50a Pad 31 Gate finger portion 40, 130 Source electrode 50, 140 Drain electrode 61b, 62b Segment 64, 65 Trench 66 Recess 71, 72, 73, 81, 82, 170, 171, 172 Recess 90, 190 Mask 90a, 190a Opening 150, AR2 Inactive region 160, AR1 Active region 183 Atom 191, 192 Region 200 Semiconductor package 210 Lead frame 210a Die pad 211 Gate lead 212 Source lead 213 Drain lead 220 Resin 230 Wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch element 320 Diode 330 Choke coil 340, 350 Capacitor 360 Diode bridge 370 AC power supply 400 Power supply device 410 Primary side circuit 420 Secondary side circuit 430 Transformer 440 Full bridge inverter circuit 500 Amplifier 510 Digital predistortion circuit 520, 530 Mixer 540 Power amplifier R1, R2 Resistor

Claims (8)

a semiconductor layer including an electron supply layer and an electron transport layer ;
an active region provided in the semiconductor layer;
an inactive region in the semiconductor layer adjacent to the active region;
an n-type first semiconductor region provided on a first surface side of the semiconductor layer on the electron supply layer side in the active region;
an n-type second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, spaced apart from the active region, and located at a distance of 500 μm or less from the first semiconductor region;
a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region. 2 . The semiconductor device according to claim 1 , wherein the first semiconductor region and the second semiconductor region penetrate the electron supply layer and reach the electron transit layer. The semiconductor device according to claim 1 or 2, characterized in that the second semiconductor region is provided at a distance of 50 μm or more from the active region. 4. The semiconductor device according to claim 1, wherein a first end face of the first semiconductor region on the first surface side of the semiconductor layer is located lower than a second end face of the second semiconductor region on the first surface side of the semiconductor layer, with respect to the first surface of the semiconductor layer. 5. The semiconductor device according to claim 1, wherein the first electrode is connected to the first semiconductor region and the second semiconductor region. forming an active region and an inactive region adjacent to the active region in a semiconductor layer including an electron supply layer and an electron transport layer ;
forming an n-type first semiconductor region on a first surface side of the semiconductor layer on the electron supply layer side in the active region;
forming an n-type second semiconductor region on the first surface side of the semiconductor layer in the inactive region, the second semiconductor region being spaced apart from the active region and located at a distance of 500 μm or less from the first semiconductor region;
forming a first electrode connected to the first semiconductor region on the first surface side of the semiconductor layer. In the step of forming the first semiconductor region and the step of forming the second semiconductor region,
forming a mask on the first surface side of the semiconductor layer, the mask having a first opening portion communicating with the active region and a second opening portion communicating with the inactive region;
7. The method for manufacturing a semiconductor device according to claim 6 , wherein the first semiconductor region and the second semiconductor region are grown in the first opening and the second opening of the mask, respectively, by metal organic chemical vapor deposition. a semiconductor layer including an electron supply layer and an electron transport layer ;
an active region provided in the semiconductor layer;
an inactive region in the semiconductor layer adjacent to the active region;
an n-type first semiconductor region provided on a first surface side of the semiconductor layer on the electron supply layer side in the active region;
an n-type second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, spaced apart from the active region, and located at a distance of 500 μm or less from the first semiconductor region;
a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region.

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