JP7703992B2 - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device - Google Patents

Description

This disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

In trench-gate MOSFETs (metal-oxide-semiconductor field effect transistors), there are known structures in which the bottom of the trench is exposed from the p-type shield region when viewed from the drain side, and in which the bottom of the trench is covered with a p-type shield region of the same width as the trench (see, for example, Patent Documents 1 to 3).

JP 2014-003051 A JP 2018-186270 A JP 2019-195081 A

In a structure in which the bottom of the trench is exposed from the p-type shield region when viewed from the drain side, or in a structure in which the bottom of the trench is covered with a p-type shield region of the same width as the trench width, the electric field concentration in the gate insulating film during off operation may become large.

The present disclosure aims to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce electric field concentration near the bottom surface of a gate trench.

The silicon carbide semiconductor device of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a first semiconductor region having a first conductivity type, a body region provided on the first semiconductor region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the first semiconductor region and having the first conductivity type, the first main surface is provided with a gate trench defined by a side surface penetrating the source region and the body region to the first semiconductor region and a bottom surface connected to the side surface, the silicon carbide substrate further has an electric field relaxation region provided between the bottom surface and the second main surface and having the second conductivity type, the electric field relaxation region has a second width at a second position contacting the bottom surface wider than a first width at a first position 1.5 μm away from the bottom surface toward the second main surface, and the first width is wider than the width of the bottom surface.

According to the present disclosure, it is possible to reduce electric field concentration near the bottom surface of the gate trench.

FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view (1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view (2) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view (3) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view (4) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view ( 5 ) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 7 is a cross-sectional view (6) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 8 is a cross-sectional view (7) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 9 is a cross-sectional view (8) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 10 is a cross-sectional view ( 9 ) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 11 is a cross-sectional view (10) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 12 is a cross-sectional view (11) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 13 is a cross-sectional view (12) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 14 is a cross-sectional view (13) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 15 is a cross-sectional view (14) showing the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 16 is a cross-sectional view illustrating a method for manufacturing a silicon carbide semiconductor device according to a modified example of the embodiment. FIG. 17 is a cross-sectional view showing a silicon carbide semiconductor device according to a modified example of the embodiment.

The form for implementing this is explained below.

[Description of the embodiments of the present disclosure]
First, the embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same symbols, and the same description will not be repeated. In the crystallographic description in this specification, individual orientations are represented by [], collective orientations by <>, individual planes by (), and collective planes by {}. In addition, when a crystallographic index is negative, it is usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[1] A silicon carbide semiconductor device according to one embodiment of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a first semiconductor region having a first conductivity type, a body region provided on the first semiconductor region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the first semiconductor region and having the first conductivity type, the first main surface is provided with a gate trench defined by a side surface penetrating the source region and the body region to the first semiconductor region and a bottom surface connected to the side surface, the silicon carbide substrate further has an electric field relaxation region provided between the bottom surface and the second main surface and having the second conductivity type, the electric field relaxation region has a second width at a second position contacting the bottom surface wider than a first width at a first position 1.5 μm away from the bottom surface toward the second main surface, and the first width is wider than the width of the bottom surface.

An electric field relaxation region is provided between the bottom surface of the gate trench and the second main surface, and when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench can be hidden by the electric field relaxation region. This can reduce electric field concentration near the bottom surface of the gate trench and suppress dielectric breakdown of the gate insulating film. In addition, short circuit resistance is improved.

[2] In [1], the electric field relaxation region may have a first electric field relaxation region in contact with the bottom surface and having the first width, and a second electric field relaxation region extending from the first electric field relaxation region in the width direction of the gate trench, and the effective concentration of the second conductive type impurity in the first electric field relaxation region may be lower than the effective concentration of the second conductive type impurity in the second electric field relaxation region. By providing the second electric field relaxation region extending from the first electric field relaxation region in the width direction of the gate trench, electric field concentration near the bottom surface of the gate trench can be further alleviated.

[3] In [2], the length of the first electric field relaxation region in the direction perpendicular to the first main surface minus the length of the second electric field relaxation region in the direction perpendicular to the first main surface may be 3 times or more and 15 times or less than the length of the second electric field relaxation region in the direction perpendicular to the first main surface. In this case, the electric field relaxation region directly below the gate trench becomes deeper, improving the breakdown voltage and short circuit resistance.

[4] In [2] or [3], the first semiconductor region may have a second semiconductor region located on the first electric field relaxation region and a third semiconductor region located on the second electric field relaxation region, and the effective concentration of the first conductive type impurity in the second semiconductor region may be higher than the effective concentration of the first conductive type impurity in the third semiconductor region. In this case, the semiconductor regions located on the first electric field relaxation region and the second electric field relaxation region are narrowed, and the short circuit resistance can be improved while reducing the feedback capacitance. Since the feedback capacitance is reduced, the switching speed is improved.

[5] In [4], the body region may have a first body region located on the second semiconductor region and a second body region located on the third semiconductor region, and the effective concentration of the second conductivity type impurity in the first body region may be lower than the effective concentration of the second conductivity type impurity in the second body region. In this case, the effective concentration of the second conductivity type impurity in the second body region directly above the second electric field relaxation region can be selectively increased. This makes it possible to reduce the effective concentration of the second conductivity type impurity in the first body region while suppressing short channelization, thereby reducing on-resistance.

[6] In [1] to [5], the first semiconductor region may have a drift region and a current diffusion region located between the drift region and the body region, the effective concentration of the first conductive type impurity in the current diffusion region may be higher than the effective concentration of the first conductive type impurity in the drift region, and the side of the gate trench may reach the current diffusion region. By providing the current diffusion region between the drift region and the body region, the on-resistance of the narrowing region can be reduced.

[7] A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes the steps of: preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having a first semiconductor region having a first conductivity type; forming a first mask on the first main surface; forming a second mask on the first mask; and forming an electric field relaxation region having a second conductivity type different from the first conductivity type by implanting ions into the silicon carbide substrate using the first mask and the second mask, wherein the first mask has a first opening, and the second mask has a second opening positioned to overlap the first opening when viewed from a direction perpendicular to the first main surface and having a width wider than that of the first opening.

By using the first mask and the second mask to perform ion implantation into the silicon carbide substrate, an electric field relaxation region can be formed between the bottom surface of the gate trench and the second main surface. Furthermore, when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench can be hidden by the electric field relaxation region. This can reduce electric field concentration near the bottom surface of the gate trench and suppress dielectric breakdown of the gate insulating film.

In addition, ions are injected into the silicon carbide epitaxial layer directly below the first opening without colliding with the crystal atoms of the material constituting the first mask. As a result, ions are injected deep into the silicon carbide epitaxial layer directly below the first opening. As a result, a first electric field relaxation region can be formed in the silicon carbide epitaxial layer located directly below the first opening. In addition, ions are scattered by the crystal atoms of the material constituting the first mask and injected into the silicon carbide epitaxial layer directly below the first opening. As a result, ions are not injected deep into the silicon carbide epitaxial layer directly below the first opening, but are injected shallowly. As a result, a second electric field relaxation region can be formed in the silicon carbide epitaxial layer located directly below the first opening. The second electric field relaxation region extending from the first electric field relaxation region in the width direction of the gate trench can further relax the electric field concentration near the bottom surface of the gate trench.

[8] In [7], the first opening and the second opening may extend along the [11-20] direction of the silicon carbide substrate. In this case, ions can be implanted deep into the silicon carbide epitaxial layer located directly below the first opening.

[9] In [7] or [8], the first mask may be made of polysilicon or silicon oxide, and the second mask may be made of resist. By making the first mask and the second mask from different materials, it is possible to prevent the first opening of the first mask from being etched when forming the second opening in the second mask. Therefore, two openings with different opening widths can be easily formed.

[10] In [7] to [9], the opening width of the first opening may be narrower than the opening width of the second opening, and the difference between the opening width of the first opening and the opening width of the second opening may be 0.2 μm or more and 1.0 μm or less. In this case, it is easy to obtain a desired ion implantation profile.

[11] In [7] to [10], the amount of misalignment between the center of the first opening in the width direction and the center of the second opening in the width direction may be within 0.2 μm. In this case, a second electric field relaxation region can be formed that protrudes approximately uniformly from the first electric field relaxation region in the width direction of the gate trench.

[12] A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes the steps of: preparing a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, the substrate having a first semiconductor region having a first conductivity type; forming a third mask formed of resist on the first main surface; and forming an electric field relaxation region having a second conductivity type different from the first conductivity type by implanting ions into the silicon carbide substrate using the third mask, the third mask having a third opening whose opening width changes in the thickness direction.

By using the third mask to perform ion implantation into the silicon carbide substrate, an electric field relaxation region can be formed between the bottom surface of the gate trench and the second main surface. Furthermore, when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench can be hidden by the electric field relaxation region. This can reduce electric field concentration near the bottom surface of the gate trench and suppress dielectric breakdown of the gate insulating film.

In addition, since the third mask has a third opening whose opening width changes in the thickness direction, a first electric field relaxation region and a second electric field relaxation region can be formed in the silicon carbide epitaxial layer, similar to the case where the first mask and the second mask are provided. This makes it possible to further relax the electric field concentration near the bottom surface of the gate trench.

[13] In [12], the third opening may have a barrel-shaped cross-sectional shape in the width direction. In this case, it is easy to obtain a desired ion implantation profile.

[Details of the embodiment of the present disclosure]
Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto.

(Silicon carbide semiconductor device)
A silicon carbide semiconductor device according to an embodiment will be described with reference to Fig. 1. As shown in Fig. 1, a silicon carbide semiconductor device 100 according to an embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.

The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1. The silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are composed of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type. A semiconductor element is formed on the silicon carbide substrate 10.

The first main surface 1 is a {0001} plane or a {0001} plane tilted at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a (000-1) plane tilted at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

In the embodiment, a field effect transistor is formed as an example of a semiconductor element on the silicon carbide substrate 10. The silicon carbide epitaxial layer 40 mainly has a drift region 11, a current diffusion region 14, a body region 12, a source region 13, an electric field relaxation region 16, and a contact region 18.

The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type. The n-type impurities are preferably added to the drift region 11 not by ion implantation but by doping the impurities during the epitaxial growth of the drift region 11. The drift region 11 is a part of the first semiconductor region.

The current diffusion region 14 is provided on the drift region 11. The current diffusion region 14 contains n-type impurities such as phosphorus and has an n-type. By providing the current diffusion region 14 on the drift region 11, the on-resistance of the narrowing region can be reduced. The current diffusion region 14 mainly includes, for example, a first current diffusion region 14a and a second current diffusion region 14b. The first current diffusion region 14a is provided on a first electric field relaxation region 16a described later. The second current diffusion region 14b is provided on a second electric field relaxation region 16b described later. The effective concentration of the n-type impurity in the first current diffusion region 14a may be higher than the effective concentration of the n-type impurity in the second current diffusion region 14b. In this case, the current diffusion region 14 is narrowed, and the short circuit withstand capability can be improved while reducing the feedback capacitance. Since the feedback capacitance is reduced, the switching speed is improved. The effective concentration of n-type impurities in the first current diffusion region 14a is, for example, 1.5×10 ¹⁷ cm ⁻³ or more and 3.0×10 ¹⁸ cm ⁻³ or less. The effective concentration of n-type impurities in the second current diffusion region 14b is, for example, 5.0×10 ¹⁶ cm ⁻³ or more and 1.0×10 ¹⁷ cm ⁻³ or less. The effective concentration of n-type impurities is the concentration obtained by subtracting the concentration of p-type impurities from the concentration of n-type impurities. The current diffusion region 14 is a part of the first semiconductor region. The first current diffusion region 14a is an example of a second semiconductor region. The second current diffusion region 14b is an example of a third semiconductor region.

The body region 12 is provided on the current diffusion region 14. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type. The body region 12 mainly includes, for example, a first body region 12a and a second body region 12b. The first body region 12a is provided on the first current diffusion region 14a. The second body region 12b is provided on the second current diffusion region 14b. The effective concentration of the p-type impurity in the first body region 12a may be lower than the effective concentration of the p-type impurity in the second body region 12b. In this case, the effective concentration of the p-type impurity in the second body region 12b directly above the second electric field relaxation region 16b can be selectively increased. This makes it possible to reduce the effective concentration of the p-type impurity in the first body region 12a while suppressing the short channel, thereby reducing the on-resistance. The effective concentration of p-type impurities in the first body region 12a is, for example, not less than 2.0×10 ¹⁷ cm ^{−3 and} not more than 3.0×10 ¹⁸ cm ⁻³ . The effective concentration of p-type impurities in the second body region 12b is, for example, not less than 3.0×10 ¹⁷ cm ⁻³ and not more than 5.0×10 ¹⁸ cm ⁻³ . The effective concentration of p-type impurities is the concentration obtained by subtracting the concentration of n-type impurities from the concentration of p-type impurities.

The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains an n-type impurity such as nitrogen or phosphorus and has an n-type. The source region 13 constitutes the first main surface 1. The effective concentration of the n-type impurity in the source region 13 is, for example, not less than 1.0×10 ¹⁸ cm ⁻³ and not more than 7.0×10 ¹⁹ cm ⁻³ .

The contact region 18 contains p-type impurities such as aluminum and has a p-type. The contact region 18 constitutes the first main surface 1. The contact region 18 penetrates the source region 13 and contacts the body region 12.

The first main surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 13, the body region 12, and the current diffusion region 14 to reach the electric field relaxation region 16. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 50° or more and 65° or less. This angle may be, for example, 55° or more. This angle may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The angle of the side surface 3 with respect to the plane including the bottom surface 4 may be 90°. The gate trench 5 extends, for example, in a stripe shape along a direction parallel to the first main surface 1. The gate trench 5 may extend in a honeycomb shape or may be scattered in an island shape.

The electric field relaxation region 16 contains p-type impurities such as aluminum and has a p-type. The electric field relaxation region 16 is provided between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the electric field relaxation region 16 contacts the bottom surface 4 of the gate trench 5. The central axis of the electric field relaxation region 16 may coincide with the central axis of the gate trench 5. The electric field relaxation region 16 has a first width W1 that is wider than the width of the bottom surface 4 of the gate trench 5 at a position 1.5 μm away from the bottom surface 4 of the gate trench 5 toward the second main surface 2. The electric field relaxation region 16 has a second width W2 that is wider than the first width W1 at a position where it contacts the bottom surface 4 of the gate trench 5.

The electric field relaxation region 16 mainly includes, for example, a first electric field relaxation region 16a and a second electric field relaxation region 16b. The first electric field relaxation region 16a has a first width W1. The upper end surface of the first electric field relaxation region 16a contacts the bottom surface 4 of the gate trench 5 and the lower end surface of the first current diffusion region 14a. The second electric field relaxation region 16b is a region that protrudes from the first electric field relaxation region 16a in the width direction of the gate trench 5. The upper end surface of the second electric field relaxation region 16b contacts the lower end surface of the second current diffusion region 14b. The difference D1 in depth between the first electric field relaxation region 16a and the second electric field relaxation region 16b may be 3 times or more and 15 times or more the depth D2 of the second electric field relaxation region 16b. In this case, the electric field relaxation region 16 directly below the gate trench becomes deeper, and the withstand voltage and short circuit withstand capacity are improved. The effective concentration of p-type impurities in the first electric field buffer region 16a may be lower than the effective concentration of p-type impurities in the second electric field buffer region 16b. The effective concentration of p-type impurities in the first electric field buffer region 16a is, for example, 5.0×10 ¹⁶ cm ^-3 or more and 3.0×10 ¹⁷ cm ^-3 or less. The effective concentration of p-type impurities in the second electric field buffer region 16b is, for example, 1.0×10 ¹⁷ cm ^-3 or more and 2.0×10 ¹⁸ cm ^-3 or less.

The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the electric field relaxation region 16 at the bottom surface 4. The gate insulating film 81 contacts each of the source region 13, the body region 12, and the current diffusion region 14 at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (polySi) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A portion of the gate electrode 82 may be disposed on the first main surface 1.

The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

The source electrode 60 contacts the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62.

The contact electrode 61 contacts the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18.

The source wiring 62 covers the upper and side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 contacts each of the interlayer insulating film 83 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum or copper (Cu). The source wiring 62 may be made of a material containing aluminum and copper. The source electrode 60 is electrically insulated from the gate electrode 82 by the interlayer insulating film 83. The source electrode 60 may include a barrier metal film such as a titanium nitride (TiN) film between the source wiring 62 and the interlayer insulating film 83.

The drain electrode 70 contacts the second main surface 2. The drain electrode 70 contacts the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 forms an ohmic junction with the silicon carbide single crystal substrate 50.

The p-type impurity concentration and n-type impurity concentration in each of the above impurity regions can be measured, for example, by using a scanning capacitance microscope (SCM) or secondary ion mass spectrometry (SIMS).

According to the silicon carbide semiconductor device 100 according to the embodiment described above, an electric field relaxation region 16 is provided between the bottom surface 4 of the gate trench 5 and the second main surface 2, and when viewed in a plan view from a direction perpendicular to the first main surface 1, the gate trench 5 can be hidden by the electric field relaxation region 16. This can relieve electric field concentration near the bottom surface 4 of the gate trench 5 and suppress dielectric breakdown of the gate insulating film 81. In addition, the short circuit resistance is improved. In addition, the second electric field relaxation region 16b extending from the first electric field relaxation region 16a in the width direction of the gate trench 5 can further relieve electric field concentration near the bottom surface 4 of the gate trench 5.

(Method of Manufacturing Silicon Carbide Semiconductor Device)
A method for manufacturing silicon carbide semiconductor device 100 according to the embodiment will now be described with reference to FIGS.

First, as shown in FIG. 2, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen. In this manner, a silicon carbide substrate 10 having a first main surface 1 and a second main surface 2 is obtained.

Next, as shown in FIG. 3, a first mask 91 is formed on the silicon carbide epitaxial layer 40. The first mask 91 has an opening 91a. The opening 91a is located on a region where the first electric field relaxation region 16a is to be formed. The opening 91a preferably extends, for example, along the [11-20] direction of the silicon carbide substrate 10. In this case, ions can be implanted deep into the silicon carbide epitaxial layer 40 located directly below the opening 91a. The first mask 91 may be a hard mask made of a material containing, for example, polysilicon or silicon oxide.

Next, as shown in FIG. 4, a second mask 92 is formed on the first mask 91. The second mask 92 is formed, for example, thicker than the first mask 91. The second mask 92 has an opening 92a. The opening 92a is located on the region where the first electric field relaxation region 16a and the second electric field relaxation region 16b are formed. The opening width Wb of the opening 92a is wider than the opening width Wa of the opening 91a. The difference between the opening width Wa and the opening width Wb is preferably 0.2 μm or more and 1.0 μm or less. In this case, it is easy to obtain a desired ion implantation profile. The opening 92a overlaps with the opening 91a when viewed from a direction perpendicular to the first main surface 1. The central axis Cb of the opening 92a may coincide with the central axis Ca of the opening 91a. The central axis Cb of the opening 92a may be offset from the central axis Ca of the opening 91a. In this case, the amount of misalignment between the central axis Cb of the opening 92a and the central axis Ca of the opening 91a is preferably within 0.2 μm. In this case, the second electric field relaxation region 16b can be formed so as to extend from the first electric field relaxation region 16a approximately uniformly in the width direction of the gate trench 5. The opening 92a, like the opening 91a, preferably extends along the [11-20] direction of the silicon carbide substrate 10. The second mask 92 is made of, for example, a material different from that of the first mask 91. In this case, when the opening 92a is formed in the second mask 92, the opening 91a of the first mask 91 can be prevented from being etched. Therefore, two openings 91a, 92a with different opening widths can be easily formed. The second mask 92 may be, for example, a resist mask.

5, a first mask 91 and a second mask 92 are used to perform channeling implantation into the silicon carbide epitaxial layer 40. The channeling implantation forms a first electric field buffer region 16a and an implantation region for the second electric field buffer region 16b. A part of the remaining portion of the silicon carbide epitaxial layer 40 functions as the drift region 11. In the channeling implantation, a p-type impurity such as aluminum is implanted. In the channeling implantation, the acceleration voltage is, for example, 750 keV or more and 950 keV or less, and the dose amount is, for example, 1.0×10 ¹³ /cm ² or more and 2.0×10 ¹⁴ /cm ² or less.

In the channeling implantation, ions are implanted into the silicon carbide epitaxial layer 40 directly below the opening 91a without colliding with the crystal atoms of the material constituting the first mask 91. As a result, ions are implanted to a deep position in the silicon carbide epitaxial layer 40 directly below the opening 91a. As a result, a first electric field relaxation region 16a, which is a first implantation region having a long length in a direction perpendicular to the first main surface 1, is formed in the silicon carbide epitaxial layer 40 located directly below the opening 91a. On the other hand, ions are scattered by the crystal atoms of the material constituting the first mask 91 and implanted into the silicon carbide epitaxial layer 40 on the side directly below the opening 91a. As a result, ions are not implanted into a deep position in the silicon carbide epitaxial layer 40 on the side directly below the opening 91a, but are implanted into a shallow position. As a result, a second implantation region having a short length in a direction perpendicular to the first main surface 1 is formed in the silicon carbide epitaxial layer 40 located on the side directly below the opening 91a. A part of the second implantation region constitutes the second electric field relaxation region 16b. The amount of ions implanted per unit depth into the first implantation region is approximately the same as the amount of ions implanted per unit depth into the second implantation region. Therefore, the effective concentration of p-type impurities in the first electric field relaxation region 16a is lower than the effective concentration of p-type impurities in the second electric field relaxation region 16b.

Next, as shown in FIG. 6, the first mask 91 and the second mask 92 are removed.

Next, as shown in FIG. 7, ion implantation is performed to form a current diffusion region 14 in the silicon carbide epitaxial layer 40. In the ion implantation, an n-type impurity such as phosphorus is implanted. In the ion implantation, an acceleration voltage is, for example, 400 keV or more and 900 keV or less, and a dose amount is, for example, 2.0×10 ¹³ /cm ² or more and 1.0×10 ¹⁴ /cm ² or less. In the ion implantation, a first current diffusion region 14a is formed on the first electric field relaxation region 16a, and a second current diffusion region 14b is formed on the side of the first current diffusion region 14a. The first current diffusion region 14a is formed by implanting an n-type impurity into a part of the silicon carbide epitaxial layer 40 having an n-type. The second current diffusion region 14b is formed by implanting an n-type impurity into a part of the second implantation region having a p-type. Therefore, the effective concentration of n-type impurities in the first current spreading region 14a is higher than the effective concentration of n-type impurities in the second current spreading region 14b.

Next, as shown in FIG. 8, ion implantation is performed to form the first body region 12a and the second body region 12b in the silicon carbide epitaxial layer 40. In the ion implantation, p-type impurities such as aluminum are implanted. In the ion implantation, the acceleration voltage is, for example, 150 keV or more and 600 keV or less, and the dose amount is, for example, 1.0×10 ¹³ /cm ² or more and 1.0×10 ¹⁴ /cm ² or less. In the ion implantation, the first body region 12a is formed on the first current diffusion region 14a, and the second body region 12b is formed on the second current diffusion region 14b. The first body region 12a is formed by implanting p-type impurities into a part of the silicon carbide epitaxial layer 40 having n-type. The second body region 12b is formed by implanting p-type impurities into a part of the second implantation region having p-type. Therefore, the effective concentration of the p-type impurity in the first body region 12a is lower than the effective concentration of the p-type impurity in the second body region 12b.

Next, as shown in FIG. 9 , ion implantation is performed to form the source region 13 and the contact region 18 in the silicon carbide epitaxial layer 40. In the ion implantation to form the source region 13, for example, an n-type impurity such as phosphorus is implanted. In the ion implantation to form the source region 13, the acceleration voltage is, for example, 50 keV to 250 keV, and the dose amount is, for example, 1.0×10 ¹⁴ /cm ² to 1.5×10 ¹⁵ /cm ^2. In the ion implantation to form the contact region 18, for example, a p-type impurity such as aluminum is implanted. In the ion implantation to form the contact region 18, the acceleration voltage is, for example, 50 keV to 300 keV, and the dose amount is, for example, 1.0×10 ¹⁵ /cm ² to 6.5×10 ¹⁵ /cm ² .

Next, as shown in FIG. 10, a gate trench 5 is formed in the source region 13, the first body region 12a, and the first current diffusion region 14a. The gate trench 5 can be formed as follows.

First, a mask (not shown) having an opening is formed in the region where the gate trench 5 is to be formed. Next, using the mask, a part of the source region 13, a part of the first body region 12a, and a part of the first current diffusion region 14a are removed by etching. By etching, a recess is formed in the region where the gate trench 5 is to be formed, the recess having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to the first main surface 1.

Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask formed on the first main surface 1. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), sulfur hexafluoride (SF ₆ ), or carbon tetrafluoride (CF ₄ ). For example, a mixed gas of chlorine gas and oxygen (O ₂ ) gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of 800° C. or more and 900° C. or less. The reactive gas may include a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen (N ₂ ) gas, argon (Ar) gas, or helium (He) gas can be used as the carrier gas.

By the above thermal etching, a gate trench 5 is formed in the first main surface 1. The gate trench 5 has a bottom surface 4 formed from the upper end surface of the first electric field relaxation region 16a, and a side surface 3 that penetrates the source region 13, the first body region 12a, and the first current diffusion region 14a and continues to the bottom surface 4. After the thermal etching, the mask is removed from the first main surface 1.

Next, as shown in FIG. 11, a gate insulating film 81 is formed. For example, the silicon carbide substrate 10 is thermally oxidized to form the gate insulating film 81 in contact with the source region 13, the first body region 12a, the first current diffusion region 14a, the first electric field relaxation region 16a, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. to 1400° C. As a result, the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4 is formed. Note that when the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. For this reason, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO anneal) in a nitric oxide (NO) gas atmosphere. In the NO anneal, the silicon carbide substrate 10 is held, for example, for about one hour under conditions of 1100°C or higher and 1400°C or lower. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the second body region 12b. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

Next, as shown in FIG. 12, the gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed, for example, by low pressure-chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the first body region 12a, the first current diffusion region 14a, and the first electric field relaxation region 16a.

Next, as shown in FIG. 13, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by a CVD method. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

14, the interlayer insulating film 83 and the gate insulating film 81 are etched to form a contact hole 90 in the interlayer insulating film 83 and the gate insulating film 81. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81. Next, a metal film (not shown) for the contact electrode 61 that contacts the source region 13 and the contact region 18 on the first main surface 1 is formed. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is composed of, for example, a material containing nickel. Next, a metal film (not shown) for the drain electrode 70 that contacts the silicon carbide single crystal substrate 50 on the second main surface 2 is formed. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is composed of, for example, a material containing nickel. Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are maintained at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 and at least a part of the metal film for the drain electrode 70 reacts with the silicon contained in the silicon carbide substrate 10 and is silicided. As a result, the contact electrode 61 that makes an ohmic junction with the source region 13 and the contact region 18, and the drain electrode 70 that makes an ohmic junction with the silicon carbide single crystal substrate 50 are formed. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon.

Next, as shown in FIG. 15, the source wiring 62 is formed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the interlayer insulating film 83. The source wiring 62 is formed, for example, by a sputtering method. The source wiring 62 is made of a material containing, for example, aluminum or copper. The source wiring 62 may be made of a material containing aluminum and copper. In this manner, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

In this manner, a silicon carbide semiconductor device 100 including a field effect transistor can be manufactured.

According to the manufacturing method of the silicon carbide semiconductor device 100 according to the embodiment described above, an electric field relaxation region 16 can be formed between the bottom surface 4 of the gate trench 5 and the second main surface 2. Furthermore, when viewed in a plan view from a direction perpendicular to the first main surface 1, the gate trench 5 can be hidden by the electric field relaxation region 16. This can reduce electric field concentration near the bottom surface 4 of the gate trench 5 and suppress dielectric breakdown of the gate insulating film 81.

In addition, ions are implanted into the silicon carbide epitaxial layer 40 directly below the opening 91a without colliding with the crystal atoms of the material constituting the first mask 91. As a result, ions are implanted to a deep position in the silicon carbide epitaxial layer 40 directly below the opening 91a. As a result, a first electric field relaxation region 16a can be formed in the silicon carbide epitaxial layer 40 located directly below the opening 91a. In addition, ions are scattered by the crystal atoms of the material constituting the first mask 91 and implanted into the silicon carbide epitaxial layer 40 on the side directly below the opening 91a. As a result, ions are not implanted into a deep position in the silicon carbide epitaxial layer 40 on the side directly below the opening 91a, but are implanted into a shallow position. As a result, a second electric field relaxation region 16b can be formed in the silicon carbide epitaxial layer 40 located on the side directly below the opening 91a. The second electric field relaxation region 16b is provided, which extends from the first electric field relaxation region 16a in the width direction of the gate trench 5, thereby further reducing the electric field concentration near the bottom surface 4 of the gate trench 5.

Instead of the laminated mask of the first mask 91 and the second mask 92, a single layer of a third mask 93 may be formed on the silicon carbide epitaxial layer 40 as shown in FIG. 16. The third mask 93 has an opening 93a. The opening width of the opening 93a varies in the thickness direction. The opening 93a preferably has a barrel-shaped cross-sectional shape that is narrowed so that the width Wc at the center in the thickness direction is wider than the width Wd at the top and bottom in the thickness direction. In this case, it is easy to obtain a desired ion implantation profile. The amount of narrowing D (=Wc-Wd) of the opening 93a can be controlled by adjusting at least one of the exposure conditions and the development conditions.

By using the third mask 93 to perform ion implantation into the silicon carbide epitaxial layer 40, an electric field relaxation region 16 can be formed between the bottom surface 4 of the gate trench 5 and the second main surface 2. Furthermore, when viewed in a plan view from a direction perpendicular to the first main surface 1, the gate trench 5 can be hidden by the electric field relaxation region 16. This can reduce electric field concentration near the bottom surface of the gate trench 5 and suppress dielectric breakdown of the gate insulating film 81.

In addition, since the third mask 93 has an opening 93a whose opening width changes in the thickness direction, the first electric field relaxation region 16a and the second electric field relaxation region 16b can be formed in the silicon carbide epitaxial layer 40 in the same manner as in the case of having the first mask 91 and the second mask 92. This makes it possible to further reduce the electric field concentration near the bottom surface 4 of the gate trench 5.

[Modification]
Next, a modified example of the embodiment will be described. The modified example differs from the embodiment mainly in the shape of the gate trench. Fig. 17 is a cross-sectional view showing a silicon carbide semiconductor device according to the modified example of the embodiment.

As shown in FIG. 17, in the silicon carbide semiconductor device 200 according to the modified example, the bottom surface 4 of the gate trench 5 is located below the upper end surface of the first electric field relaxation region 16a. The side surface 3 of the gate trench 5 contacts the source region 13, the first body region 12a, the first current diffusion region 14a, and the first electric field relaxation region 16a, and is continuous with the bottom surface 4. The other configurations are the same as those of the embodiment.

This modification can achieve the same effect as the embodiment.

In the above embodiment, n-type is described as the first conductivity type and p-type is described as the second conductivity type, but p-type may be the first conductivity type and n-type may be the second conductivity type.

Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and variations are possible within the scope of the claims.

REFERENCE SIGNS LIST 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region (part of first semiconductor region)
12 Body region 12a First body region 12b Second body region 13 Source region 14 Current spreading region (part of the first semiconductor region)
14a: first current spreading region (second semiconductor region)
14b: second current spreading region (third semiconductor region)
16 electric field relaxation region 16a first electric field relaxation region 16b second electric field relaxation region 18 contact region 40 silicon carbide epitaxial layer 50 silicon carbide single crystal substrate 60 source electrode 61 contact electrode 62 source wiring 70 drain electrode 81 gate insulating film 82 gate electrode 83 interlayer insulating film 90 contact hole 91 first mask 91a opening 92 second mask 92a opening 93 third mask 93a opening 100 silicon carbide semiconductor device 200 silicon carbide semiconductor device

Claims (10)

a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface;
The silicon carbide substrate is
a first semiconductor region having a first conductivity type;
a body region provided on the first semiconductor region and having a second conductivity type different from the first conductivity type;
a source region provided on the body region to be separated from the first semiconductor region and having the first conductivity type;
having
a gate trench is provided in the first main surface, the gate trench being defined by a side surface penetrating the source region and the body region and a bottom surface continuous with the side surface;
the silicon carbide substrate further includes an electric field relaxation region having the second conductivity type, the electric field relaxation region being provided between the bottom surface and the second main surface so as to be in contact with the bottom surface ,
the electric field relaxation region has a second width at a second position in contact with the bottom surface that is wider than a first width at a first position that is 1.5 μm away from the bottom surface toward the second main surface, and the first width is wider than the width of the bottom surface;
The electric field relaxation region is
a first electric field relief region in contact with the bottom surface and having the first width;
a second electric field relaxation region extending from the first electric field relaxation region in a width direction of the gate trench;
having
an effective concentration of the second conductivity type impurity in the first electric field buffer region is lower than an effective concentration of the second conductivity type impurity in the second electric field buffer region;
The first semiconductor region is
a second semiconductor region located on the first electric field reduction region;
a third semiconductor region located on the second electric field reduction region;
having
an effective concentration of the first conductivity type impurity in the second semiconductor region is higher than an effective concentration of the first conductivity type impurity in the third semiconductor region;
Silicon carbide semiconductor device. a difference between a length of the first electric field buffer region in a direction perpendicular to the first main surface and a length of the second electric field buffer region in a direction perpendicular to the first main surface is 3 times or more and 15 times or less than a length of the second electric field buffer region in a direction perpendicular to the first main surface;
The silicon carbide semiconductor device according to claim 1 . The body region is
a first body region located on the second semiconductor region;
a second body region located on the third semiconductor region;
having
an effective concentration of the second conductivity type impurity in the first body region is lower than an effective concentration of the second conductivity type impurity in the second body region;
The silicon carbide semiconductor device according to claim 1 . The first semiconductor region is
A drift region;
a current spreading region located between the drift region and the body region;
having
an effective concentration of the first conductivity type impurity in the current diffusion region is higher than an effective concentration of the first conductivity type impurity in the drift region;
The side of the gate trench leads to the current spreading region.
The silicon carbide semiconductor device according to claim 1 . preparing a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, the silicon carbide substrate having a first semiconductor region having a first conductivity type;
forming a first mask on the first major surface;
forming a second mask on the first mask;
forming an electric field relaxation region having a second conductivity type different from the first conductivity type by performing ion implantation into the silicon carbide substrate using the first mask and the second mask;
having
the first mask has a first opening;
the second mask has a second opening positioned to overlap the first opening when viewed in a direction perpendicular to the first main surface and having a width wider than that of the first opening;
The first opening and the second opening extend along a [11-20] direction of the silicon carbide substrate.
A method for manufacturing a silicon carbide semiconductor device. the first mask is formed of polysilicon or silicon oxide;
the second mask is formed of resist;
The method for manufacturing a silicon carbide semiconductor device according to claim 5 . The opening width of the first opening is narrower than the opening width of the second opening,
a difference between an opening width of the first opening and an opening width of the second opening is 0.2 μm or more and 1.0 μm or less;
The method for manufacturing a silicon carbide semiconductor device according to claim 5 or 6 . a positional deviation between a center of the first opening in a width direction and a center of the second opening in a width direction is within 0.2 μm;
The method for manufacturing a silicon carbide semiconductor device according to any one of claims 5 to 7 . preparing a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, the silicon carbide substrate having a first semiconductor region having a first conductivity type;
forming a third mask made of resist on the first main surface;
forming an electric field relaxation region having a second conductivity type different from the first conductivity type by implanting ions into the silicon carbide substrate using the third mask;
having
the third mask has a third opening whose opening width changes in a thickness direction;
A method for manufacturing a silicon carbide semiconductor device. The third opening has a barrel-shaped cross-sectional shape in the width direction.
The method for manufacturing a silicon carbide semiconductor device according to claim 9 .

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