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JP7728155B2 - Printed wiring board manufacturing method - Google Patents
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JP7728155B2 - Printed wiring board manufacturing method - Google Patents

Printed wiring board manufacturing method

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Publication number
JP7728155B2
JP7728155B2 JP2021188019A JP2021188019A JP7728155B2 JP 7728155 B2 JP7728155 B2 JP 7728155B2 JP 2021188019 A JP2021188019 A JP 2021188019A JP 2021188019 A JP2021188019 A JP 2021188019A JP 7728155 B2 JP7728155 B2 JP 7728155B2
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Japan
Prior art keywords
insulating layer
protective film
resin insulating
layer
wiring board
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JP2021188019A
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JP2023074862A (en
Inventor
徹 武仲
亮一 工藤
健作 中島
進 籠橋
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Ibiden Co Ltd
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Ibiden Co Ltd
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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本明細書によって開示される技術は、プリント配線板の製造方法に関する。 The technology disclosed in this specification relates to a method for manufacturing printed wiring boards.

特許文献1は、支持フィルムの一方の面に半硬化状態の絶縁層が設けられた絶縁層形成部材を準備する工程と、パッドと半硬化状態の絶縁層が接触するように絶縁層形成部材を貼り付ける工程と、絶縁層形成部材を貼り付けられた後に絶縁層を硬化させる工程、とを有する配線基板の製造方法を開示している。 Patent Document 1 discloses a method for manufacturing a wiring board that includes the steps of preparing an insulating layer-forming member having a semi-cured insulating layer provided on one side of a support film, attaching the insulating layer-forming member so that the semi-cured insulating layer contacts the pad, and curing the insulating layer after the insulating layer-forming member has been attached.

特開2009-99649号公報JP 2009-99649 A

[特許文献1の課題]
特許文献1の技術では、絶縁層形成部材が貼り付けられる際、支持フィルム及び半硬化状態の絶縁層が加圧されると考えられる。加圧により、半硬化状態の絶縁層の一部が支持フィルムの外周縁から外方にはみ出ると考えられる。はみ出た絶縁層の一部はブリードと呼ばれる。ブリードの一部は支持フィルムの上方に突出すると考えられる。ブリードが上方に突出すると、配線基板の平坦性が損なわれると考えられる。その結果、配線基板の品質が低下すると考えられる。
[Problems of Patent Document 1]
In the technology of Patent Document 1, it is believed that pressure is applied to the support film and the semi-cured insulating layer when the insulating layer-forming member is attached. It is believed that the pressure causes a portion of the semi-cured insulating layer to protrude outward from the outer periphery of the support film. The protruding portion of the insulating layer is called bleed. It is believed that a portion of the bleed protrudes upward from the support film. If the bleed protrudes upward, it is believed that the flatness of the wiring board will be impaired. As a result, it is believed that the quality of the wiring board will be reduced.

本発明のプリント配線板の製造方法は、絶縁層上に導体回路を有する導体層を形成することと、第1面と前記第1面と反対側の第2面とを有する樹脂絶縁層と前記樹脂絶縁層の前記第1面上に形成される第1保護膜とを有し、前記第1面に垂直な光で前記樹脂絶縁層と前記第1保護膜が投影される場合に前記第1保護膜の外周縁の各辺が前記樹脂絶縁層の各辺と重なる形成部材を準備することと、前記導体回路と前記第2面が接触するように前記導体層上に前記形成部材を貼り付けることと、前記貼り付けることによって前記第1保護膜の外周縁の外方および上方に突出する前記樹脂絶縁層の一部を上方から押圧して前記第1面を平坦化すること、とを有する。 The method for manufacturing a printed wiring board of the present invention includes forming a conductor layer having a conductor circuit on an insulating layer; preparing a forming member having a resin insulating layer having a first surface and a second surface opposite the first surface, and a first protective film formed on the first surface of the resin insulating layer, wherein each side of the outer periphery of the first protective film overlaps each side of the resin insulating layer when the resin insulating layer and the first protective film are projected with light perpendicular to the first surface; attaching the forming member to the conductor layer so that the conductor circuit and the second surface are in contact; and pressing from above a portion of the resin insulating layer that protrudes outward and above the outer periphery of the first protective film due to the attachment, thereby flattening the first surface.

本発明の実施形態の製造方法では、導体層上に形成部材が貼り付けられる際に、樹脂絶縁層の一部が第1保護膜の外周縁から外方にはみ出て第1保護膜の上方に突出し得る。ただし、本発明の実施形態の製造方法では、形成部材の貼り付けによって第1保護膜の外周縁の外方および上方に突出する樹脂絶縁層の一部が上方から押圧されることで第1面が平坦化される。そのため、平坦化後の第1面には上方に突出する部分が存在しない。その結果、本発明の製造方法で製造されるプリント配線板の平坦性が損なわれることが抑制される。高い品質のプリント配線板が提供される。 In the manufacturing method of an embodiment of the present invention, when a forming member is attached to the conductor layer, a portion of the resin insulating layer may protrude outward from the outer edge of the first protective film and protrude above the first protective film. However, in the manufacturing method of an embodiment of the present invention, the attachment of the forming member presses the portion of the resin insulating layer that protrudes outward and above the outer edge of the first protective film from above, flattening the first surface. Therefore, after flattening, there are no upwardly protruding portions on the first surface. As a result, the flatness of the printed wiring board manufactured by the manufacturing method of the present invention is prevented from being impaired. A high-quality printed wiring board is provided.

実施形態のプリント配線板を模式的に示す断面図。FIG. 1 is a cross-sectional view schematically showing a printed wiring board according to an embodiment. 実施形態のプリント配線板の製造方法を模式的に示す断面図。1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. 実施形態のプリント配線板の製造方法を模式的に示す断面図。1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. 実施形態のプリント配線板の製造方法を模式的に示す断面図。1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. 実施形態のプリント配線板の製造方法を模式的に示す平面図。1A to 1C are plan views schematically showing a method for manufacturing a printed wiring board according to an embodiment. 実施形態のプリント配線板の製造方法を模式的に示す平面図。1A to 1C are plan views schematically showing a method for manufacturing a printed wiring board according to an embodiment. 図2Eの工程を模式的に示す平面図。FIG. 2F is a plan view schematically showing the step of FIG. 2E. 実施形態のプリント配線板の製造方法を模式的に示す断面図。1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. 実施形態のプリント配線板の製造方法を模式的に示す断面図。1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment.

[実施形態]
図1は実施形態のプリント配線板2を示す断面図である。図1に示されるように、プリント配線板2は、絶縁層4と第1導体層10と樹脂絶縁層20と第2導体層60とビア導体70とを有する。
[Embodiment]
1 is a cross-sectional view showing a printed wiring board 2 according to an embodiment. As shown in FIG. 1, the printed wiring board 2 has an insulating layer 4, a first conductor layer 10, a resin insulating layer 20, a second conductor layer 60, and via conductors 70.

絶縁層4は熱硬化性樹脂を用いて形成される。絶縁層4はシリカ等の無機粒子を含んでもよい。絶縁層4は、ガラスクロス等の補強材を含んでもよい。 The insulating layer 4 is formed using a thermosetting resin. The insulating layer 4 may contain inorganic particles such as silica. The insulating layer 4 may also contain a reinforcing material such as glass cloth.

第1導体層10は絶縁層4上に形成されている。第1導体層10はパッド12と信号配線14とを含む。図に示されていないが、第1導体層10はパッド12と信号配線14以外の導体回路も含んでいる。第1導体層10は銅によって形成される。第1導体層10は、シード層10aとシード層10a上の電解めっき膜10bで形成されている。 The first conductor layer 10 is formed on the insulating layer 4. The first conductor layer 10 includes pads 12 and signal wiring 14. Although not shown in the figure, the first conductor layer 10 also includes conductor circuits other than the pads 12 and signal wiring 14. The first conductor layer 10 is formed of copper. The first conductor layer 10 is formed of a seed layer 10a and an electrolytic plating film 10b on the seed layer 10a.

樹脂絶縁層20は絶縁層4と第1導体層10上に形成されている。樹脂絶縁層20は第1面20F(図中の上面)と第1面20Fと反対側の第2面20B(図中の下面)を有する。樹脂絶縁層20にはパッド12を露出する開口22が形成されている。樹脂絶縁層20は熱硬化性樹脂で形成されている。熱硬化性樹脂はエポキシ系樹脂とポリマー系樹脂と無機フィラーとを含む。 The resin insulating layer 20 is formed on the insulating layer 4 and the first conductor layer 10. The resin insulating layer 20 has a first surface 20F (the upper surface in the figure) and a second surface 20B (the lower surface in the figure) opposite the first surface 20F. An opening 22 is formed in the resin insulating layer 20 to expose the pad 12. The resin insulating layer 20 is made of a thermosetting resin. The thermosetting resin contains an epoxy-based resin, a polymer-based resin, and an inorganic filler.

第2導体層60は樹脂絶縁層20の第1面20F上に形成されている。第2導体層60はランド62と信号配線64とを含む。図に示されていないが、第2導体層60はランド62と信号配線64以外の導体回路も含んでいる。第2導体層60は銅によって形成される。第2導体層60は、シード層60aとシード層60a上の電解めっき膜60bで形成されている。 The second conductor layer 60 is formed on the first surface 20F of the resin insulating layer 20. The second conductor layer 60 includes lands 62 and signal wiring 64. Although not shown in the figure, the second conductor layer 60 also includes conductor circuits other than the lands 62 and signal wiring 64. The second conductor layer 60 is formed of copper. The second conductor layer 60 is formed of a seed layer 60a and an electrolytic plating film 60b on the seed layer 60a.

ビア導体70は開口22内に形成されている。ビア導体70は第1導体層10と第2導体層60を接続する。図1ではビア導体70はパッド12とランド62を接続する。ビア導体70はシード層60aとシード層60a上の電解めっき膜60bで形成されている。 The via conductor 70 is formed in the opening 22. The via conductor 70 connects the first conductor layer 10 and the second conductor layer 60. In FIG. 1, the via conductor 70 connects the pad 12 and the land 62. The via conductor 70 is formed by the seed layer 60a and the electrolytic plating film 60b on the seed layer 60a.

[実施形態のプリント配線板2の製造方法]
図2A~図2Hは実施形態のプリント配線板2の製造方法を示す。図2A~図2Hは断面図である。
[Method for manufacturing printed wiring board 2 according to the embodiment]
2A to 2H show a method for manufacturing the printed wiring board 2 of the embodiment. 2A to 2H are cross-sectional views.

図2Aは絶縁層4と絶縁層4上に形成されている第1導体層10を示す。第1導体層10はセミアディティブ法によって形成される。 Figure 2A shows an insulating layer 4 and a first conductor layer 10 formed on the insulating layer 4. The first conductor layer 10 is formed by a semi-additive method.

図2Bに示されるように、樹脂絶縁層20と樹脂絶縁層20の第1面20F上に形成される第1保護膜32とを有する形成部材30が準備される。この時点では樹脂絶縁層20は半硬化状態である。第1保護膜32は樹脂絶縁層20の第1面20Fを完全に覆っている。形成部材30が平面視される場合、第1保護膜32の外周縁の各辺と樹脂絶縁層20の外周縁の各辺は重なる。即ち樹脂絶縁層20の第1面20Fに垂直な光で樹脂絶縁層20と第1保護膜32が投影される場合に、第1保護膜32の外周縁の各辺と樹脂絶縁層20の外周縁の各辺は重なる。第1保護膜32の例は、ポリエチレンテレフタレート(PET)製のフィルムである。第1保護膜32と樹脂絶縁層20との間に離型剤が形成されている。 As shown in FIG. 2B, a forming member 30 is prepared, including a resin insulating layer 20 and a first protective film 32 formed on the first surface 20F of the resin insulating layer 20. At this point, the resin insulating layer 20 is in a semi-cured state. The first protective film 32 completely covers the first surface 20F of the resin insulating layer 20. When the forming member 30 is viewed in a planar view, each side of the outer periphery of the first protective film 32 overlaps with each side of the outer periphery of the resin insulating layer 20. In other words, when the resin insulating layer 20 and the first protective film 32 are projected using light perpendicular to the first surface 20F of the resin insulating layer 20, each side of the outer periphery of the first protective film 32 overlaps with each side of the outer periphery of the resin insulating layer 20. An example of the first protective film 32 is a film made of polyethylene terephthalate (PET). A release agent is formed between the first protective film 32 and the resin insulating layer 20.

図2Cに示されるように、第1導体層10のパッド12と信号配線14に第2面20Bが接触するように、絶縁層4と第1導体層10上に形成部材30が貼り付けられる。この際、第1保護膜32及び半硬化状態の樹脂絶縁層20に熱と圧力が加えられる。第1保護膜32と樹脂絶縁層20は、第1保護膜32上に配置された加圧板50によって絶縁層4に向かって加圧される。加圧板50は例えばSUS(ステンレス鋼)板である。実施形態では、形成部材30が貼り付けられることにより、半硬化状態の樹脂絶縁層20が変形する。樹脂絶縁層20の一部が第1保護膜32の外周縁から外方にはみ出る。はみ出た樹脂絶縁層20の一部は第1保護膜32の上方に突出する。はみ出た樹脂絶縁層20の一部(すなわち第1保護膜32の外周縁の外方および上方に突出する樹脂絶縁層20の一部)はブリード23と呼ばれる。ブリード23は、第1保護膜32の上方に突出する突出部21を有する。樹脂絶縁層20の加熱は図示しない加熱機構によって行われる。加熱によって樹脂絶縁層20の硬化が進行する。 As shown in FIG. 2C , a forming member 30 is attached to the insulating layer 4 and the first conductor layer 10 so that the second surface 20B contacts the pads 12 and signal wiring 14 of the first conductor layer 10. At this time, heat and pressure are applied to the first protective film 32 and the semi-cured resin insulating layer 20. The first protective film 32 and the resin insulating layer 20 are pressed toward the insulating layer 4 by a pressure plate 50 placed on the first protective film 32. The pressure plate 50 is, for example, a stainless steel (SUS) plate. In this embodiment, the semi-cured resin insulating layer 20 is deformed by the attachment of the forming member 30. A portion of the resin insulating layer 20 protrudes outward from the outer periphery of the first protective film 32. The protruding portion of the resin insulating layer 20 protrudes above the first protective film 32. The protruding portion of the resin insulating layer 20 (i.e., the portion of the resin insulating layer 20 protruding outward and above the outer periphery of the first protective film 32) is called a bleed 23. The bleed 23 has a protrusion 21 that protrudes above the first protective film 32. The resin insulation layer 20 is heated by a heating mechanism (not shown). Heating promotes hardening of the resin insulation layer 20.

図2Dに示されるように、ブリード23(第1保護膜32の外周縁の外方および上方に突出する樹脂絶縁層20の一部)が上方から押圧される。ブリード23の押圧は、ブリード23に押し当てられる押圧部材55によって行われる。押圧部材55は第1保護膜32の外周縁の一部にも当接するが、第1保護膜32の全面に押し当てられることはない。押圧部材55は例えばラバー製の部材である。他の例では押圧部材55はSUS製の部材であってもよい。ブリード23が上方から押圧されることで、樹脂絶縁層20の第1面20Fが平坦化される。ブリード23の突出部21(図2C)が消失する。平坦化後の第1面20Fには上方に突出する部分が存在しない。 As shown in FIG. 2D, the bleed 23 (a portion of the resin insulation layer 20 that protrudes outward and upward from the outer periphery of the first protective film 32) is pressed from above. The bleed 23 is pressed by a pressing member 55 that is pressed against the bleed 23. The pressing member 55 also abuts against a portion of the outer periphery of the first protective film 32, but is not pressed against the entire surface of the first protective film 32. The pressing member 55 is, for example, a rubber member. In another example, the pressing member 55 may be a stainless steel member. Pressing the bleed 23 from above flattens the first surface 20F of the resin insulation layer 20. The protruding portion 21 (FIG. 2C) of the bleed 23 disappears. After flattening, there is no upwardly protruding portion on the first surface 20F.

図2Eに示されるように、第1保護膜32の上からレーザ光Lが照射される。レーザ光Lは第1保護膜32と樹脂絶縁層20を同時に貫通する。第1導体層10のパッド12に至るビア導体用の開口22が形成される。レーザ光Lは例えばUVレーザ光、CO2レーザ光である。開口22によりパッド12が露出される。 As shown in Figure 2E, laser light L is irradiated from above the first protective film 32. The laser light L simultaneously penetrates the first protective film 32 and the resin insulating layer 20. An opening 22 for a via conductor is formed, leading to the pad 12 on the first conductor layer 10. The laser light L is, for example, UV laser light or CO2 laser light. The pad 12 is exposed through the opening 22.

図2Fに示されるように、樹脂絶縁層20の第1面20Fから第1保護膜32が取り除かれる。 As shown in Figure 2F, the first protective film 32 is removed from the first surface 20F of the resin insulation layer 20.

図2Gに示されるように、樹脂絶縁層20の第1面20F上にシード層60aが形成される。シード層60aは無電解めっきによって形成される。シード層60a上にめっきレジスト100が形成される。めっきレジスト100は、ランド62と信号配線64(図1)を形成するための開口を有する。 As shown in FIG. 2G, a seed layer 60a is formed on the first surface 20F of the resin insulating layer 20. The seed layer 60a is formed by electroless plating. A plating resist 100 is formed on the seed layer 60a. The plating resist 100 has openings for forming the lands 62 and signal wiring 64 (FIG. 1).

図2Hに示されるように、めっきレジスト100から露出するシード層60a上に電解めっき膜60bが形成される。電解めっき膜60bは開口22を充填する。第1面20F上のシード層60aと電解めっき膜60bによって、ランド62と信号配線64が形成される。第2導体層60が形成される。開口22内のシード層60aと電解めっき膜60bによってビア導体70が形成される。ビア導体70は、パッド12とランド62を接続する。 As shown in FIG. 2H, an electrolytic plated film 60b is formed on the seed layer 60a exposed from the plating resist 100. The electrolytic plated film 60b fills the opening 22. The seed layer 60a and electrolytic plated film 60b on the first surface 20F form a land 62 and a signal wiring 64. The second conductor layer 60 is formed. The seed layer 60a and electrolytic plated film 60b in the opening 22 form a via conductor 70. The via conductor 70 connects the pad 12 and the land 62.

その後、めっきレジスト100が除去される。電解めっき膜60bから露出するシード層60aが除去される。第2導体層60とビア導体70は同時に形成される。加熱処理が施され、樹脂絶縁層20が完全に硬化される。実施形態のプリント配線板2(図1)が得られる。 Then, the plating resist 100 is removed. The seed layer 60a exposed from the electrolytic plating film 60b is removed. The second conductor layer 60 and via conductors 70 are formed simultaneously. A heat treatment is performed, and the resin insulating layer 20 is completely cured. The printed wiring board 2 (Figure 1) of the embodiment is obtained.

実施形態の製造方法によると、第1導体層10上に形成部材30が貼り付けられる際に、樹脂絶縁層20の一部が第1保護膜32の外周縁から外方にはみ出るとともに第1保護膜32の上方に突出する(図2C)。即ちブリード23が形成される。ただし、実施形態の製造方法では、形成部材30の貼り付け後に、押圧部材55によってブリード23が上方から押圧される(図2D)。ブリード23が上方から押圧されることで、樹脂絶縁層20の第1面20Fが平坦化される。ブリード23の突出部21が消失する。平坦化後の第1面20Fには上方に突出する部分が存在しない。その結果、実施形態の製造方法で製造されるプリント配線板2の平坦性が損なわれることが抑制される。高い品質のプリント配線板2が提供される。 According to the manufacturing method of the embodiment, when the forming member 30 is attached to the first conductor layer 10, a portion of the resin insulating layer 20 protrudes outward from the outer periphery of the first protective film 32 and protrudes above the first protective film 32 ( FIG. 2C ). In other words, a bleed 23 is formed. However, in the manufacturing method of the embodiment, after the forming member 30 is attached, the bleed 23 is pressed from above by a pressing member 55 ( FIG. 2D ). Pressing the bleed 23 from above flattens the first surface 20F of the resin insulating layer 20. The protruding portion 21 of the bleed 23 disappears. After flattening, there is no upwardly protruding portion on the first surface 20F. As a result, the flatness of the printed wiring board 2 manufactured by the manufacturing method of the embodiment is prevented from being impaired. A high-quality printed wiring board 2 is provided.

2 :プリント配線板
4 :絶縁層
10 :第1導体層
12 :パッド
14 :信号配線
20 :樹脂絶縁層
20F :第1面
20B :第2面
21 :突出部
23 :ブリード
30 :形成部材
32 :第1保護膜
50 :加圧板
55 :押圧部材
2: Printed wiring board 4: Insulating layer 10: First conductor layer 12: Pad 14: Signal wiring 20: Resin insulating layer 20F: First surface 20B: Second surface 21: Protrusion 23: Bleed 30: Forming member 32: First protective film 50: Pressing plate 55: Pressing member

Claims (2)

絶縁層上に導体回路を有する導体層を形成することと、
第1面と前記第1面と反対側の第2面とを有する樹脂絶縁層と前記樹脂絶縁層の前記第1面上に形成される第1保護膜とを有し、前記第1面に垂直な光で前記樹脂絶縁層と前記第1保護膜が投影される場合に前記第1保護膜の外周縁の各辺が前記樹脂絶縁層の各辺と重なる形成部材を準備することと、
前記導体回路と前記第2面が接触するように前記導体層上に前記形成部材を貼り付けることと、
前記貼り付けることによって前記第1保護膜の外周縁の外方および上方に突出する前記樹脂絶縁層の一部を上方から押圧して前記第1面を平坦化すること、とを有するプリント配線板の製造方法。
forming a conductor layer having a conductor circuit on an insulating layer;
preparing a forming member having a resin insulating layer having a first surface and a second surface opposite to the first surface, and a first protective film formed on the first surface of the resin insulating layer, wherein when the resin insulating layer and the first protective film are projected by light perpendicular to the first surface, each side of the outer periphery of the first protective film overlaps each side of the resin insulating layer;
attaching the forming member onto the conductor layer so that the conductor circuit and the second surface are in contact;
and pressing from above a portion of the resin insulating layer that protrudes outward and upward from the outer peripheral edge of the first protective film due to the attachment, thereby flattening the first surface.
請求項1のプリント配線板の製造方法であって、前記貼り付けることは、前記第1保護膜と前記樹脂絶縁層に熱と圧力を加えることを含む。 In the method for manufacturing a printed wiring board of claim 1, the attaching step includes applying heat and pressure to the first protective film and the resin insulating layer.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243210A (en) 2007-04-19 2007-09-20 Matsushita Electric Ind Co Ltd Heat dissipation substrate and manufacturing method thereof
JP2008251918A (en) 2007-03-30 2008-10-16 Fujifilm Corp Permanent pattern forming method and printed circuit board
JP2015195240A (en) 2014-03-31 2015-11-05 信越化学工業株式会社 Semiconductor device, stacked semiconductor device, post-sealing stacked semiconductor device, and manufacturing method thereof
JP2016193591A (en) 2015-03-31 2016-11-17 太陽インキ製造株式会社 Laminated film
WO2018008657A1 (en) 2016-07-08 2018-01-11 住友ベークライト株式会社 Sealing film, sealing method for electronic component mounted substrate, and electronic component mounted substrate coated with sealing film

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251918A (en) 2007-03-30 2008-10-16 Fujifilm Corp Permanent pattern forming method and printed circuit board
JP2007243210A (en) 2007-04-19 2007-09-20 Matsushita Electric Ind Co Ltd Heat dissipation substrate and manufacturing method thereof
JP2015195240A (en) 2014-03-31 2015-11-05 信越化学工業株式会社 Semiconductor device, stacked semiconductor device, post-sealing stacked semiconductor device, and manufacturing method thereof
JP2016193591A (en) 2015-03-31 2016-11-17 太陽インキ製造株式会社 Laminated film
WO2018008657A1 (en) 2016-07-08 2018-01-11 住友ベークライト株式会社 Sealing film, sealing method for electronic component mounted substrate, and electronic component mounted substrate coated with sealing film

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