JP7740867B2 - Chip Resistors - Google Patents

Description

The present invention relates to a surface-mount type chip resistor.

Typically, chip resistors are primarily composed of a rectangular insulating substrate, a pair of front electrodes arranged facing each other at a specified distance on the surface of the insulating substrate, a pair of rear electrodes arranged facing each other at a specified distance on the rear surface of the insulating substrate, a pair of end electrodes connecting the front and rear electrodes, a pair of external plating layers covering each of these electrodes, a resistive element bridging the pair of front electrodes, and an insulating protective film covering the resistive element.

In this type of chip resistor, the surface electrode is typically made of a low-resistivity Ag (silver)-based metal material, and an outer plating layer is formed to cover this surface electrode. However, highly corrosive sulfide gases and other gases can easily penetrate through the gap at the boundary between the outer plating layer and the protective film. This can corrode the surface electrode at the boundary between the surface electrode and the protective film, potentially causing problems such as changes in resistance or breakage.

As a result, chip resistors have been proposed in the past in which, as shown in Figure 12(a), a pair of end electrodes 100 are formed to extend beyond the boundary between the front electrode 104 and the protective film 101 and cover the edge of the protective film 101, and the outer plating layer 102 is tightly attached to the edge of the protective film 101, thereby eliminating the gap at the boundary between the outer plating layer 102 and the protective film 101 and preventing the front electrode portion at the boundary between the front electrode 104 and the protective film 101 from being exposed to sulfide gas (see, for example, Patent Document 1). In Figure 12, reference numeral 103 denotes an insulating substrate, reference numeral 105 denotes a resistor, and reference numeral 106 denotes a back electrode.

JP 2009-158721 A

In conventional chip resistors, electrolytic plating is widely used to form the outer plating layer, as it offers advantages over electroless plating, such as lower cost and shorter plating time. In electrolytic plating, the current flows perpendicular to the equipotential plane on the electrode surface of the object to be plated. Therefore, when the object has a complex shape, the current distribution becomes uneven, making it difficult to form a plating film of uniform thickness.

In the chip resistor with the configuration shown in FIG. 12(a) described above, when the outer plating layer 102 is formed by electrolytic plating, current density concentrates at the tip of the outer plating layer 102, which tends to create a thick portion 102a at the tip of the outer plating layer 102 that adheres to the end of the protective film 101, as shown in FIG. 12(b). When such a thick portion 102a is formed, the outer plating layer 102 that adheres to the end of the protective film 101 tends to peel off from the thick portion 102a at the tip, resulting in a gap at the boundary between the outer plating layer 102 and the protective film 101, allowing sulfide gas and other gases to enter through this gap.

The present invention has been made in view of the above-mentioned state of the art, and its object is to provide a chip resistor that is excellent in corrosion resistance by preventing peeling of the outer plating layer.

In order to achieve the above object, the chip resistor of the present invention comprises a rectangular parallelepiped insulating substrate, a pair of front electrodes provided at both ends of the front surface of the insulating substrate, a pair of back electrodes provided at both ends of the back surface of the insulating substrate, a resistor provided so as to straddle the pair of front electrodes, a protective film made of an insulating resin material that covers the entire resistor including the connection portion between the front electrodes and the resistor, a pair of end surface electrodes that extend at least to both end surfaces of the insulating substrate and conduct the front electrodes and the back electrode, and a pair of outer electrolytic plating layers that are provided so as to cover the end surface electrodes and extend beyond the boundary position between the front electrodes and the protective film to the end of the protective film. and a plating layer, wherein an auxiliary conductive film is provided on the front electrode in an area away from the end face of the insulating substrate, beyond the boundary with the protective film and overlapping the end of the protective film, the auxiliary conductive film extending beyond the connection portion between the front electrode and the resistor to a position above the resistor and set to be higher than the upper surface of the protective film, the external plating layer is in contact with the auxiliary conductive film and extends to the boundary between the auxiliary conductive film and the protective film, and the resistance value of the auxiliary conductive film is set higher than the resistance values of the front electrode and the end face electrodes.

In a chip resistor configured in this manner, auxiliary conductive films are provided at both ends of the protective film made of an insulating resin material, extending beyond the boundary with the front electrode to establish electrical continuity with the front electrode. The resistance of these auxiliary conductive films is set higher than the resistance of the front electrode and the end electrode, so that when the outer plating layer is formed by electrolytic plating, the current density at the tip of the outer plating layer can be reduced. This prevents the tip of the outer plating layer from becoming a thick film portion, thereby preventing peeling of the outer plating layer and achieving a chip resistor with excellent corrosion resistance.

In the chip resistor having the above configuration, the auxiliary conductive film may have a single-layer structure, but it may also have a two-layer structure consisting of a first auxiliary conductive film formed on the end of the protective film and a second auxiliary conductive film covering the side end of the first auxiliary conductive film. In this case, the top surfaces of the first auxiliary conductive film and the second auxiliary conductive film are flush with each other, and the resistance value of the first auxiliary conductive film is set higher than the resistance value of the second auxiliary conductive film.

Furthermore, in a chip resistor with the above configuration, if the end electrode extends beyond the surface of the front electrode to a position that covers part of the auxiliary conductive film, a stable plating layer can be formed on the auxiliary conductive film.

Furthermore, in a chip resistor having the above configuration, an undercoat layer made of a glass material is provided on the resistor, and an overcoat layer provided on this undercoat layer serves as a protective film, and an auxiliary conductive film is formed to cover both ends of the undercoat layer.Since an undercoat layer made of a glass material exists between the auxiliary conductive film and the surface electrode, even if sulfurization occurs in the auxiliary conductive film, the undercoat layer can prevent the sulfurization from progressing to the surface electrode.

The present invention makes it possible to provide a chip resistor that prevents peeling of the outer plating layer and has excellent corrosion resistance.

1 is a cross-sectional view of a chip resistor according to a first embodiment of the present invention; 3A to 3C are plan views showing the manufacturing process of the chip resistor. 3A to 3C are cross-sectional views showing a manufacturing process of the chip resistor. FIG. 4 is a cross-sectional view of a chip resistor according to a second embodiment of the present invention. 3A to 3C are plan views showing the manufacturing process of the chip resistor. 3A to 3C are cross-sectional views showing a manufacturing process of the chip resistor. FIG. 10 is a cross-sectional view of a chip resistor according to a third embodiment of the present invention. 3A to 3C are plan views showing the manufacturing process of the chip resistor. 3A to 3C are cross-sectional views showing a manufacturing process of the chip resistor. FIG. 10 is a cross-sectional view of a chip resistor according to a fourth embodiment of the present invention. FIG. 10 is a cross-sectional view of a chip resistor according to a fifth embodiment of the present invention. FIG. 10 is a cross-sectional view of a chip resistor according to a conventional example.

The following describes embodiments of the invention with reference to the drawings. Figure 1 is a cross-sectional view of a chip resistor 1 according to a first embodiment, Figure 2 is a plan view showing the manufacturing process of the chip resistor 1, and Figure 3 is a cross-sectional view showing the manufacturing process of the chip resistor 1.

As shown in FIG. 1, the chip resistor 1 according to the first embodiment is primarily composed of a rectangular insulating substrate 2, a pair of front electrodes 3 provided at both longitudinal ends of the upper surface of the insulating substrate 2, a pair of back electrodes 4 provided at both longitudinal ends of the lower surface of the insulating substrate 2, a rectangular resistor 5 arranged to straddle the pair of front electrodes 3, an undercoat layer 6 covering the entire resistor 5 including the connection between the front electrodes 3 and the resistor 5, an overcoat layer 7 covering the undercoat layer 6, a pair of auxiliary conductive films 8 provided at both ends of the overcoat layer 7, a pair of end electrodes 9 extending on both end surfaces of the insulating substrate 2 and connecting the corresponding front electrodes 3 and back electrodes 4, and a pair of external plating layers 10 arranged to cover the end electrodes 9.

The insulating substrate 2 is made of ceramics or the like, and is obtained by dividing a large-sized aggregate substrate (described below) along primary and secondary dividing grooves that extend lengthwise and widthwise, resulting in a large number of insulating substrates 2.

The front electrode 3 is made by screen printing an Ag (silver)-based paste containing 1-5 wt% Pd (palladium), followed by drying and firing. Similarly, the back electrode 4 is made by screen printing an Ag (silver)-based paste containing 1-5 wt% Pd, followed by drying and firing.

The resistor 5 is made by screen-printing a resistive paste such as ruthenium oxide, then drying and firing it, and both longitudinal ends of the resistor 5 overlap the front electrodes 3. Although not shown, the resistor 5 has trimming grooves formed to adjust the resistance value.

The undercoat layer 6 and overcoat layer 7 constitute the two-layer protective film 11. The undercoat layer 6 is made by screen-printing glass paste, then drying and baking it. This undercoat layer 6 is formed to cover the resistor element 5 before the trimming groove is formed. The overcoat layer 7 is made by screen-printing epoxy resin paste, then heat-curing (baking). The overcoat layer 7 is formed to cover the undercoat layer 6 after the trimming groove has been formed.

The auxiliary conductive film 8 is formed by screen-printing a resin paste filled with a carbon-based conductive filler and then heat-curing it. This auxiliary conductive film 8 covers the edge of the overcoat layer 7 and extends to a position closer to the edge than the boundary between the front electrode 3 and the overcoat layer 7.

The edge electrodes 9 are formed by sputtering nickel (Ni)/chromium (Cr) or the like, and provide electrical continuity between the front electrode 3 and rear electrode 4, which are separated by the edge of the insulating substrate 2. The edge electrodes 9 extend beyond the boundary between the front electrode 3 and auxiliary conductive film 8 to the side edges of the auxiliary conductive film 8, and the upper surface of the auxiliary conductive film 8 near the overcoat layer 7 is exposed and not covered by the edge electrodes 9.

The external plating layer 10 has a two-layer structure consisting of a barrier layer and an external connection layer. The barrier layer is a Ni plating layer formed by electrolytic plating, and the external connection layer is a Sn plating layer formed by electrolytic plating. This external plating layer 10 covers the entire surface of the end electrode 9 and the back electrode 4 exposed from the end electrode 9, as well as the auxiliary conductive film 8 exposed from the end electrode 9.

Here, while the front electrode 3 and end electrode 9 are made of a metal-based conductive material such as silver or nickel, the auxiliary conductive film 8 is made of a carbon-based conductive material that does not contain metal, so the resistance of the auxiliary conductive film 8 is higher than the resistance of the front electrode 3 and end electrode 9. In other words, when looking at the surface resistance of the auxiliary conductive film 8, the end face side covered by the end electrode 9 is low and the overcoat layer 7 side exposed from the end electrode 9 is high. Therefore, when the outer plating layer 10 is formed by electrolytic plating, the current density at the tip of the outer plating layer 10 can be reduced, preventing the tip of the outer plating layer 10 from swelling and becoming a thick film portion.

Next, a method for manufacturing the chip resistor 1 configured as described above will be described with reference to Figures 2 and 3.

First, an aggregate substrate 2A is prepared, on which primary and secondary dividing grooves extending in a grid pattern are formed. These primary and secondary dividing grooves divide the front and back surfaces of aggregate substrate 2A into numerous chip formation regions, each of which constitutes one insulating substrate 2. While Figures 2 and 3 show a single chip formation region as a representative example, in reality, many such chip formation regions are arranged in a grid pattern.

As shown in Figures 2(a) and 3(a), Ag-Pd paste is screen-printed on the back surface of the assembly substrate 2A, which is then dried and fired to form a pair of opposing back electrodes 4 at both longitudinal ends of each chip formation area, with a specified gap between them. Simultaneously, or before or after this, Ag-Pd paste is screen-printed on the front surface of the assembly substrate 2A, which is then dried and fired to form a pair of opposing front electrodes 3 at both longitudinal ends of each chip formation area, with a specified gap between them. Next, a resistive paste containing ruthenium oxide or the like is screen-printed on the surface of the assembly substrate 2A, which is then dried and fired to form a rectangular resistor 5, with both ends overlapping the front electrodes 3.

Next, as shown in Figures 2(b) and 3(b), a glass paste is screen-printed in the area covering the resistor 5 and then dried and baked to form an undercoat layer 6 that covers the entire resistor 5, including the connection end with the front electrode 3. Laser light is then irradiated onto the undercoat layer 6 to form trimming grooves (not shown) in the resistor 5 and adjust the resistance value. After that, an epoxy resin paste is screen-printed onto the undercoat layer 6 and heat-cured (baked) to form an overcoat layer 7 that covers the entire undercoat layer 6 and the end of the front electrode 3. The undercoat layer 6 and overcoat layer 7 form a two-layer protective film 11.

Next, a resin paste filled with a carbon-based conductive filler is screen-printed and heat-cured to form a pair of auxiliary conductive films 8 that cover both ends of the overcoat layer 7 by a predetermined width, as shown in Figures 2(c) and 3(c). These auxiliary conductive films 8 cover the ends of the overcoat layer 7 and are formed in an area extending from the boundary between the front electrode 3 and the overcoat layer 7 to a position closer to the end face, so that the auxiliary conductive films 8 are formed to connect to the front electrode 3.

The steps up to this point have been batch processing of the aggregate substrate 2A, but in the next step, the aggregate substrate 2A is primarily divided into strips along the primary dividing grooves, yielding strip-shaped substrates 2B whose width is the longitudinal direction of the chip formation area.

Next, Ni/Cr is sputtered toward the divided surfaces of the rectangular substrate 2B to form a pair of edge electrodes 9 that connect the front electrode 3 and the back electrode 4, as shown in Figures 2(d) and 3(d). In this case, the edge electrodes 9 are formed beyond the boundary between the front electrode 3 and the auxiliary conductive film 8 to the side edges of the auxiliary conductive film 8, but the upper surface of the auxiliary conductive film 8 near the overcoat layer 7 is not covered by the edge electrodes 9.

Next, the rectangular substrate 2B is divided into multiple chip substrates 2C along the secondary dividing grooves, and then these chip substrates 2C are sequentially subjected to electrolytic nickel plating and electrolytic tin plating to form an external plating layer 10 that covers the end electrode 9 and back electrode 4, as shown in Figures 2(e) and 3(e), completing the chip resistor 1. This external plating layer 10 has a two-layer structure of Ni plating and Sn plating, and is formed to cover the entire surface of the end electrode 9 and the back electrode exposed from the end electrode 9, as well as to cover the auxiliary conductive film 8 exposed from the end electrode 9.

In this way, in the chip resistor 1 according to the first embodiment, auxiliary conductive films 8 are provided at both ends of the overcoat layer (protective film) 7, extending beyond the boundary with the front electrode 3. The resistance value of these auxiliary conductive films 8 is set higher than the resistance values of the front electrode 3 and the end electrode 9. This allows the auxiliary conductive film 8 to reduce the current density at the tip of the outer plating layer 10 when electrolytic plating is performed to form the outer plating layer 10. As a result, the tip of the outer plating layer 10 does not bulge and become a thick portion. Instead, the tip of the outer plating layer 10, which is formed to a uniform thickness, is configured to adhere closely to the end of the overcoat layer 7. This prevents peeling of the outer plating layer 10 due to the thick portion, resulting in a chip resistor 1 with high corrosion resistance (particularly sulfur resistance).

Figure 4 is a cross-sectional view of a chip resistor 20 according to a second embodiment, with parts corresponding to those in Figure 1 being assigned the same reference numerals. The second embodiment shown in Figure 4 differs from the first embodiment shown in Figure 1 in that, of the end electrode 9, the upper surface portion 9a covering the front electrode 3, the lower surface portion 9b covering the rear electrode 4, and the side surface portion 9c covering the end surface of the insulating substrate 2 are formed by sputtering from different directions. Other than that, the configuration is essentially the same, so a repeated explanation will be omitted here.

The manufacturing method of the chip resistor 20 according to the second embodiment will be described below with reference to Figures 5 and 6. Note that the manufacturing process of this chip resistor 20 is the same as that of the first embodiment up to the step of forming the auxiliary conductive film 8 shown in Figures 5(a) and 6(a), and Figures 5 and 6 show the steps thereafter.

That is, a two-layer protective film 11 consisting of an undercoat layer 6 and an overcoat layer 7 is formed to cover the resistor 5, and then a resin paste filled with a carbon-based conductive filler is screen-printed and heat-cured to form a pair of auxiliary conductive films 8 that cover both ends of the overcoat layer 7 by a predetermined width, as shown in Figures 5(a) and 6(a).

Next, a masking paste that can be washed away with water or the like is screen-printed on the surface of the overcoat layer 7 and dried to form a masking 12 that covers the exposed portion of the overcoat layer 7 sandwiched between a pair of auxiliary conductive films 8, as shown in Figures 5(b) and 6(b). At this time, the masking 12 is formed so as to extend beyond the boundary between the auxiliary conductive film 8 and the overcoat layer 7 and cover part of the auxiliary conductive film 8, but the upper surface of the auxiliary conductive film 8 near the edge is exposed and not covered by the masking 12. Similarly, a masking 13 is formed on the back side of the aggregate substrate 2A to cover the exposed portion of the aggregate substrate 2A sandwiched between a pair of back electrodes 4.

Next, Ni/Cr is sputtered vertically toward the upper surface of collective substrate 2A to form the upper surface portion 9a of edge electrode 9, which covers front electrode 3 exposed on the front surface side of collective substrate 2A, auxiliary conductive film 8, and masking 12, as shown in Figures 5(c) and 6(c). Similarly, Ni/Cr is sputtered vertically toward the lower surface of collective substrate 2A to form the lower surface portion 9b of edge electrode 9, which covers back electrode 4 exposed on the back surface side of collective substrate 2A and masking 13.

Then, the aggregate substrate 2A is divided into strips along the primary dividing grooves to obtain strip-shaped substrates 2B whose width is the longitudinal direction of the chip formation area. Next, Ni/Cr is sputtered horizontally toward the divided surfaces of the strip-shaped substrates 2B to form the side portions 9c of the end electrode 9 on the divided surfaces of the strip-shaped substrates 2B, as shown in Figures 5(d) and 6(d).

Next, the rectangular substrate 2B is divided into multiple chip-like substrates 2C along the secondary dividing grooves, and then the maskings 12 and 13 are washed and removed, as shown in Figures 5(e) and 6(e). As a result, the upper surface of the overcoat layer 7 and the upper surface of the auxiliary conductive film 8 near the overcoat layer 7, which were covered by the masking 12, are exposed and not covered by the edge electrodes 9, and the central portion of the back surface of the chip-like substrate 2C, which was covered by the masking 13, is exposed, forming a pair of edge electrodes 9 that connect the front electrode 3 and back electrode 4 corresponding to both ends of the chip-like substrate 2C.

Next, the chip substrate 2C is sequentially subjected to electrolytic nickel plating and electrolytic tin plating to form an external plating layer 10 that covers the end electrode 9 and back electrode 4, as shown in Figures 5(f) and 6(f), completing the chip resistor 20. This external plating layer 10 has a two-layer structure consisting of a Ni plating layer and a Sn plating layer, and is formed to cover the entire surface of the end electrode 9 and the back electrode exposed from the end electrode 9, as well as to cover the auxiliary conductive film 8 exposed from the end electrode 9.

In the chip resistor 20 according to the second embodiment, the upper surface 9a, lower surface 9b, and side surface 9c that make up the end electrode 9 are formed by sputtering from different directions, while the upper surface 9a that covers the front electrode 3 and auxiliary conductive film 8 is formed by sputtering perpendicular to the substrate surface, making it easy to form an upper surface 9a with a uniform thickness. Therefore, when subsequent electrolytic plating is performed, the current distribution on the upper surface 9a, which is the object to be plated, is not uneven. Furthermore, the resistivity of the end electrode 9 can be reduced, further differentiating the resistance value from the exposed portion of the auxiliary conductive film 8. This more reliably prevents a thick film from forming at the tip of the outer plating layer 10.

Figure 7 is a cross-sectional view of a chip resistor 30 according to a third embodiment of the present invention, with parts corresponding to those in Figure 1 being given the same reference numerals.

The chip resistor 30 according to the third embodiment differs from the chip resistor 1 according to the first embodiment in that the end electrode 9 does not cover the surface of the front electrode 3, and the auxiliary conductive film 8 has a two-layer structure consisting of a first auxiliary conductive film 80 formed on the end of the overcoat layer 7 and a second auxiliary conductive film 81 covering part of the first auxiliary conductive film 80; otherwise, the configuration is basically the same.

7, the chip resistor 30 according to the third embodiment is primarily composed of a rectangular insulating substrate 2, a pair of front electrodes 3 provided at both longitudinal ends of the upper surface of the insulating substrate 2, a pair of back electrodes 4 provided at both longitudinal ends of the lower surface of the insulating substrate 2, a rectangular resistor 5 arranged to straddle the pair of front electrodes 3, an undercoat layer 6 covering the entire resistor 5 including the connection between the front electrodes 3 and the resistor 5, an overcoat layer 7 covering the undercoat layer 6, a pair of first auxiliary conductive films 80 covering both ends of the overcoat layer 7, a pair of second auxiliary conductive films 81 covering the side ends of the first auxiliary conductive films 80, a pair of end electrodes 9 provided on both end surfaces of the insulating substrate 2 and connecting the corresponding front electrodes 3 and back electrodes 4, and a pair of external plating layers 10 arranged to cover the end electrodes 9.

The first auxiliary conductive film 80 is formed by screen-printing and heat-curing a resin paste filled with a carbon-based conductive filler. This first auxiliary conductive film 80 covers the edge of the overcoat layer 7 and is formed closer to the edge than the boundary between the front electrode 3 and the overcoat layer 7. The second auxiliary conductive film 81 is formed by screen-printing and heat-curing a resin paste filled with conductive metal particles such as silver. This second auxiliary conductive film 81 covers the side edge of the first auxiliary conductive film 80 and is formed in a range extending to a position closer to the edge than the boundary between the front electrode 3 and the first auxiliary conductive film 80. The first auxiliary conductive film 80 and the second auxiliary conductive film 81 form a two-layer auxiliary conductive film 8, and the top surfaces of the first auxiliary conductive film 80 and the second auxiliary conductive film 81 are flush. Therefore, the surface resistance of the auxiliary conductive film 8 is lower on the edge side where the second auxiliary conductive film 81 is exposed and higher on the overcoat layer 7 side where the first auxiliary conductive film 80 is exposed.

Next, a method for manufacturing the chip resistor 30 configured as described above will be described with reference to Figures 8 and 9. Note that the manufacturing process for this chip resistor 30 is the same as the first embodiment up to the process of forming the overcoat layer 7 shown in Figures 8(a) and 9(a), and Figures 8 and 9 show the processes thereafter.

That is, as shown in Figures 8(a) and 9(a), a two-layer protective film 11 consisting of an undercoat layer 6 and an overcoat layer 7 is formed to cover the resistor 5, and then a resin paste filled with a carbon-based conductive filler is screen-printed and heat-cured to form a pair of first auxiliary conductive films 80 that cover both ends of the overcoat layer 7 by a predetermined width, as shown in Figures 8(b) and 9(b).

Next, a resin silver paste is screen-printed and heat-cured to form a pair of second auxiliary conductive films 81 that cover the side edges of the first auxiliary conductive film 80, as shown in Figures 8(c) and 9(c). As a result, an auxiliary conductive film 8 with a two-layer structure consisting of the first auxiliary conductive film 80 and the second auxiliary conductive film 81 is formed, and the surface resistance of this auxiliary conductive film 8 is lower on the end face side where the second auxiliary conductive film 81 is exposed and higher on the overcoat layer 7 side where the first auxiliary conductive film 80 is exposed.

Then, the aggregate substrate 2A is divided into strips along the primary dividing grooves to obtain strip-shaped substrates 2B whose width is the longitudinal direction of the chip formation area. Next, Ni/Cr is sputtered toward the divided surfaces of the strip-shaped substrates 2B to form edge electrodes 9 that connect the front electrodes 3 and back electrodes 4 on the divided surfaces of the strip-shaped substrates 2B, as shown in Figures 8(d) and 9(d).

Next, the rectangular substrate 2B is divided into multiple chip substrates 2C along the secondary dividing grooves, and these chip substrates 2C are then sequentially subjected to electrolytic nickel plating and electrolytic tin plating to form an external plating layer 10 that covers the front electrode 3, end electrode 9, and back electrode 4, as shown in Figures 8(e) and 9(e), completing the chip resistor 30. This external plating layer 10 has a two-layer structure consisting of a Ni plating layer and a Sn plating layer, and is formed to cover the entire surfaces of the end electrode 9 and back electrode, as well as the front electrode 3 and auxiliary conductive film 8 (first auxiliary conductive film 80 and second auxiliary conductive film 81), extending to the tip of the overcoat layer 7.

As such, in the chip resistor 30 according to the third embodiment, the auxiliary conductive film 8 has a two-layer structure consisting of a first auxiliary conductive film 80 formed on the end of the overcoat layer 7 and a second auxiliary conductive film 81 covering part of the first auxiliary conductive film 80. Because the first auxiliary conductive film 80 is made of a carbon-based conductive material and the second auxiliary conductive film 81 is made of a metal-based conductive material such as silver, it is easy to form an auxiliary conductive film 8 with a higher resistance value on the overcoat layer 7 side than on the end surface side.

Figure 10 is a cross-sectional view of a chip resistor 40 according to the fourth embodiment, with parts corresponding to those in Figure 7 being given the same reference numerals.

As shown in FIG. 10, the chip resistor 40 according to the fourth embodiment differs from the chip resistor 30 according to the third embodiment in that, of the first auxiliary conductive film 80 and second auxiliary conductive film 81 that make up the auxiliary conductive film 8, the first auxiliary conductive film 80 is separated from the front electrode 3 without contacting it; otherwise, the configuration is basically the same. If the first auxiliary conductive film 80, which has a higher resistance value, is floating above the front electrode 3 in this way, the resistance value of the auxiliary conductive film 8 can be more effectively made higher on the overcoat layer 7 side and lower on the end face side.

Figure 11 is a cross-sectional view of a chip resistor 50 according to the fifth embodiment, with parts corresponding to those in Figure 1 being given the same reference numerals.

As shown in FIG. 11, the chip resistor 50 according to the fifth embodiment differs from the chip resistor 1 according to the first embodiment in that, of the undercoat layer 6 and overcoat layer 7 that make up the protective film 11, the overcoat layer 7 is formed in the center of the upper surface of the undercoat layer 6 excluding both end portions, and the auxiliary conductive film 8 is formed so as to cover both end portions of the undercoat layer 6; otherwise, the configuration is basically the same.

In the chip resistor 50 configured in this manner, after a pair of auxiliary conductive films 8 are formed on both ends of the undercoat layer 6, the overcoat layer 7 can be formed in the central portion of the upper surface of the undercoat layer 6 exposed between these auxiliary conductive films 8, thereby improving the linearity of the overcoat layer 7. Furthermore, because the overcoat layer 7 does not cover both ends of the undercoat layer 6, the undercoat layer 6 made of glass material can be in close contact with the front electrode 3 over a wider area. Therefore, even if sulfuric acid gas or the like penetrates between the overcoat layer 7 and the auxiliary conductive film 8, the undercoat layer 6 can reliably prevent the sulfuric acid gas or the like from penetrating the front electrode 3.

1, 20, 30, 40, 50 Chip resistor 2 Insulating substrate 2A Aggregate substrate 2B Strip-shaped substrate 2C Chip-shaped substrate 3 Front electrode 4 Back electrode 5 Resistor 6 Undercoat layer 7 Overcoat layer 8 Auxiliary conductive film 80 First auxiliary conductive film 81 Second auxiliary conductive film 9 End electrode 9a Upper surface portion 9b Lower surface portion 9c Side surface portion 10 External plating layer 11 Protective film 12, 13 Masking

Claims (4)

a pair of front electrodes provided at both ends of a front surface of the insulating substrate; a pair of back electrodes provided at both ends of a back surface of the insulating substrate; a resistor provided so as to straddle the pair of front electrodes; a protective film made of an insulating resin material that covers the entire resistor including the connection portion between the front electrodes and the resistor; a pair of end electrodes that extend at least to both end surfaces of the insulating substrate and conduct the front electrodes and the back electrodes; and a pair of external plating layers that are made of electrolytic plating and that are provided so as to cover the end electrodes and extend beyond the boundary position between the front electrodes and the protective film to the end of the protective film,
an auxiliary conductive film is provided on the front electrode in a region separated from the end face of the insulating substrate, the auxiliary conductive film extending beyond a boundary with the protective film and overlapping an end of the protective film;
the auxiliary conductive film extends beyond the connection portion between the front electrode and the resistor to a position above the resistor, and is set to be higher than an upper surface of the protective film,
A chip resistor characterized in that the external plating layer is in contact with the auxiliary conductive film and extends to the boundary between the auxiliary conductive film and the protective film, and the resistance value of the auxiliary conductive film is set higher than the resistance values of the surface electrode and the end electrode. A chip resistor as described in claim 1, characterized in that the auxiliary conductive film has a two-layer structure consisting of a first auxiliary conductive film formed on the end of the protective film and a second auxiliary conductive film covering the side end of the first auxiliary conductive film, the upper surfaces of the first auxiliary conductive film and the second auxiliary conductive film are flush with each other, and the resistance value of the first auxiliary conductive film is set higher than the resistance value of the second auxiliary conductive film . A chip resistor as described in claim 1, wherein the end surface electrode extends beyond the surface of the front electrode to a position covering a portion of the auxiliary conductive film. A chip resistor as described in claim 1, characterized in that an undercoat layer made of a glass material is provided on the resistor element, an overcoat layer provided on the undercoat layer serves as the protective film, and the auxiliary conductive film is formed to cover both ends of the undercoat layer.