JP7775800B2 - Silicon wafers and epitaxial silicon wafers - Google Patents

Description

The present invention relates to silicon wafers and epitaxial silicon wafers.

For example, epitaxial silicon wafers for power MOS transistors require extremely low resistivity before the silicon epitaxial layer is formed. For this reason, we provide epitaxial silicon wafers in which a silicon epitaxial layer is formed on the surface of a silicon wafer that has been heavily doped with phosphorus (P) to achieve a resistivity of 1.2 mΩ·cm or less.

In recent years, there has been a demand for n-type silicon wafers with extremely low resistivity of 0.9 mΩ-cm or less. However, when the resistivity of a silicon wafer is extremely low, there is a problem in that stacking faults (SFs) occur in the silicon epitaxial layer when epitaxial growth is performed, and there is a demand for a reduction in the density of SFs that occur in silicon epitaxial layers.

As described in Patent Document 1, the applicant has discovered a technology for suppressing the generation of SF in a silicon epitaxial layer by adjusting the residence time (thermal history) of a single crystal ingot at 570°C ± 70°C during single crystal growth (shortening the time spent in the temperature range where SF nuclei are formed). Furthermore, as described in Patent Document 2, the applicant has discovered that the generation of SF in a silicon epitaxial layer can be suppressed by using a technique of performing high-temperature heat treatment (argon annealing) before growing the silicon epitaxial layer.

International Publication No. 2014/175120 JP 2014-011293 A

As described in Patent Document 1, if a silicon wafer is cut from a crystalline region that has been exposed to a temperature range where SF nuclei are formed for a shorter period of time (a silicon wafer with fewer SF nuclei), the SF density in the epitaxial layer after growth can be reduced.

Furthermore, as described in Patent Document 2, by subjecting a silicon wafer cut from a crystal region that has a long residence time in a temperature range where SF nuclei are formed (a silicon wafer with many SF nuclei) to argon annealing, it is possible to reduce the SF density in the epitaxial layer after the silicon epitaxial layer is grown.
Although the techniques described in Patent Documents 1 and 2 are effective as techniques for suppressing the generation of SFs in a silicon epitaxial layer, in recent years, there has been an increasing demand for larger diameter epitaxial silicon wafers, and users are requesting further reductions in the SF density.

The present invention aims to provide a silicon wafer with a low density of dislocation loop defects that cause SF, and an epitaxial silicon wafer with low occurrence of SF in the silicon epitaxial layer.

After extensive research into the causes of SFs that occur in silicon epitaxial layers, the inventors discovered that heavily phosphorus-doped silicon wafers contain two main types of dislocation loop defects (defects in which a disordered portion of the crystal arrangement is connected in a loop shape) depending on the thermal history the crystal experiences during the single crystal ingot growth process.

The process leading to the discovery of dislocation loop defects will be described below.
First, a silicon single crystal ingot having a diameter of 200 mm and doped with a high concentration of phosphorus as a dopant was grown, and silicon wafers were produced by cutting from a crystal region having a long residence time in the temperature zone where SF nuclei are formed (hereinafter referred to as the residence time in the SF nuclei generation temperature zone) and by cutting from a crystal region having a short residence time in the SF nuclei generation temperature zone.

Specifically, silicon wafers with a long residence time in the SF nucleation temperature zone were produced, which were silicon wafers with a resistivity of 0.75 mΩ cm and cut from the top side of the straight body portion of a single crystal ingot with a residence time of 570°C ± 70°C of 350 minutes or more, and silicon wafers with a resistivity of 0.7 mΩ cm and cut from the bottom side of the straight body portion of a single crystal ingot with a residence time of 50 minutes or less at 570°C ± 70°C, respectively.
Each silicon wafer was cleaved in the thickness direction, and the cleaved cross section was observed with a transmission electron microscope (TEM). The results are shown in Figure 1.

As a result, in the silicon wafer cut from the crystalline region (top-side crystalline region) with a long residence time in the SF nucleation temperature zone, large complex dislocation loop defects 1 in which dislocation loops overlap each other as shown in Figure 1(a) were observed, and it was confirmed that there was a high density of large defects with a size exceeding 60 nm. Figure 1(b) is a photograph taken from a different angle of the complex dislocation loop defect 2 shown in Figure 1(a), and it can be seen that this complex dislocation loop defect 2 has a planar shape.
On the other hand, in the silicon wafer sliced from the crystal region (bottom crystal region) with a short residence time in the SF nucleation temperature zone, small dislocation loop defects 4 as shown in FIG. 2 were observed, and it was confirmed that the density of large complex dislocation loop defects with a size exceeding 60 nm was low.

It was then confirmed that SFs are generated in silicon epitaxial layers starting from large-sized complex dislocation loop defects. This suggests that the conditions under which SFs are generated in silicon epitaxial layers differ depending on whether or not complex dislocation loop defects are present. Therefore, the inventors considered the mechanism by which dislocation loops are generated and came to the following conclusion.

The present inventors hypothesized the following regarding the generation of dislocation loop defects.
First, during the cooling process of a silicon single crystal ingot, interstitial phosphorus present between lattices in the crystal kicks out lattice silicon present at the lattice positions (flips off the lattice silicon), generating interstitial silicon. This generated excess interstitial silicon aggregates and forms dislocation loops, and interstitial phosphorus segregates in these dislocation loops.

They then thought that suppressing the agglomeration of interstitial silicon would be effective in suppressing the occurrence of dislocation loop defects, and that intentionally adding an impurity element that can pair with interstitial silicon might be able to suppress the agglomeration of interstitial silicon, and came up with the idea of incorporating boron into the crystal during the single crystal growth stage.
The inventors have grown a silicon single crystal ingot by doping (adding) boron to a silicon melt and evaluated the defects formed in the boron-doped silicon wafer, and have found that it is possible to reduce the defect density of large dislocation loops formed in the silicon wafer, leading to the completion of the present invention.

The silicon wafer of the present invention contains phosphorus as a dopant, has a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and also contains boron.

The resistivity of a silicon wafer as defined in this invention is the value measured on the surface of the silicon wafer using the four-point probe method.

In the silicon wafer, the boron concentration is preferably 5.0×10 ¹⁴ atoms/cm ³ or more and 1.2×10 ¹⁸ atoms/cm ³ or less.

The boron concentration of a silicon wafer as defined in the present invention is a value obtained by thinning the silicon wafer by polishing, and measuring the boron concentration at the center of the thickness of the silicon wafer using secondary ion mass spectrometry (SIMS).
Since the outermost surface of a silicon wafer has a large amount of noise, making it difficult to accurately measure the boron concentration, accurate measurement of the boron concentration is possible if measurement is performed at a depth of 1 μm or more from the wafer surface, excluding the outermost surface. In the present invention, the concentration at the center of the silicon wafer thickness is specified to obtain a more accurate value.

The epitaxial silicon wafer of the present invention comprises a silicon wafer containing phosphorus as a dopant, having a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and containing boron, and a silicon epitaxial layer on the surface of the silicon wafer, wherein the silicon wafer has a low boron concentration layer on the surface side in contact with the silicon epitaxial layer, the low boron concentration layer having a lower boron concentration than the boron concentration at the center of the thickness of the silicon wafer.

In the epitaxial silicon wafer, it is desirable that the boron concentration is 5.0× ¹⁰ atoms/cm ^or more and 1.2× ¹⁰ atoms/cm or less, the boron concentration of the low boron concentration layer is 0.9 times or ^less the boron concentration at the center of the thickness of the silicon wafer, and the depth of the low boron concentration layer is 0.7 μm or more and 4.8 μm or less from the boundary between the silicon wafer and the silicon epitaxial layer in the thickness direction of the silicon wafer.

The depth of the low boron concentration layer is a value based on the boron concentration profile in the depth direction obtained by SIMS measurement, and refers to the depth position (width) in the thickness direction of the silicon wafer from the boundary between the epitaxial layer and the silicon wafer.

The resistivity of the epitaxial silicon wafer specified in this invention is the value measured by the four-point probe method on the back surface of the silicon wafer. If an oxide film is formed on the back surface of the epitaxial silicon wafer, the value is measured by the four-point probe method on the back surface of the silicon wafer after removing the back surface oxide film.

The boron concentration of the epitaxial silicon wafer specified in the present invention is a value obtained by thinning the silicon wafer by polishing and measuring the boron concentration at the center of the thickness of the silicon wafer by SIMS.
In the manufacture of epitaxial silicon wafers, the silicon wafers are subjected to high-temperature heat treatments during epitaxial growth and before the epitaxial growth process, which causes boron to diffuse outward and reduces the boron concentration in the surface layer of the silicon wafer.
Therefore, to measure the boron concentration of an epitaxial silicon wafer, it is necessary to measure it at a depth where out-diffusion of boron does not occur, and an accurate measurement of the boron concentration is possible if the measurement is made at a depth of 40 μm or more from approximately the wafer surface in the depth direction of the wafer. In the present invention, in order to obtain a more accurate value, the concentration is specified as the concentration at the center of the silicon wafer thickness.

In the epitaxial silicon wafer, it is desirable that the oxygen concentration of the silicon wafer be 4×10 ¹⁷ atoms/cm ³ or more and 10×10 ¹⁷ atoms/cm ³ or less.
The oxygen concentration of an epitaxial silicon wafer as defined in the present invention is a value obtained by thinning the silicon wafer by polishing and measuring the oxygen concentration at the center of the silicon wafer thickness by SIMS. To measure the oxygen concentration of an epitaxial silicon wafer, it is necessary to measure it at a depth where oxygen out-diffusion does not occur. Accurate measurement of the oxygen concentration is possible if the measurement is made at a depth of 150 μm or more from the wafer surface in the wafer depth direction. To obtain a more accurate value, the present invention defines the concentration at the center of the silicon wafer thickness.

In the epitaxial silicon wafer, it is desirable that no COPs exist in the silicon wafer.
In the present invention, "COP-free" refers to a silicon wafer in which no COPs are detected by the observation and evaluation described below. Specifically, a silicon wafer cut from a single crystal silicon ingot grown by the CZ method is first subjected to SC-1 cleaning (i.e., cleaning with a mixed solution of ammonia water, hydrogen peroxide solution, and ultrapure water in a ratio of 1:1:15). The surface of the silicon wafer after cleaning is observed and evaluated using a KLA-Tencor Surfscan SP-1 surface defect inspection device to identify light point defects (LPDs) estimated to be surface pits. The observation mode is oblique mode (oblique incidence mode), and the estimation of surface pits is performed based on the detection size ratio of the wide/narrow channel. The LPDs thus identified are evaluated for their presence or absence of COPs using an atomic force microscope (AFM). A silicon wafer in which no COPs are observed by this observation and evaluation is defined as a "COP-free silicon wafer."
When evaluating a silicon wafer having a diameter of 300 mm, observation and evaluation can be performed using a Surfscan SP-2.

It is desirable that the above-mentioned epitaxial silicon wafer have an oxide film on the back surface of the silicon wafer.

In the above-mentioned epitaxial silicon wafer, it is desirable that there be no oxide film on the edge or outer periphery of the back surface of the silicon wafer.

The silicon wafer of the present invention contains phosphorus as a dopant, has a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and a boron concentration of 5.0× ¹⁰ atoms/cm ^or more and 1.2× ¹⁰ atoms/ ^cm or less, wherein the silicon wafer has a low boron concentration layer on its surface, the boron concentration of the low boron concentration layer is 0.9 times or less than the boron concentration at the center of the silicon wafer in its thickness direction, and the depth of the low boron concentration layer is 0.7 μm or more and 4.8 μm or less from the surface of the silicon wafer in the thickness direction of the silicon wafer.

In the silicon wafer, the oxygen concentration is preferably 4×10 ¹⁷ atoms/cm ³ or more and 10×10 ¹⁷ atoms/cm ³ or less.

It is preferable that the above silicon wafer is free of COPs.

1 is a photograph of complex dislocation loops observed in a silicon wafer cut from a crystalline region that has a long residence time in the SF nucleation temperature zone. 1 is a photograph of dislocation loops observed in a silicon wafer cut from a crystalline region having a short residence time in the SF nucleation temperature zone. 1 is a flowchart showing an embodiment of a method for manufacturing an epitaxial silicon wafer according to the present invention. 1 is a cross-sectional view of one embodiment of an epitaxial silicon wafer according to the present invention. 1 is a graph showing the evaluation results of dislocation loops in the epitaxial silicon wafers of Example 1 and Comparative Example 1. 1 is a graph showing the results of investigation of boron concentration profiles of epitaxial silicon wafers of Examples 4 and 5. 1 shows X-ray topography photographs of the surfaces of silicon wafers of Examples 6 and 7 and Comparative Examples 4 and 5. 1 is a graph showing the relationship between LPD density and resistivity when an epitaxial layer is formed on the surface of each silicon wafer in Examples 8 and 9 and Comparative Examples 6 and 7.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The silicon wafer according to the present invention is a silicon wafer doped with phosphorus (P), a dopant for adjusting resistivity, to have a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and contains boron. The boron concentration is preferably 5.0× ¹⁰ atoms/cm ^or more and 1.2× ¹⁰ atoms/cm ^or less.
The epitaxial silicon wafer according to the present invention comprises the above silicon wafer and a silicon epitaxial layer formed on the silicon wafer.

A suitable manufacturing flow for obtaining the epitaxial silicon wafer according to the present invention is shown in Figure 3. The manufacturing flow preferably includes a single crystal ingot manufacturing process S1, a backside oxide film forming process S2, a peripheral oxide film removal process S3, an argon annealing process S4, a pre-baking process S5, and an epitaxial layer forming process S6.

In the single crystal ingot manufacturing process S1, a single crystal silicon ingot doped with phosphorus as an n-type dopant is manufactured using the CZ method (Czochralski method) using a single crystal ingot pulling device (not shown) so as to satisfy the following conditions: In this embodiment, we will explain the case of manufacturing a single crystal silicon ingot with a diameter of 200 mm (210 mm, taking into account processing losses after silicon ingot manufacturing). Note that the single crystal diameter is not limited to this example. The same applies to the manufacture of a single crystal silicon ingot with a diameter of 300 mm. Note that the manufacturing tolerance of the single crystal silicon ingot is ±0.5 mm.

(phosphorus concentration)
By doping the single crystal ingot with red phosphorus (phosphorus) so that the phosphorus concentration in the single crystal ingot is 6×10 ¹⁹ atoms/cm ³ or more and 1.64×10 ²⁰ atoms/cm ³ or less, a single crystal ingot with a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less can be obtained.

Furthermore, the lower the resistivity, the higher the density of SFs that occur in the silicon epitaxial layer. SFs are particularly likely to occur when the resistivity is 0.9 mΩ·cm or less, so the effect of adding boron is more pronounced. Therefore, it is desirable to set the phosphorus concentration to 8.3×10 ¹⁹ atoms/cm ³ or more and the resistivity to 0.9 mΩ·cm or less. The phosphorus concentration of the silicon wafer is the value obtained by measuring the phosphorus concentration at the center of the silicon wafer thickness using secondary ion mass spectrometry (SIMS). The phosphorus concentration can also be determined from the resistivity measured by the four-probe method using the calculation formula or graph specified in SEMI MF723-0307.
If the silicon raw material is doped with phosphorus before being melted, the phosphorus will evaporate during the melting of the silicon raw material, making it impossible to obtain the desired resistivity. Therefore, it is desirable to dope the silicon melt with red phosphorus after the silicon raw material has been melted.

(boron concentration)
By adding boron powder to a crucible together with silicon raw material and melting them so that the boron concentration in the single crystal ingot is 5.0× ¹⁰ atoms/cm ^or more and 1.2× ¹⁰ atoms/cm ^{or less} , a single crystal ingot having a predetermined boron concentration can be grown.
By setting the boron concentration to 5.0× ¹⁰ atoms/cm ^or more, it is possible to reduce the size and density of dislocation loop defects formed in the silicon wafer, and to significantly reduce the SF density that occurs in the epitaxial layer after the epitaxial growth process.
It should be noted that the higher the boron concentration, the more effective it is in reducing the LPD density (SF density) occurring in the epitaxial layer, so it is particularly desirable for the boron concentration to be 7×10 ¹⁷ atoms/cm ³ or higher.

Furthermore, since boron, a p-type dopant with the opposite polarity to phosphorus, an n-type dopant, is added, there is a concern that the resistivity in the single crystal may fluctuate. However, since the boron concentration added in the present invention is low and the phosphorus concentration added is overwhelmingly dominant, the resistance fluctuation due to the boron addition is extremely slight and can be almost ignored. However, if the boron concentration is increased too much, the range of resistivity fluctuation will also increase, so it is desirable to keep the boron concentration in the single crystal at 1.2 x ¹⁰ atoms/cm ^or less.

(oxygen concentration)
If the oxygen concentration in the silicon wafer is high, it tends to deteriorate the device breakdown voltage characteristics, so it is desirable to lower the oxygen concentration in the single crystal ingot, and it is desirable to set the oxygen concentration in the range of 4×10 ¹⁷ atoms/cm ³ to 10×10 ¹⁷ atoms/cm ³ .
To grow a single crystal ingot with a low oxygen concentration, it is desirable to apply a magnetic field to the silicon melt. A well-known horizontal magnetic field or cusp magnetic field can be applied, and the oxygen concentration incorporated into the single crystal can be reduced to the desired concentration by slowing down the rotation speed of the crucible containing the silicon melt or by lowering the pressure inside the pulling furnace.
If the oxygen concentration is less than 4×10 ¹⁷ atoms/cm ³ , the strength of the silicon wafer is low and there is a risk of slip dislocations occurring when the silicon wafer is subjected to high-temperature heat treatment. Therefore, it is desirable that the oxygen concentration be 4×10 ¹⁷ atoms/cm ³ or more.

After this, silicon wafers are cut from the single crystal ingot produced in the single crystal ingot production process S1 and subjected to the required processing (grinding, etching, polishing, etc.) to produce mirror-finished silicon wafers with excellent surface roughness and flatness.

In the rear surface oxide film forming step S2, it is desirable to form an oxide film (hereinafter referred to as rear surface oxide film) on the rear surface of the silicon wafer using a CVD apparatus within the following condition ranges.
Raw material gas: mixed gas of monosilane ( _SiH4 ) and oxygen ( _O2 ) Thickness of rear surface oxide film: 100 nm or more and 1500 nm or less Film formation temperature: 400°C or more and 450°C or less By providing such a rear surface oxide film, the autodoping phenomenon can be suppressed and the resistance fluctuation of the epitaxial layer can be suppressed.

In the backside oxide film formation step S2, it is difficult to form an oxide film only on the backside of the silicon wafer, and an oxide film inevitably forms on the edge (chamfered portion) of the silicon wafer after the backside oxide film formation step S2. If an epitaxial layer is formed on the oxide film surface, there is a risk of nodules (granular silicon) forming in that area. Therefore, it is desirable to remove the oxide film formed on the edge of the silicon wafer and on the outer periphery of the backside of the wafer.

Therefore, in the peripheral oxide film removal step S3, it is sufficient to remove the oxide film present at the edge (chamfered portion) of the silicon wafer and the peripheral portion of the back surface of the wafer using various techniques such as polishing and etching, and it is preferable that the width of the oxide film present at the peripheral portion of the back surface of the wafer be removed be less than 5 mm from the outer edge of the silicon wafer.
By removing the edge of the silicon wafer and the outer periphery of the backside oxide film in this manner, it is possible to prevent the generation of nodules during the growth of the silicon epitaxial layer, and also to prevent the generation of particles from the wafer edge.

In the argon annealing step S4, it is desirable to perform the heat treatment under the following conditions.
Gas atmosphere: argon gas Heat treatment temperature: 1150°C or higher and 1250°C or lower Heat treatment time: 30 minutes or higher and 120 minutes or lower As the heat treatment apparatus, it is desirable to use a batch furnace (vertical heat treatment apparatus) that can perform heat treatment on multiple silicon wafers at once.
Boron doping suppresses the generation of large dislocation loop defects in the silicon wafer, and small dislocation loop defects present in the silicon wafer can be eliminated by subjecting the silicon wafer to argon annealing, thereby making it possible to reduce the generation of SFs in the epitaxial layer as much as possible.

Furthermore, by performing argon annealing on the silicon wafer before the epitaxial growth process, it is possible to reduce the diffusion of boron from the silicon wafer to the silicon epitaxial layer that occurs during the epitaxial layer formation step S6. This point will be described below.
FIG. 4(a) is a schematic diagram showing a low boron concentration layer formed in the surface layer of a silicon wafer by argon annealing.
4(a), high-temperature argon annealing of the silicon wafer 11 causes outward diffusion of boron in the surface layer of the silicon wafer 11, thereby reducing the boron concentration in the surface layer. As a result, low-boron concentration layers 12, which have a lower boron concentration than the boron concentration in the thickness center C of the silicon wafer 11 where no outward diffusion of boron has occurred, are formed on the front and back surfaces of the silicon wafer 11.

FIG. 4(b) is a schematic diagram showing the boron concentration profile when epitaxial growth is performed on an argon-annealed silicon wafer.
4(b), the boron concentration after the epitaxial layer formation step S6 exhibits a concentration profile in which the boron concentration in the surface layer portion of the silicon wafer is reduced. If the region where the boron concentration is 0.9 times or less the center C of the thickness of the silicon wafer 11 where no out-diffusion of boron has occurred is defined as the low-boron concentration layer 12, the depth D of the low-boron concentration layer 12 formed on the surface side of the silicon wafer 11 that contacts the silicon epitaxial layer 13 after the epitaxial growth process can be set to 0.7 μm or more and 4.8 μm or less from the boundary between the silicon wafer 11 and the silicon epitaxial layer 13 in the thickness direction of the silicon wafer 11.
The formation of this low boron concentration layer 12 can further reduce the diffusion of boron from the silicon wafer 11 to the silicon epitaxial layer 13 that occurs during the epitaxial layer formation step S6. The thickness of the low boron concentration layer 12 can be adjusted as desired by adjusting the temperature and time of the argon annealing heat treatment.

In the pre-baking step S5 in a gas atmosphere containing hydrogen and hydrogen chloride, it is desirable to perform heat treatment on the silicon wafer in an epitaxial apparatus (Centura (registered trademark) manufactured by Applied Materials, Inc.) within the following condition ranges.
Atmosphere: hydrogen gas, hydrogen chloride gas Flow rate of hydrogen gas: 40 L/min Flow rate of hydrogen chloride gas: 1 L/min Heat treatment temperature: 1050°C or higher and 1250°C or lower Heat treatment time: 30 seconds or higher and 300 seconds or lower

The removal amount of the silicon wafer surface layer in the pre-bake step S5 is preferably 100 nm or more and 300 nm or less, and more preferably 150 nm ± 10 nm.

In the epitaxial layer forming step S6, it is desirable to grow an epitaxial layer on the silicon wafer that has been subjected to the pre-baking step S5 within the following condition range.
Dopant gas: phosphine ( _PH3 ) gas Raw material source gas: trichlorosilane ( _SiHCl3 ) gas Carrier gas: hydrogen gas Growth temperature: 1050°C or higher and 1150°C or lower Epitaxial layer thickness: 1 μm or higher and 10 μm or lower Epitaxial layer resistivity: 0.01 Ω·cm or higher and 10 Ω·cm or lower Phosphorus concentration: 4.44× ¹⁰¹⁴ atoms/ ^cm3 or higher and 4.53× ¹⁰¹⁸ atoms/ ^cm3 or lower By performing the epitaxial layer formation step S6, an epitaxial silicon wafer is manufactured in which a silicon epitaxial layer is formed on the surface of the silicon wafer.

By carrying out the above process flow, it is possible to provide a silicon wafer capable of reducing the generation of SFs in the epitaxial layer, and an epitaxial silicon wafer with a reduced SF density in the epitaxial layer.
Specifically, the present invention provides a silicon wafer to which phosphorus is added and boron is doped so that the resistivity is 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and this is a novel silicon wafer that has not existed before.

By doping with boron, the silicon wafer has a reduced defect density of large dislocation loops. This silicon wafer functions effectively as a bulk wafer for epitaxial growth, reducing the occurrence of epitaxial defects (LPDs/SFs observed on the surface of the epitaxial layer).

Furthermore, by setting the oxygen concentration of the silicon wafer to 4×10 ¹⁷ atoms/cm ³ or more and 10×10 ¹⁷ atoms/cm ³ or less, it is possible to prevent defects in the device breakdown voltage even when doped with boron.

Furthermore, by subjecting a silicon wafer to argon annealing before forming a silicon epitaxial layer, the boron concentration in the surface layer of the silicon wafer is reduced, and the amount of boron diffusion into the silicon epitaxial layer that occurs during the formation of the silicon epitaxial layer can be reduced.
By reducing the amount of boron diffused into the silicon epitaxial layer, it is possible to suppress the deterioration of electrical characteristics due to defects caused by boron incorporated into the silicon epitaxial layer during heat treatment in the device process for fabricating devices on the epitaxial silicon wafer.

In the above embodiment, the resistivity of the silicon wafer was set to 0.5 mΩ·cm or more and 1.2 mΩ·cm or less. However, for a silicon wafer with even lower resistivity, it is preferable to set the resistivity to 0.9 mΩ·cm or less. The lower the resistivity, the more pronounced the occurrence of SF in the epitaxial layer, and therefore the greater the effect of the boron doping of the present invention.

Furthermore, the silicon wafer of this embodiment is manufactured from a single crystal ingot made from a silicon melt doped with phosphorus to achieve a resistivity of 1.2 mΩ·cm or less. Due to the high concentration of phosphorus added, the oxidation-induced stacking fault (OSF) ring region, where OSFs occur during the single crystal ingot manufacturing process, disappears at the center of the ingot, resulting in a crystal region free of COPs. In other words, the silicon wafer of this embodiment can be made free of COPs by the high concentration of phosphorus added, preventing the occurrence of defects in the epitaxial layer due to COPs.

The experimental conditions and evaluation results of examples and comparative examples of the present invention will be described below.
<Dislocation loop evaluation>
The following Example 1 and Comparative Example 2 were evaluated for dislocation loops.
Example 1
In Example 1, epitaxial silicon wafers were manufactured within the range of conditions for the epitaxial silicon wafer manufacturing flow described with reference to Fig. 3. The single crystal ingot was manufactured under the growth conditions in which boron powder was added before melting the silicon raw material, and phosphorus was added to the silicon melt after melting the raw material so that the resistivity at the top end of the straight body of the single crystal ingot was 0.9 mΩ cm.
A sample wafer was cut from the top of the boron-doped single crystal ingot and processed to produce a mirror-finished silicon wafer. The resistivity of this silicon wafer was measured using the four-point probe method, and the resistivity was found to be 0.75 mΩ·cm, and the boron concentration of the silicon wafer was found to be ^1.2 × ¹⁰ atoms/cm.

<Comparative Example 1>
Compared to Example 1 above, silicon wafers were manufactured under the same manufacturing conditions as Example 1, except that boron doping was not performed during the growth stage of the single crystal ingot. As in Example 1, a sample wafer with a resistivity of 0.75 mΩ cm was cut out and subjected to a predetermined processing treatment to produce a mirror-finished silicon wafer.

The silicon wafers of Example 1 and Comparative Example 1 were cleaved in the thickness direction, and the cleaved cross sections were observed with a transmission electron microscope (TEM). Fig. 5 is a graph showing the evaluation results of dislocation loops in the silicon wafers of Example 1 and Comparative Example 1. The horizontal axis of Fig. 5 represents dislocation loop size, and the vertical axis represents dislocation loop density.
FIG. 5(a) shows the results for the silicon wafer of Comparative Example 1, which was not doped with boron. Since this sample wafer was cut from the top side of the crystal, where the residence time in the SF nucleation temperature zone is longer, many large dislocation loop defects exceeding 100 nm were observed.
On the other hand, FIG. 5( b) shows the results for the silicon wafer of Example 1, which was doped with boron at a high concentration. Since the sample wafer was cut from the top side of the crystal, where the residence time in the SF nucleation temperature zone was long, many small dislocation loops were observed, but it was confirmed that the density of large dislocation loops exceeding 100 nm was greatly reduced.
That is, it was confirmed that the density of large dislocation loops formed in the silicon wafer was reduced by boron doping.

[LPD Density Evaluation]
When a silicon epitaxial layer is formed using a sample silicon wafer cut from the top side of the straight body of an ingot, which has a long residence time in the temperature range where SF nuclei are formed, many SFs occur in the epitaxial layer, resulting in an increase in LPD density. Therefore, in this experiment, sample silicon wafers of the following Examples 2 and 3 and Comparative Examples 2 and 3 were cut from the top side of the straight body, and the LPD densities observed on the epitaxial layer surfaces after epitaxial layer formation were measured.
The specific conditions for the back surface oxide film forming process and the epitaxial layer forming process, which were carried out as common processing steps in each of the examples and comparative examples, are as follows:
[Backside oxide film formation conditions]
A backside oxide film was formed on the backside of each silicon wafer (the surface opposite to the surface on which the epitaxial film was formed) under the following conditions.
Raw material gas: mixed gas of monosilane (SiH ₄ ) and oxygen (O ₂ ) Film formation method: CVD method Film formation temperature: 400° C.
Thickness of rear surface oxide film: 550 nm
The oxide film present on the chamfered portion and the outer periphery of the back surface of each silicon wafer was removed by etching.
[Hydrogen baking conditions]
Atmosphere: Hydrogen gas Heat treatment temperature: 1200°C
Heat treatment time: 30 seconds [epitaxial film growth conditions]
Dopant gas: phosphine (PH ₃ ) gas Raw material source gas: trichlorosilane (SiHCl ₃ ) gas Carrier gas: hydrogen gas Growth temperature: 1080° C.
Epitaxial film thickness: 4 μm
Resistivity (epitaxial film resistivity): 0.3 Ω cm
<Comparative Example 2>
An epitaxial silicon wafer was manufactured by forming a silicon epitaxial layer having a thickness of 4 μm on the surface of the silicon wafer of Comparative Example 1, which was not doped with boron and in which many dislocation loops were observed.

<Comparative Example 3>
The silicon wafer of Comparative Example 1 was subjected to argon annealing (heat treatment in an argon gas atmosphere at 1200° C. for 30 minutes), and then a silicon epitaxial layer having a thickness of 4 μm was formed on the surface of the silicon wafer to produce an epitaxial silicon wafer.

Example 2
An epitaxial silicon wafer was manufactured by forming a silicon epitaxial layer having a thickness of 4 μm on the surface of the boron-doped silicon wafer of Example 1 without subjecting it to argon annealing.

Example 3
The boron-doped silicon wafer of Example 1 was subjected to argon annealing (heat treatment at 1200°C for 30 minutes in an argon gas atmosphere), and then a silicon epitaxial layer having a thickness of 4 μm was formed on the surface of the silicon wafer to produce an epitaxial silicon wafer. The epitaxial growth conditions were the same for Examples 2 and 3 and Comparative Examples 2 and 3.

The LPD density on the silicon epitaxial layer surface of the epitaxial silicon wafer of Comparative Example 2 was measured using a surface defect inspection device (Surfscan SP-1, manufactured by KLA-Tencor Corporation). Specifically, the measurement was performed in normal mode (DCN mode), and the density of LPDs of 90 nm or larger observed on the epitaxial film surface was measured. The measurement area was the epitaxial layer surface excluding an annular region extending from the outermost periphery of the epitaxial silicon wafer to 3 mm radially inward. The number of LPDs counted can be considered the number of SFs. As a result, the number of detected LPDs was so large that it overflowed (more than 100,000 per wafer), making it impossible to perform LPD measurement itself.
In Comparative Example 3, in which the silicon wafer was subjected to argon annealing, the LPD density was reduced compared to Comparative Example 2, but 280 LPDs per wafer were observed. The LPD density of each of the following Examples and Comparative Examples was measured under the same conditions as those of Comparative Example 2.

When the LPD density on the surface of the silicon epitaxial layer of the epitaxial silicon wafer of Example 2 was measured, more than 90,000 LPDs per wafer were observed. This is presumably because, although the density of large-sized complex dislocation loops in the silicon wafer was reduced by boron doping, there were still many small dislocation loops less than 100 nm in size.

In Example 3, in which the silicon wafer was argon annealed before the epitaxial growth process, the LPD density on the epitaxial layer surface was significantly reduced to 120 LPDs/wafer. This is thought to be due to the argon anneal eliminating small dislocation loops less than 100 nm in size that existed in the surface layer of the silicon wafer.

From the above, it was revealed that when boron is doped and the silicon wafer is annealed with argon, the effect of reducing SF generation in the silicon epitaxial layer is enhanced, and the LPD density after epitaxial layer formation can be reduced to about half that of Comparative Example 3.

[Boron concentration profile evaluation]
When boron is doped, boron diffusion into the silicon epitaxial layer occurs due to heat treatment during the formation of the silicon epitaxial layer. Therefore, the behavior of boron diffusion into the silicon epitaxial layer was evaluated.
Example 4
The same silicon wafer as in Example 1 (boron concentration at the center of the wafer thickness: 1.2×10 ¹⁸ atoms/cm ³ ) was prepared, and an epitaxial silicon wafer was manufactured by forming a silicon epitaxial layer similar to that in Example 2 without performing argon annealing.
Example 5
An epitaxial silicon wafer was manufactured by subjecting a silicon wafer similar to that of Example 4 to argon annealing similar to that of Example 3 and then forming a silicon epitaxial layer thereon.

Figure 6 is a graph showing the results of the boron concentration profile measurement using secondary ion mass spectrometry for the epitaxial silicon wafers of Examples 4 and 5. The horizontal axis of Figure 6 represents the depth from the surface of the epitaxial silicon wafer, and the vertical axis represents the boron concentration. It can be seen that the interface between the silicon epitaxial layer and the silicon wafer is located 4 μm deep from the surface of the epitaxial silicon wafer.

In Example 4, in which the silicon wafer was not subjected to argon annealing, the width of the low boron concentration layer was less than 0.2 μm. On the other hand, in Example 5, in which argon annealing was performed before the formation of the silicon epitaxial layer, a low boron concentration layer with a thickness of 1.4 μm was formed from the interface between the silicon epitaxial layer and the silicon wafer in the depth direction of the wafer, and it was confirmed that the boron concentration of the silicon epitaxial layer was below the detection limit (2 × ¹⁰ atoms/cm ^or less) throughout almost the entire epitaxial layer except for the vicinity of the interface with the silicon wafer.
The thickness of the low-boron concentration layer depends on the argon annealing conditions, and can be adjusted as desired by adjusting the heat treatment temperature and time in the argon annealing. By forming a low-boron concentration layer of a predetermined thickness in the surface layer portion of the silicon wafer, the amount of boron diffusion from the silicon wafer to the epitaxial layer can be reduced.

For example, with all other conditions remaining the same as in Example 5, when the heat treatment conditions were changed to 1150°C x 10 minutes, the thickness was 0.7 μm, when it was 1200°C x 10 minutes, it was 1.2 μm, when it was 1150°C x 60 minutes, it was 1.1 μm, when it was 1200°C x 60 minutes, it was 1.8 μm, and when it was 1300°C x 60 minutes, it was 4.8 μm. In other words, the thickness of the low-boron concentration layer can be adjusted as desired by adjusting the heat treatment temperature and time in argon annealing. By forming a low-boron concentration layer of a predetermined thickness in the surface layer of the silicon wafer, the amount of boron diffusion from the silicon wafer to the epitaxial layer can be reduced.

[Slip dislocation evaluation]
For the following Comparative Examples 4 and 5 and Examples 6 and 7, the presence or absence of slip dislocations (defects along the crystal plane of silicon) was investigated depending on whether or not boron doping and argon annealing were performed.
The specifications and conditions common to the silicon wafers of Comparative Examples 4 and 5 and Examples 6 and 7 are listed below.
Resistivity: 0.82mΩ・cm
Boron concentration: 1.2×10 ¹⁸ atoms/cm ³
In Comparative Example 5 and Example 7, argon annealing was performed in an argon gas atmosphere at 1200° C. for 30 minutes.
In the following description, "heat treatment corresponding to the epitaxial layer growth conditions" refers to heat treatment performed without introducing raw material source gas into the epitaxial apparatus (Centura (registered trademark) manufactured by Applied Materials, Inc.), and refers to heat treatment at 1150°C for 1 minute in a hydrogen gas atmosphere.
<Comparative Example 4>
The silicon wafer that was not doped with boron was subjected to a heat treatment corresponding to the epitaxial layer growth conditions without argon annealing (only the heat treatment was performed, and no silicon epitaxial layer was grown).
<Comparative Example 5>
The silicon wafer that was not doped with boron was subjected to argon annealing, and heat treatment corresponding to the epitaxial layer growth conditions was carried out.
Example 6
The boron-doped silicon wafer was subjected to a heat treatment corresponding to the epitaxial layer growth conditions without argon annealing.
Example 7
The boron-doped silicon wafer was subjected to argon annealing, and heat treatment corresponding to the epitaxial layer growth conditions was carried out.

Each silicon wafer was examined using X-ray topography to check for the presence or absence of slip dislocations on the wafer surface. As a result, as shown in Figure 7, no slip dislocations were observed in any of the silicon wafers, confirming that slip dislocations do not occur even when highly doped with boron.

[Verification of resistivity, boron concentration, and LPD density]
In order to verify the correlation between resistivity, boron concentration, and LPD density for the following Comparative Examples 6 and 7 and Examples 8 and 9, silicon wafers were manufactured under a plurality of conditions, epitaxial layers were formed on the surfaces of the silicon wafers, and the LPD density observed on the surfaces of the epitaxial layers was measured.
The argon annealing in the following Comparative Example 7 and Example 9 is a heat treatment at 1200° C. for 30 minutes in an argon gas atmosphere.
<Comparative Example 6>
A single crystal ingot with a resistivity ranging from 0.5 mΩ cm to 1.2 mΩ cm was grown by doping the single crystal ingot with phosphorus so that the resistivity of the upper end of the straight body of the ingot was 1.2 mΩ cm without boron doping, and multiple silicon wafers with different resistivities were manufactured from the single crystal ingot. A 4 μm thick epitaxial layer was formed on each silicon wafer without argon annealing.
Comparative Example 7
As in Comparative Example 6, single crystal ingots with resistivities ranging from 0.5 mΩ cm to 1.2 mΩ cm were grown without boron doping, and multiple silicon wafers with different resistivities were manufactured from the single crystal ingots. After argon annealing was performed on each silicon wafer without boron doping, an epitaxial layer with a thickness of 4 μm was formed.

Example 8
As in Comparative Example 6, single crystal ingots with resistivities ranging from 0.5 mΩ·cm to 1.0 mΩ·cm were grown, and multiple silicon wafers with different resistivities were produced from the single crystal ingots. Boron doping was performed so that the boron concentration at the top end of the single crystal ingot's straight body was 1.2×10 ¹⁸ atoms/cm ³ and the boron concentration at the bottom end of the single crystal ingot's straight body (solidification rate 1) was 7.0×10 ¹⁷ atoms/cm ^3. However, a 4 μm-thick epitaxial layer was formed on each silicon wafer without argon annealing.
Example 9
As in Comparative Example 6, single crystal ingots with resistivity ranging from 0.5 mΩ cm to 1.0 mΩ cm were grown, and multiple silicon wafers with different resistivities were produced from the single crystal ingots. Boron doping was performed ^so that the boron concentration at the top end of the straight body of the single crystal ingot was 1.2 × ¹⁰ atoms/cm and the boron concentration at the bottom end of the straight body of the single crystal ingot (solidification rate 1) was 7.0 × ¹⁰ atoms/cm ^. Each silicon wafer was then annealed with argon, and a 4 μm-thick epitaxial layer was formed thereon.

Figure 8 is a graph showing the relationship between the resistivity of the silicon wafer and the LPD density observed on the epitaxial layer surface for each of the epitaxial silicon wafers of Examples 8 and 9 and Comparative Examples 6 and 7. The horizontal axis of Figure 8 represents the solidification rate of the ingot body at the position where the silicon wafer was sliced, when the solidification amount of the entire length of the grown ingot body is set to 1.

As shown in Figure 8, in Example 8, in which boron doping was performed but argon annealing was not performed before the epitaxial growth process, an LPD density equivalent to the LPD density measurement results of Comparative Example 6, in which boron doping was not performed and the silicon wafer was not argon annealed, was observed, regardless of the solidification rate, and the LPD reduction effect of boron doping was not confirmed.

On the other hand, in Example 9, in which the silicon wafers were doped with boron and argon annealed before epitaxial growth, the LPD density was able to be kept below 120/wafer, even when using silicon wafers sliced from the top crystalline region, where the residence time in the SF nucleation temperature zone is longer. Furthermore, when using silicon wafers sliced from the bottom crystalline region (a crystalline region with a solidification rate of 0.6 or higher), where the residence time in the SF nucleation temperature zone is shorter, the LPD density was able to be kept below 10/wafer. This is because the high concentration of boron doping reduces dislocation loop defects, and the argon annealing of the silicon wafers eliminates the reduced dislocation loop defects. It is presumed that the synergistic effect of the high concentration of boron doping and argon annealing results in the reduction of SFs.

In Comparative Example 7, in which boron doping was not performed and the silicon wafer was argon annealed before the epitaxial growth process, the LPD density was reduced compared to Comparative Example 6. However, when silicon wafers cut from the top crystal region were used, the LPD density dropped from 100/wafer to 300/wafer.

These results demonstrate that by doping silicon wafers with boron and annealing them with argon prior to epitaxial growth, the LPD density observed on the epitaxial layer surface in all crystalline regions of a single crystal ingot can be increased to at least 120 LPDs per wafer.

10...epitaxial silicon wafer, 11...silicon wafer, 12...low boron concentration layer, 13...epitaxial layer, C...center, D...depth.

Claims (10)

A silicon wafer in which the dopant is phosphorus, the resistivity is 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and the boron concentration is 5.0×10 ¹⁴ atoms/cm ³ or more and 1.2×10 ¹⁸ atoms/cm ³ or less . a silicon wafer containing phosphorus as a dopant, having a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and containing boron;
a silicon epitaxial layer on the surface of the silicon wafer;
The silicon wafer is an epitaxial silicon wafer having a low boron concentration layer on the surface side in contact with the silicon epitaxial layer, the low boron concentration layer having a lower boron concentration than the boron concentration in the center of the thickness of the silicon wafer. the boron concentration is 5.0×10 ¹⁴ atoms/cm ³ or more and 1.2×10 ¹⁸ atoms/cm ³ or less, and
The boron concentration of the low boron concentration layer is 0.9 times or less the boron concentration at the center of the thickness of the silicon wafer, and
3. The epitaxial silicon wafer according to claim 2 , wherein the depth of the low boron concentration layer is 0.7 μm or more and 4.8 μm or less from the boundary between the silicon wafer and the silicon epitaxial layer in the thickness direction of the silicon wafer. The epitaxial silicon wafer according to claim 2 or 3 ,
The epitaxial silicon wafer has an oxygen concentration of 4×10 ¹⁷ atoms/cm ³ or more and 10×10 ¹⁷ atoms/cm ³ or less. The epitaxial silicon wafer according to claim 2 or 3 ,
An epitaxial silicon wafer in which no COPs exist in the silicon wafer. The epitaxial silicon wafer according to claim 2 or 3 ,
An epitaxial silicon wafer having an oxide film on the back surface of the silicon wafer. 7. The epitaxial silicon wafer according to claim 6 ,
An epitaxial silicon wafer in which no oxide film is present on the edge and the outer periphery of the back surface of the silicon wafer. A silicon wafer containing phosphorus as a dopant, having a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and a boron concentration of 5.0×10 ¹⁴ atoms/cm ³ or more and 1.2×10 ¹⁸ atoms/cm ³ or less,
the silicon wafer has a low boron concentration layer on its surface;
The boron concentration of the low boron concentration layer is 0.9 times or less the boron concentration at the center of the thickness of the silicon wafer, and
A silicon wafer, wherein the depth of the low boron concentration layer is 0.7 μm or more and 4.8 μm or less from the surface of the silicon wafer in the thickness direction of the silicon wafer. The silicon wafer according to claim 8 ,
The silicon wafer has an oxygen concentration of 4×10 ¹⁷ atoms/cm ³ or more and 10×10 ¹⁷ atoms/cm ³ or less. The silicon wafer according to claim 8 or claim 9 ,
The silicon wafer is free of COPs.