JP7782324B2 - Control device for bidirectional isolated DC/DC converter - Google Patents

Description

This invention relates to voltage balance control in a series connection of dual active bridge (DAB) bidirectional isolated DC/DC converters, which convert DC power to AC power using an inverter, isolate it using a transformer, and then convert it back to DC using another inverter.

Because the input and output sides of a DAB converter are insulated, multiple units can be connected in series and parallel. By designing a single DAB converter cell using a low-voltage device, mass-producing it, and connecting multiple units in series on one side and in parallel on the other, it is possible to convert DC power into low-voltage, high-current power, or vice versa, while still providing isolation.

By configuring a unit from multiple cells in this way and connecting both sides (primary and secondary sides) of this unit in series as shown in Figure 7, it is possible to step up/down and insulate high-voltage DC power. However, maintaining an even DC voltage balance between each unit becomes a challenge. In some cases, current control, voltage control, and damping control may be added to suppress DC voltage oscillations and resonance when a separate reactor is connected.

In addition, Non-Patent Documents 1 and 2 examine capacitor voltage balance control and output voltage control in a configuration in which three or more DAB converters are connected in series and parallel.

In a DC/DC converter equipped with multiple DAB converters, a conventional technique for determining the pulse width of the semiconductor switching elements in each converter is described, for example, in Non-Patent Document 3, and a conventional technique for generating gate signals for the semiconductor switching elements from pulse width command values, phase command values, etc. is described, for example, in Patent Document 1.

Furthermore, multiple units each consisting of multiple DAB converters, one connected in series and the other in parallel, can be connected in series on both sides. With this configuration, it is possible to convert very high voltage DC power into high current high voltage DC power, or vice versa, while still providing isolation. Patent Document 2 discloses such a configuration and its control method.

Patent No. 6785304 WO2017/163508

P. Zumel et al. , “Modular Dual-Active Bridge Converter Architecture,” in IEEE Transactions on Industry Applications, vol. 52, no. 3, pp. 2444-2455.2016 F. Deng. X. Znang. X. Li, T. Lei and T. Wang, “Decoupling Control Strategy for Input-Series Output-Parallel Systems Based on Dual Active Bridge dc-dc Converters, “2018 9th IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG), 2018, PP. 1-8 B. Zhao, Q. Song, W. Liu and Y. Sun. “Overview of Dual-Active-Bridge Isolated Bidirectional DC-DC Converter for High-Frequency-Link Power-Conversion System”in IEEE Transactions on Power Electronics. vol. 29. no. 8. pp. 4091-4106. Aug. 2014 Tsuboi, Tsuji, and Yamada, "Instability Phenomena in Chopper Systems with Input LC Filters and Their Countermeasures," Journal of Electrical Engineering D, Vol. 120, No. 10, pp. 1171-1181 (2000)

However, in Non-Patent Documents 1 and 2, when current control is applied, simply replacing the voltage control built into each DAB converter with current control requires high-response current control when there is a sudden change in the current command value or detected value, so information on the current command value and detected value must be communicated at high speed between the DAB converters. Even in applications where a slow response speed of current control is acceptable, high-speed communication or a large filter is required if current ripple needs to be reduced.

Patent Document 2 requires a separate auxiliary converter to maintain the DC voltage balance between each series-connected unit, which increases costs and weight accordingly.

As described above, when controlling a device consisting of multiple bidirectional isolated DC/DC converters, the challenges are maintaining DC voltage balance between the DC/DC converters and reducing communication loads and large filters. Another challenge is maintaining DC voltage balance between each unit connected in series without using an auxiliary converter.

The present invention was devised in view of the above-mentioned problems of the prior art. One aspect of the present invention is a dual active power converter (DAB) including a primary single-phase inverter whose AC side is connected to the primary winding of an isolation transformer, a secondary single-phase inverter whose AC side is connected to the secondary winding of the isolation transformer, a primary capacitor connected between the positive and negative terminals of the DC side of the primary single-phase inverter, and a secondary capacitor connected between the positive and negative terminals of the DC side of the secondary single-phase inverter. a plurality of DAB converters are provided, the plurality of DAB converters are layered into first to m (m = an integer of 2 or more) stages, the components of the first stage are the cells, a group of a predetermined number of first stage elements is a unit which is a component of the second stage, a group of a predetermined number of second stage elements is a device which is a component of the third stage, and the fourth stage and onwards are higher-level devices which are groups of a predetermined number of the devices which are the components of the previous stage, and the positive and negative terminals of the primary side single-phase inverters of z (z = an integer of 2 or more) cells are connected in series and the positive and negative terminals of the secondary side single-phase inverters are connected in parallel to form the unit, and the primary and secondary sides of the components of the second stage and onwards are connected in series within the group. A control device for a C/DC converter, the control device comprising: a current control unit that outputs a phase command value that causes a primary side DC current or a secondary side DC current to follow a set current command value; a capacitor voltage balance control unit that outputs a phase command value that reduces a deviation between a primary side capacitor voltage of a representative cell in a unit or an average voltage value obtained by dividing the primary side DC voltage of the unit by the number of cells in the unit, and the primary side capacitor voltage of a kth cell (k=an integer from 1 to z); a unit power command value calculation unit that outputs a unit power command value that controls a power command value between the primary side and secondary side of each component in the second stage and thereafter so that the DC voltages on the upstream side of power transmission in each component are equal within the assembly; a cell pulse width command value calculation unit provided in the representative cell or in each cell, which calculates a cell pulse width command value for the primary single-phase inverter and the secondary single-phase inverter of a cell based on a unit pulse width command value for the primary single-phase inverter and the secondary single-phase inverter of a unit determined by the primary capacitor voltage, the secondary capacitor voltage, the turns ratio of the primary winding and the secondary winding of the isolation transformer, and the output of the adder; and a cell pulse width command value calculation unit provided in the representative cell or in each cell, which calculates a cell pulse width command value for the primary single-phase inverter and the secondary single-phase inverter of a cell based on the unit pulse width command value for the primary single-phase inverter and the secondary single-phase inverter of the unit determined by the primary capacitor voltage, the secondary capacitor voltage, the turns ratio of the primary winding and the secondary winding of the isolation transformer, and the output of the adder. and a gate signal generation unit that generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter based on a value obtained by adding a phase command value fed back from the current control unit and the unit power command value to the cell pulse width command value. The gate signal generation unit generates a gate signal for the representative cell based on the value obtained by adding the unit power command value to the phase command value fed back from the capacitor voltage balance control unit or the phase command value fed back from capacitor voltage balance control, and the cell pulse width command value or the unit pulse width command value.

In another aspect, a dual active inverter (DAB) is provided, which includes a primary single-phase inverter whose AC side is connected to the primary winding of an isolation transformer, a secondary single-phase inverter whose AC side is connected to the secondary winding of the isolation transformer, a primary capacitor connected between the positive and negative terminals of the DC side of the primary single-phase inverter, and a secondary capacitor connected between the positive and negative terminals of the DC side of the secondary single-phase inverter. a plurality of DAB converters are provided, the plurality of DAB converters are layered into first to m (m = an integer of 2 or more) stages, the components of the first stage are the cells, a group of a predetermined number of first stage elements is a unit which is a component of the second stage, a group of a predetermined number of second stage elements is a device which is a component of the third stage, and stages 4 and onwards are higher-level devices which are groups of a predetermined number of the devices which are components of the previous stage, the positive and negative terminals of the primary side single-phase inverters of each of z (z = an integer of 2 or more) cells are connected in series and the positive and negative terminals of each of the secondary side single-phase inverters are connected in parallel to form the unit, and the primary and secondary sides of the components of the second stage and onwards are connected in series within the group. a current control unit that outputs a phase command value that causes a primary side DC current or a secondary side DC current to follow a set current command value; a capacitor voltage balance control unit that outputs a phase command value that reduces the deviation between the primary side capacitor voltage of a kth cell (k=an integer from 1 to z) and the primary side capacitor voltage of a representative cell in the unit or an average voltage value obtained by dividing the primary side DC voltage of the unit by the number of cells in the unit; and a unit power command value calculation unit that outputs a unit power command value that controls the power command value between the primary side and secondary side of each component in the second stage and thereafter so that the DC voltages on the upstream side of power transmission in each component are equal within the assembly. an adder that adds a power command value and the unit power command value; a phase difference/pulse width calculation unit that calculates a unit pulse width command value and a phase difference of the primary single-phase inverter and the secondary single-phase inverter of the unit based on the primary capacitor voltage, the secondary capacitor voltage, the turns ratio of the primary winding and the secondary winding of the isolation transformer, and the output of the adder; a cell pulse width command value calculation unit that calculates a cell pulse width command value of the primary single-phase inverter and the secondary single-phase inverter of the cell from the unit pulse width command value; and a phase difference calculation unit that calculates a phase difference determined by feedback control from the cell pulse width command value and the phase difference calculated by the phase difference/pulse width calculation unit. and a gate signal generation unit that generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter of each cell based on a phase difference command value obtained by subtracting a command value. The gate signal generation unit generates a gate signal for a representative cell based on a phase difference command value, which is the difference between the phase command value fed back from the current control unit and the phase difference calculated by the phase difference/pulse width calculation unit, and the cell pulse width command value, and generates a gate signal for the kth cell based on a phase difference command value, which is the difference between the phase command value fed back from the capacitor voltage balance control unit and the phase difference calculated by the phase difference/pulse width calculation unit, and the cell pulse width command value.

In another aspect, a dual active inverter (DAB) is provided, which includes a primary single-phase inverter whose AC side is connected to the primary winding of an isolation transformer, a secondary single-phase inverter whose AC side is connected to the secondary winding of the isolation transformer, a primary capacitor connected between the positive and negative terminals of the DC side of the primary single-phase inverter, and a secondary capacitor connected between the positive and negative terminals of the DC side of the secondary single-phase inverter. a plurality of DAB converters are provided, the plurality of DAB converters are layered into first to m (m = an integer of 2 or more) stages, the components of the first stage are the cells, a group of a predetermined number of first stage elements is a unit which is a component of the second stage, a group of a predetermined number of second stage elements is a device which is a component of the third stage, and stages 4 and onwards are higher-level devices which are groups of a predetermined number of the devices which are components of the previous stage, and a unit is formed by connecting the positive and negative terminals of the primary side single-phase inverters of z (z = an integer of 2 or more) cells in series and connecting the positive and negative terminals of the secondary side single-phase inverters in parallel, and the primary and secondary sides of the components of the second stage and onwards are connected in series within the group. a current control unit that outputs a phase command value that makes a primary side DC current or a secondary side DC current follow a set current command value; a capacitor voltage balance control unit that outputs a phase command value that reduces the deviation between the primary side capacitor voltage of a kth (k=an integer from 1 to z) cell and the primary side capacitor voltage of a representative cell in the unit or an average voltage value obtained by dividing the primary side DC voltage of the unit by the number of cells in the unit; a unit power command value calculation unit that outputs a unit power command value that controls the power command value between the primary side and secondary side of each component in the second stage and thereafter so that the DC voltages on the upstream side of power transmission in each component are equal within the assembly; a phase difference/pulse width calculation unit that calculates a unit pulse width command value and a phase difference of the primary single-phase inverter and the secondary single-phase inverter of the unit from an average voltage value obtained by dividing the primary DC voltage of the unit by the number of cells in the unit, the secondary DC voltage in the unit, a turns ratio between the primary winding and the secondary winding of the isolation transformer, and the output of the adder; a cell pulse width command value calculation unit that calculates a cell pulse width command value of the primary single-phase inverter and the secondary single-phase inverter of the cell from the unit pulse width command value; and a phase command value determined by feedback control from the cell pulse width command value and the phase difference calculated by the phase difference/pulse width calculation unit. and a gate signal generation unit that generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter of each cell based on a phase difference command value obtained by subtracting . The gate signal generation unit generates a gate signal for the representative cell based on a phase difference command value that is the difference between the phase command value for the representative cell fed back from the current control unit and the phase difference calculated by the phase difference/pulse width calculation unit, and the cell pulse width command value, and generates a gate signal for the kth cell based on a phase difference command value that is the difference between the phase command value for the kth cell fed back from the capacitor voltage balance control unit and the phase difference calculated by the phase difference/pulse width calculation unit, and the cell pulse width command value.

In one aspect, the unit power command value calculation unit controls the unit power command value of a specific component in the second or subsequent stage so that the DC voltage upstream of the power transmission of the specific component is reduced when the energy stored in the primary DC capacitor and secondary DC capacitor of the specific component is greater than that of the other components in the assembly, and controls the unit power command value of the specific component so that the DC voltage upstream of the power transmission of the specific component is increased when the energy stored in the primary DC capacitor and secondary DC capacitor of the specific component in the second or subsequent stage is less than that of the other components in the assembly.

In one aspect, the control device reduces the operating power factor of a specific component in the second stage or later if the energy stored in the primary-side DC capacitor and secondary-side DC capacitor of that component is other than the smallest among all components.

In one aspect, the control device is characterized in that, if the energy stored in the primary-side DC capacitor and secondary-side DC capacitor of a specific component in the second stage or later is other than the smallest among all components, the control device increases the DC component of the current output by that component.

According to the present invention, in a control device for a bidirectional isolated DC/DC converter, it is possible to maintain the balance of DC voltages between the DC/DC converters while reducing the communication load.

1 is a diagram showing a bidirectional isolated DC/DC converter according to first to third embodiments; 2 is an operational waveform diagram of a pulse width control method for semiconductor switching elements of the primary-side single-phase inverter and the secondary-side single-phase inverter of FIG. 1 . FIG. 2 is a block diagram showing a control device according to the first embodiment. FIG. 10 is a block diagram showing a control device according to a second embodiment. FIG. 11 is a block diagram showing a control device according to a third embodiment. FIG. 3 is a block diagram showing a control unit in each embodiment. FIG. 10 is a diagram showing a bidirectional isolated DC/DC converter according to a fourth embodiment. FIG. 10 is a block diagram showing a control device according to a fourth embodiment. FIG. 4 is a block diagram showing a unit power command value calculation unit. FIG. 4 is a block diagram showing a cell pulse width command value calculation unit. FIG. 10 is a diagram showing a bidirectional isolated DC/DC converter according to a fifth embodiment. FIG. 4 is a block diagram showing an i-th device voltage control deviation calculation unit. FIG. 10 is a block diagram showing an i-th device energy deviation calculation unit. FIG. 10 is a block diagram showing a case where the fourth and fifth embodiments are applied to the first embodiment.

Embodiments 1 to 5 of the control device for a bidirectional isolated DC/DC converter according to the present invention will be described in detail below with reference to Figures 1 to 13.

[Embodiment 1]
FIG. 1 shows the configuration of a bidirectional isolated DC/DC converter according to the first embodiment.

In Figure 1(a), which shows a configuration in which an inductor (L) is connected to the secondary side, reference numeral 1 denotes a primary-side single-phase inverter in which semiconductor switching elements S11, S21, S31, and S41 are bridge-connected, and reference numeral 2 denotes a secondary-side single-phase inverter in which semiconductor switching elements S51, S61, S71, and S81 are bridge-connected.

The connection point of the semiconductor switching elements S11 and S21 is connected to the connection point of the semiconductor switching elements S31 and S41 via the reactor _L1 and the primary winding ₃₁ of the insulating transformer 3.

The connection point of the semiconductor switching elements S51 and S61 is connected to the connection point of the semiconductor switching elements S71 and S81 via the reactor _L2 and the secondary winding ₃₂ of the insulating transformer 3.

The primary winding ₃₁ and secondary winding ₃₂ of the isolation transformer 3 are insulated from each other, and the turns ratio thereof is _N1 : _N2 .

The semiconductor switching elements S11, S21, S31, S41, S51, S61, S71, and S81 are configured, for example, as IGBTs, and switching is controlled by gate signals generated by a gate signal generation unit of the control device, which will be described later.

V _acp1 indicates the voltage at the connection point of semiconductor switching elements S11 and S21, and V _acs1 indicates the voltage at the connection point of semiconductor switching elements S51 and S61.

A primary-side capacitor _Cin is connected between the positive and negative terminals on the DC side of the primary-side single-phase inverter 1, and a secondary-side capacitor _Cout is connected between the positive and negative terminals on the DC side of the secondary-side single-phase inverter 2.

V _in1 indicates the voltage of the primary side capacitor C _in , and V _out indicates the voltage of the secondary side capacitor C _out .

The first DAB converter 10 ₁ is composed of the primary side single-phase inverter 1, primary side capacitor C _in , insulating transformer 3, secondary side single-phase inverter 2, and secondary side capacitor C _out , and n DAB converters 10 ₁ , to 10 _n , each having the same configuration as this DAB converter 10 ₁ , are provided.

Numeral 11 denotes a first DC power source, between whose positive and negative terminals are successively connected in series the positive and negative terminals of the primary side single-phase inverters 1 of n DAB converters 10 ₁ to 10 _n .

Numeral 12 denotes a second DC power supply, between whose positive and negative terminals are connected in parallel the positive and negative terminals of the secondary side single-phase inverters 2 of n DAB converters 10 ₁ to 10 _n .

An inductor 22 (L) is connected between the positive terminal of the secondary-side single-phase inverter 2 of the first DAB converter ₁₀₁ and the positive terminal of the second DC power supply 12. Note that the second DC power supply 12 is connected to, for example, a load (not shown).

_Vcc indicates the voltage of the first DC power supply 11, and _Vload indicates the voltage of the second DC power supply 12.

In FIG. 1(b), which shows a configuration in which an inductor (L) is connected to the primary side, instead of the inductor 22 in FIG. 1(a), an inductor 21 (L) is connected between the positive terminal of the primary-side single-phase inverter ₁ of the first DAB converter 101 and the positive terminal of the first DC power supply 11, and other parts are configured in the same way as in FIG. 1(a).

In addition, the inductors 21 and 22 may not be connected.

In the following specification, each of the DAB converters 10 ₁ to 10 _n may be referred to as a cell. The current and voltage of each part in Figures 1(a) and 1(b) are detected by current detectors and voltage detectors, respectively, not shown.

Figure 2 shows the operating waveforms of the pulse width control system in the control device of this first embodiment. Two upper-arm semiconductor switching elements ( _S11 and _S31 on the primary side, for example) or two lower-arm semiconductor switching elements (S21 and S41 on the primary side, for example) of the primary-side single-phase inverter 1 and secondary-side single-phase inverter 2 in each DAB converter 10 1 , . . . 10 n are simultaneously turned ON to set a period during which the output voltage is zero. Simultaneously turning ON the upper-left and lower-right switching elements (S11 and S41 on the primary side, for example) of each inverter makes the output voltage positive, and the pulse widths W11 and W21 can be adjusted by the length of the ON time. Simultaneously turning ON the lower-left and upper-right switching elements (S21 and S31 on the primary side, for example) of each inverter produces a negative voltage.

A method is being considered for using this pulse width control to expand the soft switching range even when there is a large difference in DC voltage between the primary and secondary sides. The control of this embodiment 1 can be applied to square wave control in which there is no period when the output voltage is zero in both inverters, or when pulse width control is performed on only one inverter, or on both inverters.

In this embodiment 1, the control system is divided into separate control systems for each DAB converter.

The control device in the first embodiment includes the control blocks shown in Figures 3 and 6. In Figure 3, reference numeral 30 denotes a gate signal generating unit that generates gate signals _S1(n ), S2(n), S3( _n) , S4 _(n) , S5(n), S6(n), S7 _(n) , and _{S8(n) for the primary single-phase inverters 1 and secondary single-phase inverters 2 of each of the n DAB converters 101, to, and 10n, based on pulse width command values W1(n), W2(n) for the primary single -} phase inverters 1 and secondary single-phase inverters 2 of the DAB converters 101 _{, to} , _{and 10n} , and a phase command value θFB _(n) determined by feedback control _, which will be described later.

The pulse width command values _W1(n) and W2 _(n) are determined from the input voltage (voltage Vin _(n) of primary capacitor Cin), output voltage (voltage Vout of _secondary capacitor _Cout ) of the _nth cell of each DAB converter, turns ratio _N1 / _N2 of insulating transformer 3, and power command value P*, for example, by a method described in Non-Patent Document 3.

The phase command value θ _FB(n) determined by the feedback control is generated by the control block in Fig. 6. Fig. 6(a) is applied to the device in Fig. 1(a) in which the inductor 22 is connected to the secondary side, and Fig. 6(b) is applied to the device in Fig. 1(b) in which the inductor 21 is connected to the primary side.

In FIG. 6( a), reference numeral 61 denotes a current control unit that receives as input a detected value of the current (secondary-side DC current) I _load flowing through the inductor 22 and a set current command value I _load ^* , and performs PI control on the difference between them to output a phase command value θ _acr that causes the detected value to follow the current command value.

Reference numeral 62 denotes a damping control section that receives the voltage _Vout of the secondary-side capacitor _Cout of the first DAB converter ₁₀₁ as an input and outputs a phase difference _θdump1 that suppresses resonance generated by the inductor 22 and the secondary-side capacitor _Cout .

The current (secondary side DC current) I _load flowing through the inductor 22 may be used as an input to the damping control section 62 .

The damping control unit 62 and the damping control unit 66 (described later) use the damping circuit shown in Figure 2 of Non-Patent Document 4, for example.

A subtractor 63 subtracts the output (phase difference θ _dump1 ) of the damping control unit 62 from the output (phase command value θ _acr ) of the current control unit 61 to output a phase command value θ _FB1 for the first cell.

In addition, if there is no inductor 22 and there is no risk of resonance, or if resonance is tolerable, the damping control unit 62 may be omitted.

Reference numeral 64 denotes a capacitor voltage balance control unit that inputs the voltage _Vin1 of the primary capacitor _Cin of the DAB converter ₁₀₁ of the first cell (representative cell) that serves as a reference as a command value, and the voltage Vin _(n) of the primary capacitor _Cin of the DAB converter _10n of the nth cell as a detected value of the controlled object, amplifies the deviation between the two using a controller, and outputs a phase command value _θFB(n) (=phase difference θbal _(n) ) required to make the capacitor voltage Vin _{(n) of} the nth cell follow the capacitor voltage Vin1 of the first cell.

In addition, instead of the voltage _Vin1 of the primary side capacitor _Cin of the first cell, the average voltage value ( _Vcc / _Ncell ) obtained by dividing the primary side DC voltage _Vcc of the first DC power source 11 by the number of cells (number of installed DAB converters) may be input.

In FIG. 6(b), reference numeral 65 denotes a current control unit that receives as input the detected value of the current (primary side DC current) I _in flowing through the inductor 21 and the set current command value I _in ^* , and outputs a phase command value θ _acr that causes the detected value to follow the current command value by performing PI control on the deviation between them.

Reference numeral 66 denotes a damping control section that receives the voltage _Vin1 of the primary side capacitor _Cin of the first DAB converter ₁₀₁ as an input and outputs a phase difference _θdump1 that suppresses resonance generated by the inductor 21 and the primary side capacitor _Cin .

Incidentally, as the input to the damping control section 66, either or both of the current (primary side DC current) Iin flowing through the inductor 21 _and the voltage (input voltage) _Vcc of the first DC power supply 11 may be used.

A subtractor 67 subtracts the output (phase difference θ _dump1 ) of the damping control unit 66 from the output (phase command value θ _acr ) of the current control unit 65 to output a phase command value θ _FB1 for the first cell.

In addition, if there is no inductor 21 and there is no risk of resonance, or if resonance is tolerable, the damping control unit 66 may be omitted.

64 is a capacitor voltage balance control unit configured identically to the capacitor voltage balance control unit 64 in Figure 6(a).

The subtraction output θ _FB1 (phase command value) of the subtracters 63 and 67 and the output θ _FB(n) (phase command value) of the capacitor voltage balance control unit 64 are input to the gate signal generation unit 30 as the phase command value (θ _FB(n) ) determined by feedback control.

In controlling the first cell (DAB converter 10 ₁ ), the outputs of current control units 61 and 65 (because the power supply voltage is considered constant in this embodiment 1) that control the input power or output power, and the outputs of damping control units 62 and 66 that suppress LC resonance are applied.

That is, the gate signal generating unit 30 generates a gate signal for the first cell's DAB converter 101 using the phase command value θ _FB1 and pulse width command values W _1(n) and W 2(n) obtained by subtracting the phase difference θ _dump1 output from the damping control unit ₆₂ or 66 from the phase command value θ acr output from the current control unit 61 or 65 in a subtractor _{63 or 67} and feeding it back.

In the control of the second cell and thereafter (DAB converter ₁₀₂ and thereafter), balance control of the capacitor voltage of each cell is applied. That is, the gate signal generation unit 30 generates a gate signal for the DAB converter 10n of the nth cell based on the phase command value θFB _(n) and pulse width command values _W1(n) and W2 _(n) fed back from the capacitor voltage balance control unit ₆₄ .

By dividing the control among each cell as described above, the only communication required between cells to achieve the desired control is the input voltage value and detected capacitor voltage value. Because only the first cell performs current control, high-speed communication of current command value and detected value information between each cell is not required. Furthermore, when the input is capacitive, the input voltage value does not change rapidly, reducing the communication load between cells.

In addition, this embodiment 1 can be applied regardless of the number of installed cells, and there are few changes to control when the number of cells is changed, making it possible to shorten design time. Furthermore, this embodiment 1 can be applied not only to power control on the parallel side, but also to power control on the series side.

As described above, according to this first embodiment, the signals communicated between cells are input/output voltages and capacitor voltages, which do not fluctuate suddenly, and therefore the communication load can be reduced. Therefore, a control system can be constructed using optical cables or wireless communication, which are difficult to use when the communication load is high, thereby reducing the amount of wiring required.

[Embodiment 2]
The control device in the second embodiment includes the control blocks shown in Figures 4 and 6. The second embodiment is characterized in that command values for the pulse width and phase difference are calculated in advance in order to improve the responsiveness of power control.

In Figure 4, 41 is a phase difference/pulse width calculation unit that calculates pulse width command values _W1 (n) and W2 _{(n) (} pulse widths W11 and _W21 that simultaneously _{turn on} the upper arm semiconductor switching elements or lower arm semiconductor switching elements of each inverter shown in the operating waveforms of Figure 2) and phase difference θFF _{( n) from the input voltage (voltage of primary side capacitor Cin) Vin (n)} , output voltage (voltage of secondary side capacitor Cout) _Vout , power command value P* and turns ratio N1/N2 of the insulating transformer 3 of multiple DAB converters ₁₀₁ , ..., _{10n (each cell)} .

The phase difference/pulse width calculation unit 41 performs calculations using, for example, the technology described in Non-Patent Document 3.

A subtractor 42 subtracts a phase command value θ _FB(n) determined by feedback control in each control unit in FIG. 6 from the phase difference θ _FF(n) calculated by the phase difference/pulse width calculation unit 41, and outputs a phase difference command value θ _(n) .

In this way, the subtractor 42 calculates the difference between the phase command value θ _FB(n) of the feedback control and the phase difference θ _FF calculated by the phase difference/pulse width calculation unit 41, thereby correcting the error between the transmission power and the power command value P* due to deviations in the circuit constants, detection errors, etc.

Reference numeral 43 denotes a gate signal generation unit that generates gate signals S1 _(n) , S2(n), S3(n), _S4(n) , S5(n), S6(n), S7 _(n) , and S8 _(n ) for the primary-side single-phase inverter 1 and the secondary-side single-phase inverter 2 of each DAB converter 10 ₁ , ..., 10 _n, based on the pulse width command values W 1( _{n) ,} W 2 _{( n)} calculated by the phase difference/pulse width calculation unit 41 and the phase difference command value θ _{(n) output} from the subtractor ₄₂ .

The subtraction output θ _FB1 (phase command value) of the subtractors 63 and 67 in FIG. 6 and the output θ _FB(n) (phase command value) of the capacitor voltage balance control unit 64 are input to the subtractor 42 in FIG. 4 as the phase command value θ _FB(n) determined by feedback control, and the difference with the phase difference θ _FF(n) is calculated.

In the control of the first cell (DAB converter 10 ₁ ), the outputs of the current control sections 61 and 65 and the outputs of the damping control sections 62 and 66 are applied in the same manner as in the first embodiment.

That is, the gate signal generating unit 43 generates a gate signal for the first cell DAB converter 101 using the phase difference command value θ _(n) obtained by subtracting the difference between the phase command value _θFB1 to which the output of the subtractor 63 or ₆₇ is fed back and the phase difference θFF _(n) calculated by the phase difference/pulse width calculating unit 41, and the pulse width command values W1 _(n) and W2 _(n) .

In the control of the second cell and thereafter (DAB converter ₁₀₂ and thereafter), balance control of the capacitor voltage of each cell is applied. That is, a gate signal generation unit 43 generates a gate signal for the nth DAB converter 10n using a phase difference command value θ _(n) obtained by a subtractor 42 as the difference between a phase command value θFB _(n) fed back from a capacitor voltage balance control unit 64 _and the phase difference θFF( _n ) calculated by a phase difference/pulse width calculation unit 41, and pulse width command values _W1(n) and W2 _(n) .

As described above, the phase difference/pulse width calculation unit 41 calculates the pulse width and phase difference in a feedforward manner, thereby improving the responsiveness of power control. However, due to cell loss, dead time, gate driver delays, etc., the pulse width and phase difference are not output as calculated, and the actual output power contains an error compared to the command value. In embodiment 2, feedback control is performed only for this error (current control units 61, 65). Therefore, there is no need to speed up the feedback control response compared to embodiment 1.

As described above, according to the second embodiment, the addition of a phase difference/pulse width calculation unit improves the responsiveness of power control. Furthermore, because the pulse width of each cell is changed in accordance with the capacitor voltage imbalance rate (in accordance with the output of the capacitor voltage balance control unit 64), power conversion efficiency in the transient state of capacitor voltage balance control can be improved. However, compared to the first embodiment, although it is necessary to communicate the power command value P* between each cell, the increase in communication load is slight for applications that do not require a high response speed.

[Embodiment 3]
The control device in the third embodiment includes the control blocks shown in Figures 5 and 6. In the third embodiment, some of the input parameters of the phase difference/pulse width calculation unit 41 in the second embodiment are changed to calculate the pulse width commands _W11 , _W21 and phase difference _θFF1 for the first cell, and these pulse width commands _W11 , _W21 and phase difference _θFF1 for the first cell are used to control the DAB converters of the second cell and thereafter.

In Figure 5(a) showing the control block of the first cell, reference numeral 51 denotes a phase difference/pulse width calculation unit that receives as input the average voltage value _Vcc / _Ncell (average input voltage value) obtained by dividing the voltage _Vcc of the first DC power supply 11 by the number of installed DAB converters _Ncell , the voltage _Vload of the second DC power supply 12, the power command value P*, and the turns ratio _N1 / _N2 of the primary winding and secondary winding of the isolation transformer 3, and calculates the pulse width command values _W11 , _W21 and phase difference _θFF1 of the primary side single-phase inverter ₁ and secondary side single-phase inverter 2 of the first cell DAB converter 101.

A subtractor 52 subtracts a phase command value θ _FB1 determined by feedback control of each control unit in FIG. 6 from the phase difference θ _FF1 calculated by the phase difference/pulse width calculation unit 51, and outputs a phase difference command value θ ₁ .

Reference numeral 53 denotes a gate signal generation unit that generates gate signals S11, _S21 , S31, _S41 , S51, S61, S71, and S81 for the primary-side single-phase inverter ₁ and the secondary-side single-phase inverter 2 of the first cell DAB converter ₁₀₁ based on the pulse width command values W11 and W21 calculated by the phase difference/pulse width calculation unit 51 and the phase difference command value θ1 output from the subtractor 52.

In FIG. 5B showing the control block of the DAB converter for the second cell and thereafter, reference numeral 54 denotes a subtractor that subtracts the phase command value θ FB(n) for the second cell and thereafter determined by feedback control in each control unit in FIG. 6 from the phase difference θ _FF1 for the first cell calculated by the phase difference/pulse width calculation unit 51 in FIG _{. 5A} , and outputs the phase difference command value θ _(n) for the second cell and thereafter.

The gate signal generation unit 53 in FIG. 5(b) generates gate signals (S1(n), S2(n), S3(n), _S4 (n), S5( _n) , S6 _(n) , S7(n), S8 _(n)) for the primary side single-phase inverter 1 and the secondary side single-phase inverter 2 of the DAB converters 10 ₂ , ..., 10 _n of the second and subsequent cells, based on the pulse width command values W 11 and _W 21 of the first cell calculated by the phase difference/pulse width calculation unit 51 _{and the phase difference command value} θ _{(n )} that is the output of _{the subtractor 54} .

During transient operation of the capacitor voltage balance control unit 64 in Figure 6, there is a deviation in the capacitor voltage, which causes the pulse width and phase difference to change. Since the change in pulse width acts as a disturbance to the capacitor voltage balance control and damping control, if the capacitor voltage fluctuates significantly, the responsiveness of the capacitor voltage balance control and damping control will deteriorate.

To solve this problem, in this third embodiment, the input voltage average value ( _Vcc / _Ncell ) is used as the input for calculating the phase difference and pulse width instead of the first cell capacitor voltage _Vin1 , and the same phase difference _θFF1 and pulse width command values _W11 and _W21 are used in the control systems of all cells regardless of the capacitor voltage imbalance rate. This reduces disturbance to the capacitor voltage balance control unit 64 and damping control units 62 and 66 due to fluctuations in capacitor voltage, thereby improving responsiveness.

Because the responsiveness of voltage balance control is improved in this way, the input capacitor capacitance can be reduced, enabling the device to be more compact. However, compared to embodiment 2, the number of signals to be communicated between cells increases from the power command value P* to three: _W11 , _W21 , and _θFF1 . However, the voltage Vcc of the first DC power supply 11 and the voltage Vload of the second DC power supply 12, to which the capacitors are connected, do not change suddenly. As with embodiment 2, the remaining power command value P*, _W11 , _W21 , and _θFF1, change only slowly if the application does not require a high response speed. Therefore, embodiment 3 can be applied even to low-speed communication.

[Embodiment 4]
The first to third embodiments are methods for controlling a unit consisting of multiple DAB converters, one connected in series and the other in parallel. The first to third embodiments are methods characterized by a reduction in communication load and wiring.

Embodiments 1 to 3 explain the control method for a single unit, and do not mention the control method when multiple units are connected in series on both sides.

Figure 7 shows a configuration in which a unit is made up of z (z = an integer greater than or equal to 2) DAB converters (cells) with their primary sides connected in series and their secondary sides connected in parallel, and y (y = an integer greater than or equal to 2) units connected in series on both sides. This embodiment 4 applies to the circuit in Figure 7. In Figure 7, one DAB converter is called a cell.

The main circuit configuration will be explained hierarchically. The first-level components are cells. The second-level components are units, which are collections of a certain number (z units) of cells, which are first-level components, connected in series on the primary side and in parallel on the secondary side. The third-level components are devices. Devices are collections of a certain number (y units) of units, which are second-level components, connected in series on both the primary and secondary sides.

In other words, the bidirectional isolated DC/DC converter of this fourth embodiment includes a first DC power source DCP, a second DC power source DCS, and one third-stage component between the first DC power source DCP and the second DC power source DCS. Inside the third-stage component are y second-stage components connected in series, namely, the 11th unit to the 1yth unit. Inside the second-stage component are z first-stage components, with their primary sides connected in series and their secondary sides connected in parallel, respectively, and are the 111th cell to the 11zth cell.

In Figure 7, DCP represents the first DC power supply, DCS represents the second DC power supply, Cp represents the primary side capacitor, Cs represents the secondary side capacitor, Vdcp represents the primary side DC voltage of the first DC power supply DCP, and Vdcs represents the secondary side DC voltage of the second DC power supply DCS.

Vdcp111 is the primary capacitor voltage, Vdcs111 is the secondary capacitor voltage, ip111 is the primary AC current detection value, and is111 is the secondary AC current detection value. The three-digit alphanumeric character at the end of each symbol indicates the cell number, and the two-digit alphanumeric character indicates the unit number. For example, Vdcp111 indicates the primary capacitor voltage of the 111th cell of the 11th unit, and Vdcp11 indicates the primary DC voltage of the 11th unit (the sum of the primary capacitor voltages of the 111th cells to the 11zth cells of the 11th unit).

The semiconductor switching elements S11 to S81, the primary single-phase inverter 1, and the secondary single-phase inverter 2 are the same as those in embodiments 1 to 3.

One end of reactor L1 is connected to the connection point of semiconductor switching elements S11 and S21. One end of reactor L2 is connected to the connection point of semiconductor switching elements S31 and S41. One end of reactor L3 is connected to the connection point of semiconductor switching elements S51 and S61. One end of reactor L4 is connected to the connection point of semiconductor switching elements S71 and S81.

The primary winding of the isolation transformer Tr is connected between the other end of reactor L1 and the other end of reactor L2. The secondary winding of the isolation transformer Tr is connected between the other end of reactor L3 and the other end of reactor L4. The turns ratio of the isolation transformer Tr is 1:n.

In Figure 7, reactors L1 to L4 are connected in series between the primary-side single-phase inverter 1, secondary-side single-phase inverter 2, and the isolation transformer Tr, but the leakage inductance of the isolation transformer Tr may be used instead of the reactors L1 to L4. Also, both the reactors L1 to L4 and the leakage inductance of the isolation transformer Tr may be used.

Figures 8 to 10 show block diagrams of the control device of this fourth embodiment.

In this fourth embodiment, the third embodiment is applied to the voltage balance control of each cell within a unit. Figure 8 shows the control block of the 11th unit. In this fourth embodiment, each unit has the control block of Figure 8. Like the first to third embodiments, this fourth embodiment also has the control block of Figure 6. Figure 8 differs from the third embodiment in the following respects.

Figure 8(a) shows the control block of the representative cell (cell 111 of unit 11).

An adder 85 adds a unit power command value P ₁₁ for an eleventh unit, which will be described later, to the power command value P*.

The phase difference and pulse width calculation unit 81 receives as input a value Vdcp11/z obtained by dividing the primary side DC voltage Vdcp11 of the 11th unit by the number of cells z of the unit, the secondary side DC voltage Vdcs11 of the 11th unit, the output of the adder 85, and the turns ratio 1/n of the insulating transformer Tr, and outputs unit pulse width command values Wp11, Ws11, and phase difference _θFF1 of the 11th unit.

The subtractor 82 subtracts the phase command value θ _FB1 from the phase difference θ _FF1 and outputs the result as a phase difference command value θ ₁ .

The cell pulse width command value calculation unit 86 outputs cell pulse width command values Wp111p, Wp111m, Ws111p, and Ws111m based on the unit pulse width command values Wp11 and Ws11 of the 11th unit.

The gate signal generating unit 83 generates a gate signal based on the cell pulse width command values Wp111p, Wp111m, Ws111p, and Ws111m of the 111th cell and the phase difference command value _θ1 , and generates a gate signal for the semiconductor switching element of the corresponding 111th cell.

8(b) shows the control block of the 11kth cell (2≦k≦z) of the 11th unit. A subtractor 84 subtracts the phase command value θ _FB(k) from the phase difference θ _FF1 and outputs the phase difference command value θ _(k) . A gate signal generator 83 generates a gate signal based on the cell pulse width command values Wp111p, Wp111m, Ws111p, and Ws111m and the phase difference command value θ _(k) .

Embodiment 4 applies voltage balance control to each unit. Figure 9 is a block diagram of the unit power command value (P1j) calculation unit for the 1jth unit.

The energy E1j stored in both the primary capacitor Cp and secondary capacitor Cs of the 1j unit is calculated as follows (not shown):

The energy stored in the unit's primary-side capacitor Cp is determined by applying a low-pass filter LPF to the primary-side capacitor voltages Vdcp1j1 to Vdcp1jz of z cells, squaring the result, multiplying it by the primary-side capacitor capacitance Cp, dividing by 2, and adding up the resulting values. Furthermore, the energy stored in the unit's secondary-side capacitor Cs is determined by applying a low-pass filter LPF to the secondary-side DC voltage Vdcs1j, squaring the result, multiplying it by the secondary-side capacitor capacitance Cs and the number of cells z in the unit, and dividing by 2. The sum of these two results is the energy E1j.

That is, E1j=Cp/2×(Vdcp1j1 ² +Vdcp1j2 ² + . . . Vdcp1jz ² )+zCs×Vdcs1j ² /2.

For simplicity, the energy stored in the primary capacitor Cp of the unit may be calculated approximately from the average value of the primary capacitor voltages Vdcp1j1 to Vdcp1jz of z cells. In this case, E1j ≈ Cp/2 × (Vdcp1j/z) ² + zCs × Vdcs1j ² /2.

E1avg is the average energy value stored in both the primary-side capacitor Cp and the secondary-side capacitor Cs of the 11th to 1yth units. Subtractor 91 calculates the deviation between energy E1j and the average energy value E1avg.

Amplifier 92 amplifies the output of subtractor 91 by multiplying it by gain G2. Gain G2 may be a fixed value, or its value may be varied by gain adjuster 93 based on the power command value P*, such as by decreasing it when the power command value P* is near zero as shown. The output of amplifier 92 becomes the DC voltage imbalance command value Vdc1j of the 1j unit.

The low-pass filter LPF1 removes ripple and noise at twice the frequency of the fundamental wave from the primary side DC voltage Vdcp1j of the 1j unit.

The average primary DC voltage Vdcp1avg for the 11th to 1yth units is either the sum of Vdcp11 to Vdcp1y or the primary DC voltage Vdcp divided by the number y of units.

Adder 94 calculates the deviation between the imbalance command value Vdc1j and the primary DC voltage average value Vdcp1avg, and then adds the primary DC voltage Vdcp1j of the 1jth unit to the deviation. The output of adder 94 is input to the upper terminal of switch SW1.

Low-pass filter LPF2 removes ripple and noise at twice the frequency of the fundamental wave from the secondary DC voltage Vdcs1j of the 1j unit.

Vdcs1avg is the average secondary DC voltage of the 11th to 1yth units.

The adder 95 calculates the deviation between the imbalance command value Vdc1j and the secondary DC voltage average value Vdcs1avg, and then adds the secondary DC voltage Vdcs1j of the 1jth unit to the deviation.

Multiplier 96 multiplies the output of adder 95 by the inverse of the transformer turns ratio of isolation transformer Tr, 1/n, and inverts the sign. The output of multiplier 96 is input to the lower terminal of switch SW1.

P* is the power command value transmitted between the primary and secondary sides. If the power command value P* is positive, power is transmitted from the primary side to the secondary side, and if it is negative, power is transmitted from the secondary side to the primary side. The power command value P* can be provided externally, or it can be obtained by voltage control or current control of either the primary side DC voltage Vdc1 or the secondary side DC voltage Vdc2.

Comparator 97 detects whether the power command value P* is positive. Switch SW1 outputs the input from its upper terminal if the power command value P* is positive, and outputs the input from its lower terminal if the power command value P* is zero or negative.

To prevent frequent switching of switch SW1, if the power command value P* is near zero, the previous switch state may be maintained, providing hysteresis characteristics.

If the power command value P* is zero, the average value of the deviation of the primary DC voltage of the 1j unit and the deviation of the secondary DC voltage of the 1j unit may be output.

Adder 98 adds the device voltage control deviation Vd1 to the output of switch SW1. In this embodiment 4, Vd1 = 0.

Amplifier 99 amplifies the output of adder 98 and outputs the unit power command value P1j of the 1j unit. In this example, the following two are used in combination: Proportional amplifier P1 outputs a value proportional to the output of adder 98. Gain-equipped first-order lag filter 99a amplifies the low-frequency components of the output of adder 98. Adder 99b adds the outputs of these two amplifiers and outputs the unit power command value P1j of the 1j unit. The unit power command value P1j of the 1j unit output from amplifier 99 is input to adder 85 in Figure 8.

Figure 10 shows a block diagram of the calculation unit for the cell pulse width command values (Wp1jkp, Wp1jkm, Ws1jkp, Ws1jkm) of the 1jkth cell of the 1jth unit. Figure 10 consists of the following:

Subtractor 101 subtracts unit pulse width command value Ws1j from unit pulse width command value Wp1j. Comparator 102 inputs the output of subtractor 101 and determines whether Wp1j > Ws1j. Comparator 102 may have hysteresis characteristics to avoid frequent switching of switch SW2, which will be described later.

Switch SW2 inputs unit pulse width command values Wp1j and Ws1j and outputs the smaller of the two. Switch SW3 inputs unit pulse width command values Wp1j and Ws1j and outputs the larger of the two.

E1j is the energy stored in both the primary capacitor Cp and secondary capacitor Cs of the 1jth unit. E1min is the minimum value of the energy stored in both the primary capacitor Cp and secondary capacitor Cs of each cell of the 11th to 1yth units. Subtractor 103 subtracts the minimum value E1min from energy E1j to determine the deviation.

Adder 104 adds the device energy deviation Ed1 to the deviation (output of subtractor 103). In this embodiment 4, the device energy deviation Ed1 is zero.

Amplifier 105 amplifies the output of adder 104. In this example, the following two amplifiers are used in combination: Proportional amplifier P2 outputs a value proportional to the output of adder 104. Gain-added first-order lag filter 105a amplifies the low-frequency components of the output of adder 104. Adder 105b adds the outputs of these two amplifiers. The gains of the two amplifiers can be fixed values, or they can be variable so that they increase as the power command value P* approaches zero and decrease as it moves away from zero.

Adder 106 adds the output of amplifier 105 and the output of switch SW2.

The first limiter 107 limits the output of the adder 106. The upper limit of the first limiter 107 is usually 1, and the lower limit is a value greater than zero, such as 0.2. The upper limit may also be a value slightly smaller than 1.

Subtractor 108 calculates the difference between the input and output of first limiter 107 and outputs the value that exceeds first limiter 107. Subtractor 109 subtracts the output of subtractor 108 from the output of switch SW3. Second limiter 110 limits the output of subtractor 109. The upper and lower limits of second limiter 110 are set in the same way as for first limiter 107.

The fourth switch SW4 inputs the outputs of both the first limiter 107 and the second limiter 110, and outputs the output of the second limiter 110 if Wp1j > Ws1j, otherwise it outputs the output of the first limiter 107. The value output by the fourth switch SW4 does not depend on the magnitude relationship between the unit pulse width command values Wp1j and Ws1j, and is the value obtained by adding or subtracting the output of amplifier 105 to the unit pulse width command value Wp1j.

The fifth switch SW5 inputs the outputs of both the first limiter 107 and the second limiter 110, and outputs the output of the first limiter 107 if Wp1j > Ws1j, or the output of the second limiter 110 otherwise. The value output by the fifth switch SW5 is not dependent on the magnitude relationship between the unit pulse width command values Wp1j and Ws1j, and is the value obtained by adding or subtracting the output of amplifier 105 to the unit pulse width command value Ws1j.

When Wp1j > Ws1j, the second and third switches SW2 and SW3 are switched down and the fourth and fifth switches SW4 and SW5 are switched up, and the fourth switch SW4 outputs a signal based on the unit pulse width command value Wp1j, and the fifth switch SW5 outputs a signal based on the unit pulse width command value Ws1j.

When Wp1j < Ws1j, the second and third switches SW2 and SW3 are switched up, and the fourth and fifth switches SW4 and SW5 are switched down. Even under this condition, the fourth switch SW4 outputs a signal based on the unit pulse width command value Wp1j, and the fifth switch SW5 outputs a signal based on the unit pulse width command value Ws1j.

Subtractor 111 calculates the difference between the input and output of second limiter 110 and outputs the value that exceeds second limiter 110. The output of this subtractor 111 becomes the DC component command value for the AC current.

ip1jk is the detected primary AC current value of the 1jk cell of the 1j unit. is1jk is the detected secondary AC current value of the 1jk cell of the 1j unit. Multiplier 112 multiplies the detected secondary AC current value is1jk by the turns ratio n.

Low-pass filter LPF3 extracts the DC component from the primary-side AC current detection value ip1jk. Low-pass filter LPF4 extracts the DC component from the output n×is1jk of multiplier 112.

Subtractor 113 subtracts the output of low-pass filter LPF3 from the DC component command value to obtain the deviation. Subtractor 114 subtracts the output of low-pass filter LPF4 from a value obtained by inverting the DC component command value to obtain the deviation. PI amplifiers 115 and 116 amplify the respective deviations.

Adder 117 adds the value obtained by amplifying the DC component of the primary side AC current detection value ip1jk by PI amplifier 115 to the output of fourth switch SW4, and outputs the result as cell pulse width command value Wp1jkp. Subtractor 118 subtracts the value obtained by amplifying the DC component of the primary side AC current detection value ip1jk by PI amplifier 115 from the output of fourth switch SW4, and outputs the result as cell pulse width command value Wp1jkm.

Adder 119 adds the value obtained by amplifying the DC component of the secondary-side AC current detection value is1jk by PI amplifier 116 to the output of fifth switch SW5, and outputs the result as cell pulse width command value Ws1jkp. Subtractor 120 subtracts the value obtained by amplifying the DC component of the secondary-side AC current detection value is1jk by PI amplifier 116 from the output of fifth switch SW5, and outputs the result as cell pulse width command value Ws1jkm.

In this fourth embodiment, the 11th unit, consisting of a total of z cells (cells 111 to 11z) connected in series on the primary side and in parallel on the secondary side, is regarded as the 11th unit, and control is performed by regarding the primary and secondary sides of this unit as y cells connected in series.

The voltage balance control for each cell within the unit is shown in Figure 8, and the operation is the same as in embodiment 3.

In FIG. 8 , the representative 111th cell of the 11th unit inputs Vdcp11/z, which is the primary DC voltage Vdcp11 of the 11th unit divided by the number of cells z of the unit, the secondary DC voltage Vdcs11 of the 11th unit, the power command value P* plus the unit power command value P11 of the 11th unit, and the turns ratio 1/n to determine appropriate unit pulse width command values Wp11, Ws11 and phase difference _θFF1 .

Then, the cell pulse width command value calculation unit 86 calculates the cell pulse width command values Wp111p, Wp111m, Ws111p, and Ws111m based on the unit pulse width command values Wp11 and Ws11 using the transformer bias magnetization suppression control shown in Figure 10 and discharge control due to power factor reduction when there is no load.

The subtractor 82 subtracts the phase command value θ _FB1 fed back from the current control unit 61 from the phase difference θ _FF1 , and outputs a phase difference command value θ ₁ .

The gate signal generator 83 generates a gate signal for the representative cell based on the cell pulse width command values Wp111p, Wp111m, Ws111p, and Ws111m and the phase difference command value θ _1. It also distributes the cell pulse width command values Wp111p, Wp111m, Ws111p, and Ws111m and the phase difference θ _FF1 to the other cells in the 11th unit.

The 11k-th cell performs feedback control using the capacitor voltage balance control unit 64 in Fig. 6 to equalize the primary side DC voltage Vdcp11k within the 11th unit, and generates a phase command value θFB _(k) . A subtractor 84 subtracts the phase command value θFB _(k) from the phase difference _θFF1 given from the 111-th cell, and generates a phase difference command value θ _(k) .

The gate signal generating unit 83 generates gate signals based on the phase difference command value θ _(k) and the distributed cell pulse width command values Wp111p, Wp111m, Ws111p, and Ws111m.

The voltage balance control of each unit is shown in Figures 9 and 10.

The unit power command value calculation unit outputs a unit power command value that controls the power command value between the primary and secondary sides of each second-stage component (unit) so that the DC voltage on the upstream side of the power transmission in each second-stage component (unit) is equal within the third-stage component (device).

In Figure 9, when power flows from the primary side to the secondary side, the deviation between the primary side DC voltage Vdcp1j of the 1j unit and the average primary side DC voltage value Vdcp1avg of all units is input to amplifier 99 and output as unit power command value P1j to adder 85 in Figure 8.

For example, if the primary side DC voltage Vdcp11 of the 11th unit is larger than the primary side DC voltage average value Vdcp1avg, P*+ _P11 input to FIG. 8 will also be larger than that of the other units, and each cell of the 11th unit will transfer more power from the primary side to the secondary side, thereby lowering the primary side DC voltage Vdcp11 of the 11th unit.

In addition, the downstream side will balance spontaneously without voltage balance control.

In addition, when the energy stored in the primary side DC capacitor and secondary side DC capacitor of a second-stage component (unit) is greater than that of other second-stage components (units) in the third-stage component (device), the unit power command value calculation unit controls the unit power command value of a specific second-stage component (unit) so that the DC voltage upstream of the power transmission of the specific second-stage component (unit) is reduced.

The unit power command value calculation unit controls the unit power command value of a specific second-stage component (unit) so that the DC voltage upstream of the power transmission of the specific second-stage component (unit) is increased when the energy stored in the primary-side DC capacitor and secondary-side DC capacitor of the second-stage component (unit) is smaller than that of other second-stage components (units) in the third-stage component (device).

In other words, for units with large stored energy, the unbalance command value Vdc1j increases and the unit power command value P1j output from amplifier 99 also increases, providing the function of significantly reducing the primary side DC voltage. This reduces the power received from the DC side, suppresses charging of the unit's stored energy, and reduces the difference in stored energy with other units.

In Figure 10, the positive and negative pulse widths of the AC voltage are changed according to the DC components of the primary AC current detection value ip1jk and secondary AC current detection value is1jk of the 1jk cell of the 1j unit, preventing magnetic saturation of the transformer.

The system also compares the stored energy E1j of the 1jth unit with the smallest value E1min of the stored energy of the 11th to 1yth units, and amplifies the resulting deviation. Depending on the result, it widens the pulse width of the narrower pulse with a larger DC voltage, and narrows the pulse width of the wider pulse with a smaller DC voltage.

If the energy stored in the primary DC capacitor and secondary DC capacitor of a specific component (unit) in the second stage or later is not the smallest among the components (units), the operating power factor of the component (unit) will be reduced.

The "phase difference/pulse width calculation unit 81" in Figure 8 minimizes the AC current by setting the power factor of the AC side with the higher DC voltage to 1. However, manipulating the pulse width reduces the power factor, and unnecessary current begins to flow on the AC side. This allows for intentionally increasing copper loss and conduction loss in cells with large stored energy to encourage discharge and equalize the unit DC voltage.

In addition, if the energy stored in the primary side DC capacitor and secondary side DC capacitor of a specific second-stage component (unit) is not the smallest among the other second-stage components (units), the DC component of the AC side current output by all first-stage components (cells) that make up the specific second-stage component (unit) is increased.

Depending on the operating amount that exceeds the second limiter 110, a DC component is intentionally superimposed on the primary side AC current detection value ip1jk and the secondary side AC current detection value is1jk. This also increases copper loss and conduction loss, equalizing the unit DC voltage.

By reversing the sign of the superimposed DC component in the primary side AC current detection value ip1jk and the secondary side AC current detection value is1jk, it is possible to prevent DC from being superimposed on the excitation current and prevent magnetic saturation of the transformer.

In this fourth embodiment, cell 111, which is the representative cell of unit 11, must externally input the average primary side DC voltage Vdcp11/z, power command value P*, and unit power command value P11.

Furthermore, it is necessary to output cell pulse width command values Wp111p, Wp111m, Ws111p, and Ws111m and phase difference θ _FF1 to cells 112 to 11z of the 11th unit. However, cells 112 to 11z of the 11th unit can operate simply by communicating with cell 111 of the 11th unit, which is the representative cell, without inputting any external signals.

In addition, cells 112 to 11z of the 11th unit calculate their own stored energy and transmit it to cell 111 of the 11th unit, which then calculates the sum and transmits it to the unit control unit (the unit power command value calculation unit in Figure 9 or the unit pulse width command value calculation unit in Figure 10), allowing the unit control unit to operate without knowing the state of each cell. If the stored energy is calculated approximately, cells 112 to 11z of the 11th unit do not need to transmit the stored energy. In this way, by applying this embodiment 4, the circuit shown in Figure 7 can be operated with a small communication load.

As described above, according to this fourth embodiment, it is possible to operate a circuit in which units in which one side of a DAB converter cell is connected in series and the other side in parallel are connected in series on both sides. Furthermore, it is possible to interchange power between high-voltage DC power systems and to step up and down the voltage using low-voltage components, and it is also possible to insulate the primary and secondary sides.

In addition, the voltage balance between the series-connected sides of cells and between the series-connected sides of units can be maintained evenly, allowing the withstand voltage required of components to be lowered.

Furthermore, unlike Patent Document 2, no auxiliary converter is required, which reduces costs and size.

Furthermore, this embodiment 4 can reduce communication load.

[Embodiment 5]
The fifth embodiment has a configuration in which the primary and secondary sides of the device of the fourth embodiment are connected in series as shown in Fig. 11. The control of each cell unit is applied to the fourth embodiment. The fifth embodiment is applied to the circuit of Fig. 11.

In this fifth embodiment, the first-stage components are cells, and an assembly of a predetermined number (z units) of first-stage cells is a unit, which is a component of the second stage. An assembly of a predetermined number (y units) of second-stage units connected in series is a device, which is a component of the third stage. From the fourth stage onwards, higher-level devices are assemblies of a predetermined number (x units (x = an integer greater than or equal to 2)) of third-stage devices connected in series.

In other words, the bidirectional isolated DC/DC converter of this fifth embodiment includes a first DC power source DCP, a second DC power source DCS, and first to xth devices connected between the first DC power source DCP and the second DC power source DCS. The first to xth devices include an 11th unit to a 1yth unit. The 11th unit to the 1yth unit each include a 111th cell to an 11zth cell.

In addition, the single-digit alphanumeric character at the end of each reference symbol in this embodiment 5 indicates the device number. For example, Vdcp1 indicates the primary side DC voltage of the first device.

The control device of this fifth embodiment has the control blocks shown in Figures 8, 9, and 10, and further calculates the device voltage deviation Vdi (Vd1) shown in Figure 9 and the device energy deviation Edi (Ed1) shown in Figure 10 using Figures 12 and 13.

Figure 12 is a block diagram of the i-th (i = integer from 1 to x) device voltage deviation (Vdi) calculation unit in this embodiment 5. Figure 12 differs from Figure 9 in the following respects.

The output device voltage deviation Vdi is input to the adder 98 in Figure 9.

That is, in this fifth embodiment, in FIG. 9, the power command value between the primary and secondary sides of each unit is controlled so that the DC voltages on the upstream side of the power transmission of each unit in each device are equal within the device. Also, in FIG. 12, the power command value between the primary and secondary sides of each device is controlled so that the DC voltages on the upstream side of the power transmission of each device are equal.

Also, in Figure 12, when the energy stored in the primary side DC capacitor and secondary side DC capacitor of a specific third-stage component (device) is greater than that of other third-stage components (devices) in the fourth-stage component (higher-level device), the unit power command value of the specific third-stage component (device) is controlled so that the DC voltage upstream of the power transmission of the specific third-stage component (device) is reduced.

In addition, if the energy stored in the primary side DC capacitor and secondary side DC capacitor of a specific third-stage component (device) is smaller than that of other third-stage components (devices) in the fourth-stage component (higher-level device), the unit power command value of the specific third-stage component (device) is controlled so that the DC voltage upstream of the power transmission of the specific third-stage component (device) is increased.

Figure 13 is a block diagram of the i-th device energy deviation (Edi) calculation unit. Figure 13 consists of the following:

Ei is the total accumulated energy detection value for all y units belonging to the i-th device. Emin is the minimum value of the accumulated energy of the first to x-th devices. Subtractor 131 calculates the deviation between energy Ei and the minimum energy value Emin.

Adder 132 adds 0 to the output of subtractor 131. Adder 132 is optional. Divider 133 divides the output of adder 132 by the number of apparatus constituent units y. The output of divider 133 is the i-th apparatus energy deviation Edi.

In this embodiment 5, control is performed assuming that x more devices from embodiment 4 are connected in series.

The voltage balance control of the equipment is shown in Figures 12 and 13. In Figure 12, the primary DC voltage Vdcpi and secondary DC voltage Vdcsi of the i-th equipment to be controlled are compared with the average primary DC voltage Vdcpavg and average secondary DC voltage Vdcsavg of x number of equipment. Then, depending on the direction of the power command value P*, the appropriate deviation is output from either the primary or secondary side and distributed to each unit as the equipment voltage deviation Vdi.

In the first unit, the unit voltage deviation Vdi is input as Vd1 in Figure 9, added to the output of switch SW1, and then amplified by amplifier 99. The control block in Figure 9 evens out the unit voltage balance on the side aligned with the direction of the power command value P*, and for units with small stored energy, the unit DC voltage on the side receiving power increases. Since the unit voltage deviation Vdi is input to y units of the i-th unit, it is multiplied by 1/y in advance to prevent excessive manipulation.

Figure 13 shows a control block that balances the device DC voltage by performing a discharge operation targeted at light loads and no loads. In devices with large amounts of stored energy, the device energy deviation Edi becomes large, which is output as energy deviation Ed1 in Figure 10 and is amplified by amplifier 105 in Figure 10, increasing losses in the y x z cells that make up the device.

A circuit with the same configuration can be operated by increasing the number of series units in embodiment 4 without applying embodiment 5. However, in embodiment 4, information on the DC voltage and stored energy of other units is required to control a unit, and increasing the number of series units increases the communication load and the wiring between units.

On the other hand, in this embodiment 5, a unit can operate using only information from other units within the same device, and does not require information from other devices. The unit must transmit the total amount of stored energy to the device's control block (Figures 12 and 13).

The control block of the device requires information on the device's stored energy, average value, and DC voltage, but can operate without knowing the state of each unit. By applying this embodiment 5, it is possible to reduce the communication load and wiring compared to the case in which the number of series units is increased in embodiment 4.

In this fifth embodiment, the 0 (adders 98, 132) added in Figures 12 and 13 is replaced with a higher voltage deviation, and by connecting further configurations of the fifth embodiment in series, the number of series units can be increased, making it possible to handle higher voltages.

As described above, according to this fifth embodiment, the communication load can be reduced compared to the fourth embodiment even when the number of units connected in series is increased.

The present invention has been described in detail above, only with reference to the specific examples. However, it will be obvious to those skilled in the art that numerous variations and modifications are possible within the scope of the technical concept of the present invention, and it is natural that such variations and modifications fall within the scope of the claims.

Note that while embodiments 4 and 5 have been described as examples applied to embodiment 3, they may also be applied to embodiments 1 and 2.

When applied to the first embodiment, as shown in FIG. 14 , a cell pulse width command value calculation unit 86 inputs unit pulse width command values W1(1) and W1(2) for the primary-side single-phase inverter and secondary-side single-phase inverter of the DAB converter of a unit, which are determined based on the voltages of the primary capacitors of multiple DAB converters _{(each cell)} , the voltages of the secondary capacitors, the turns ratio between the primary and secondary windings of the isolation transformer, and the sum of the power command value P _* and the unit power command value _P11 . The cell pulse width command value calculation _unit 86 calculates cell pulse width command values for the primary-side single-phase inverter and secondary-side single-phase inverter of the cell based on the unit pulse width command values W1(1) and _W1(2) . The calculated cell pulse width command values are input to the gate generators 30 of all cells in the unit, which drive the inverters of each cell based on the converted gate signals.

Furthermore, the communication load can be reduced by providing a cell pulse width command value calculation unit 86 only for the representative cell. In this case, the unit pulse width command values W1 _(n) and W2 _(n) are input directly to the gate signal generation unit for cells other than the representative cell. However, since discharge is performed only in the representative cell, problems arise, such as it taking time for the voltage balance deviation to converge to zero and the heat load being concentrated on the representative cell. To address this problem, it is sufficient to standardize the design and components used for each unit of the device to prevent imbalance in loss.

In the gate signal generating unit 30, the representative cell generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter based on the cell pulse width command value, the sum of the phase command value θ _FB(1) determined by feedback control and the unit power command value _P11 in Fig. 9 (output of the adder 87). The other cells generate gate signals for the k-th cell using the phase command value θ _FB(n) and the cell pulse width command value or the unit pulse width command value. Alternatively, the gate signal for the k-th cell may be generated using the sum of the phase command value θ _FB(n) and the unit power command value _P11 (output of the adder 87).

When applied to embodiment 2, the adder (in cells 111 to 11z) adds the unit power command value P11 to the power command value P*.

The phase difference and pulse width command values are calculated using the primary capacitor voltage, secondary capacitor voltage, turns ratio of the isolation transformer's primary and secondary windings, and the output of the adder to calculate the unit pulse width command value and phase difference for the unit's primary single-phase inverter and secondary single-phase inverter.

The cell pulse width command value calculation unit calculates the cell pulse width command values for the cell's primary single-phase inverter and secondary single-phase inverter from the unit pulse width command value (for cells 111 to 11z).

The gate signal generation unit generates gate signals for the primary single-phase inverter and secondary single-phase inverter of each cell (in cells 111 to 11z) based on the cell pulse width command value and the phase difference command value obtained by subtracting the phase command value determined by feedback control from the phase difference calculated by the phase difference/pulse width calculation unit.

The gate signal generation unit generates a gate signal for the representative cell using a phase difference command value, which is the difference between the phase command value fed back from the current control unit and the phase difference calculated by the phase difference/pulse width calculation unit, and a cell pulse width command value. The gate signal generation unit generates a gate signal for the kth cell using a phase difference command value, which is the difference between the phase command value fed back from the capacitor voltage balance control unit and the phase difference calculated by the phase difference/pulse width calculation unit, and a cell pulse width command value.

DESCRIPTION OF SYMBOLS 1... Primary side single-phase inverter 2... Secondary side single-phase inverter 3... Insulation transformer 30, 43, 53, 83... Gate signal generation unit 61, 65... Current control unit 64... Capacitor voltage balance control unit 41, 51, 81... Phase difference/pulse width calculation unit 42, 52, 54, 82, 84... Subtractor 85... Adder 86... Cell pulse width command value calculation unit

Claims (5)

a plurality of DAB (Dual Active Bridge) converters are provided, each including a primary-side single-phase inverter having an AC side connected to a primary winding of an isolation transformer, a secondary-side single-phase inverter having an AC side connected to a secondary winding of the isolation transformer, a primary-side capacitor connected between positive and negative terminals of the DC side of the primary-side single-phase inverter, and a secondary-side capacitor connected between positive and negative terminals of the DC side of the secondary-side single-phase inverter;
The plurality of DAB converters are layered into first to m (m = an integer of 2 or more) stages, the components of the first stage are cells , a predetermined number of first stage elements are aggregates of units that are components of the second stage, a predetermined number of second stage elements are aggregates of devices that are components of the third stage, and the fourth stage and onwards are aggregates of predetermined numbers of the devices that are components of the previous stage, which are higher-level devices,
A control device for a bidirectional isolated DC/DC converter in which the unit is configured by connecting the positive and negative terminals of the primary-side single-phase inverters of z (z = an integer of 2 or more) cells in series and connecting the positive and negative terminals of the secondary-side single-phase inverters in parallel, and the primary and secondary sides of components from the second stage onwards are connected in series within an assembly,
The control device
a current control unit that outputs a first phase command value that causes the primary-side DC current or the secondary-side DC current to follow a set current command value;
a capacitor voltage balance control unit that outputs a k-th phase command value that reduces the deviation between the primary capacitor voltage of the k-th cell (k=an integer from 2 to z) and the average voltage value obtained by dividing the primary capacitor voltage of a representative cell in the unit or the primary DC voltage of the unit by the number of cells in the unit;
a unit power command value calculation unit that outputs a unit power command value that increases or decreases the power transmitted between the primary side and the secondary side of each component so that the DC voltages on the upstream side of the power transmission in each component are equal within the assembly, in the second stage and thereafter;
an adder that adds a power command value, which is a command value for power transmitted between the primary side and the secondary side, to the unit power command value;
a phase difference/pulse width calculation unit that calculates a unit pulse width command value and a phase difference of the primary-side single-phase inverter and the secondary-side single-phase inverter of a unit based on the primary-side capacitor voltage, the secondary-side capacitor voltage of each cell, the turns ratio between the primary winding and the secondary winding of the isolation transformer, and the output of the adder;
a cell pulse width command value calculation unit that calculates cell pulse width command values for the primary-side single-phase inverter and the secondary-side single-phase inverter of the cell from the unit pulse width command value;
a gate signal generating unit that generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter of each cell based on the cell pulse width command value and a phase difference command value obtained by subtracting the first phase command value or the kth phase command value from the phase difference calculated by the phase difference/pulse width calculating unit,
the gate signal generating unit generates a gate signal of a representative cell based on a phase difference command value which is a difference between the first phase command value and the phase difference calculated by the phase difference/pulse width calculating unit, and the cell pulse width command value , and generates a gate signal of the kth cell based on a phase difference command value which is a difference between the kth phase command value and the phase difference calculated by the phase difference/pulse width calculating unit, and the cell pulse width command value. a plurality of DAB (Dual Active Bridge) converters are provided, each including a primary-side single-phase inverter having an AC side connected to a primary winding of an isolation transformer, a secondary-side single-phase inverter having an AC side connected to a secondary winding of the isolation transformer, a primary-side capacitor connected between positive and negative terminals of the DC side of the primary-side single-phase inverter, and a secondary-side capacitor connected between positive and negative terminals of the DC side of the secondary-side single-phase inverter;
The plurality of DAB converters are layered into first to m (m = an integer of 2 or more) stages, the components of the first stage are cells , a predetermined number of first stage elements are aggregates of units that are components of the second stage, a predetermined number of second stage elements are aggregates of devices that are components of the third stage, and the fourth stage and onwards are aggregates of predetermined numbers of the devices that are components of the previous stage, which are higher-level devices,
A control device for a bidirectional isolated DC/DC converter in which a unit is formed by connecting the positive and negative terminals of each of the primary-side single-phase inverters of z (z = an integer of 2 or more) cells in series and connecting the positive and negative terminals of each of the secondary-side single-phase inverters in parallel, and the primary and secondary sides of components from the second stage onwards are connected in series within an assembly,
The control device
a current control unit that outputs a first phase command value that causes the primary-side DC current or the secondary-side DC current to follow a set current command value;
a capacitor voltage balance control unit that outputs a k-th phase command value that reduces the deviation between the primary capacitor voltage of the k-th cell (k=an integer from 2 to z) and the average voltage value obtained by dividing the primary capacitor voltage of a representative cell in the unit or the primary DC voltage of the unit by the number of cells in the unit;
a unit power command value calculation unit that outputs a unit power command value that increases or decreases the power transmitted between the primary side and the secondary side of each component so that the DC voltages on the upstream side of the power transmission in each component are equal within the assembly, in the second stage and thereafter;
an adder that adds a power command value, which is a command value for power transmitted between the primary side and the secondary side, to the unit power command value;
a phase difference/pulse width calculation unit that calculates a unit pulse width command value and a phase difference of the primary single-phase inverter and the secondary single-phase inverter of the unit based on an average voltage value obtained by dividing the primary DC voltage of the unit by the number of cells in the unit, the secondary DC voltage of the unit, the turns ratio between the primary winding and the secondary winding of the isolation transformer, and the output of the adder;
a cell pulse width command value calculation unit that calculates cell pulse width command values for the primary-side single-phase inverter and the secondary-side single-phase inverter of the cell from the unit pulse width command value;
a gate signal generating unit that generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter of each cell based on the cell pulse width command value and a phase difference command value obtained by subtracting the first phase command value or the kth phase command value from the phase difference calculated by the phase difference/pulse width calculating unit,
the gate signal generating unit generates a gate signal of a representative cell based on a phase difference command value which is a difference between the first phase command value and the phase difference calculated by the phase difference/pulse width calculating unit, and the cell pulse width command value , and generates a gate signal of the kth cell based on a phase difference command value which is a difference between the kth phase command value and the phase difference calculated by the phase difference/pulse width calculating unit, and the cell pulse width command value. The unit power command value calculation unit
When the energy stored in the primary side DC capacitor and the secondary side DC capacitor of a specific component in the second or subsequent stage is larger than that of other components in the assembly, the unit power command value of the specific component is controlled so that the DC voltage on the upstream side of the power transmission of the specific component is reduced;
3. The control device for a bidirectional isolated DC/DC converter according to claim 1, wherein, when the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component in a second or subsequent stage is smaller than that of other components in the assembly, the unit power command value of the specific component is controlled so that the DC voltage on the upstream side of power transmission of the specific component is increased. The control device
4. The control device for a bidirectional isolated DC/DC converter according to claim 1, wherein when the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component in the second stage or later is other than the smallest among all the components, the operating power factor of the component is reduced. The control device
5. The control device for a bidirectional isolated DC/DC converter according to any one of claims 1 to 4, characterized in that, when the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component in the second stage or later is other than the smallest among all the components, the DC component of the current output by that component is increased.