JP7786209B2 - DAB bidirectional isolated DC/DC converter and its control method - Google Patents

Description

This invention relates to voltage balance control in a series connection of dual active bridge (DAB) bidirectional isolated DC/DC converters, which convert DC power to AC power using an inverter, isolate it using a transformer, and then convert it back to DC using another inverter.

Because the input and output sides of DAB converters are insulated, multiple units can be connected in series or parallel. Connecting them in parallel allows for the conversion and isolation of high-current DC power, and connecting one end in series also allows for bidirectional conversion from high-voltage power to low-voltage, high-current power. Furthermore, if a single DAB unit using a low-voltage device is designed and mass-produced, connecting multiple units in series or parallel allows for high-voltage, high-power conversion.

The problem in this case is the capacitor voltage balance at one end of the series connection. If the voltage balance is disrupted, the voltage burden will be concentrated on a specific DAB unit, causing problems such as unit overheating, element destruction due to switching surges, and component destruction due to overvoltage. If the other end is connected in parallel, the charge in the DC capacitor can be transferred to another unit via the parallel side, maintaining the series capacitor voltage balance.

However, if both ends are connected in series, charge movement is limited to within the same unit, making it difficult to maintain balance.

Non-patent document 1 and patent documents 1 to 3 describe a method for controlling the balance of capacitor voltages using an auxiliary converter. By using an auxiliary converter, it is possible to keep the deviation in capacitor voltage very small under any conditions.

Non-Patent Document 1 and Patent Document 1 use a DAB converter as the auxiliary converter, Patent Document 2 uses a chopper, and Patent Document 3 uses a resonant circuit and a voltage doubler rectifier circuit. Because the auxiliary converter in Patent Document 3 is composed only of passive elements, the capacitor voltage can be balanced without using a separate control means.

Patent document 4 describes a configuration in which a bridge cell is connected to one end of a DAB unit, and the cascade-connected bridge cells are connected to a power supply. A method for controlling the balance of capacitor voltages has been established in a cascade-connected bridge cell configuration, and it can also be used with AC power supplies. If the power supply is DC only, the number of semiconductor elements can be reduced by replacing the bridge cell with a chopper cell. A switch is connected to the other end of the DAB unit, allowing the number of DAB units connected in parallel to be freely changed depending on the number and capacity of the load.

International Publication WO2017/163508 Japanese Patent Application Laid-Open No. 2017-017868 JP 2017-017869 A Japanese Patent Application Laid-Open No. 2019-213424

Takuji Ishibashi, Takuji Jido, Osamu Mori, "Circuit Configuration and Control Method of High-Voltage, Large-Capacity DC/DC Converter for DC Transmission and Distribution Systems of Large-Scale Offshore Wind Power Generation," IEEJ Transactions on Power Generation, Vol. 138, No. 1, 2018, pp. 58-66

However, in the configurations of Non-Patent Document 1 and Patent Documents 1 to 3, the number of parts, cost, and device volume increase by the amount of the added auxiliary converters. In Patent Document 1, M-1 auxiliary converters are required for an M series configuration.

In Non-Patent Document 1, two auxiliary converters are required for a configuration with three inputs in series and three in parallel and nine outputs in series. Furthermore, the capacity design of the auxiliary converters also poses problems.

For example, Non-Patent Document 1 describes a design example that takes into account variations in semiconductor losses and reactor variations. However, it cannot address other issues, such as increases in leakage current due to aging of DC capacitors, making it impossible to maintain balance. Designing capacity with a margin of error increases costs and device volume. Furthermore, the configurations in Non-Patent Document 1 and Patent Documents 1 and 2 require separate control means for the auxiliary circuit, which increases costs by the amount of the detector and control board.

The configuration of Patent Document 3 eliminates the need for a control means. However, designing the regulated voltage is difficult. If the regulated voltage is excessive, even if the capacitor voltages are balanced, current continues to circulate between the upper and lower DAB units via the auxiliary converter, increasing losses. If the regulated voltage is insufficient, the capacitor voltage balance is significantly disrupted before current begins to flow through the auxiliary converter, increasing the deviation in capacitor voltage.

In Patent Document 4, the number of parts, costs, and device volume increase by the amount of the bridge cell and chopper cell connected to one end. A switching device is also required at the other end, which also increases the number of parts, costs, and device volume. The switching device in particular requires M x M switches for M units and M loads, significantly increasing the number of parts. If the switches use mechanical contacts, their lifespan becomes an issue, and circuit breakers compatible with DC current are large and expensive. If semiconductor switches are used, increased loss due to voltage drop becomes an issue.

As shown above, the challenge in a DAB-type bidirectional isolated DC/DC converter, in which both ends are connected in series, is to achieve equal capacitor voltage balance.

The present invention was devised in view of the above-mentioned problems of the related art, and one aspect thereof is a DAB type bidirectional isolated DC/DC converter comprising a primary side DC power supply, a secondary side DC power supply, and a plurality of cells connected between the primary side DC power supply and the secondary side DC power supply, wherein the converter comprises a primary side DC capacitor of each cell connected in series between the positive and negative poles of the primary side DC power supply, a secondary side DC capacitor of each cell connected in series between the positive and negative poles of the secondary side DC power supply, a first inverter of each cell connected to the primary side DC capacitor of each cell, a second inverter of each cell connected to the secondary side DC capacitor of each cell, and a primary winding connected to the AC side of the first inverter of each cell, and a secondary winding connected to the AC side of the second inverter of each cell. The system comprises a transformer for each cell, each having a secondary winding connected to the downstream side, and a control unit that generates gate signals for the first and second inverters. The system is hierarchically structured into first to n (n = an integer of 2 or greater) stages, with the first stage being the cells, the second stage being units that are aggregations of a predetermined number of the cells that are components, the third stage being devices that are aggregations of a predetermined number of the units that are components, and the fourth stage and beyond being higher-level devices that are aggregations of a predetermined number of the devices that are components. The control unit controls at least one of the phase difference or pulse width of the AC voltages output by the first inverter and the second inverter of each component so that the DC capacitor voltages upstream of the power transmission of each component in each aggregation are equal within the aggregation.

In one aspect, the control unit controls the phase difference between the AC voltages output by the first inverter and the second inverter of a specific component so that the DC capacitor voltage upstream of the power transmission of the specific component is reduced when the energy stored in the primary DC capacitor and the secondary DC capacitor of the specific component is greater than that of the other components in the assembly; and controls the phase difference between the AC voltages output by the first inverter and the second inverter of the specific component so that the DC capacitor voltage upstream of the power transmission of the specific component is increased when the energy stored in the primary DC capacitor and the secondary DC capacitor of the specific component is less than that of the other components in the assembly.

In one aspect, the control unit reduces the operating power factor of a component other than the component with the least amount of energy stored in the primary-side DC capacitor and the secondary-side DC capacitor.

In one aspect, the control unit increases the DC component of the current output by a component other than the component with the smallest amount of energy stored in the primary-side DC capacitor and the secondary-side DC capacitor.

In one aspect, the control unit includes a thirteenth subtractor that calculates a first energy deviation, which is the deviation between the energy stored in the primary side DC capacitor and the secondary side DC capacitor of the kth (k to 1 to z) cell of the jth (j = an integer from 1 to y) unit and the average value of the energy stored in the primary side DC capacitor and the secondary side DC capacitor of the cell of the jth unit, a fourth amplifier that amplifies the first energy deviation and outputs an unbalance voltage command value for the kth cell of the jth unit, and a fourth amplifier that amplifies the first energy deviation and outputs an unbalance voltage command value for the primary side DC capacitor of the kth cell of the jth unit. a first subtractor that subtracts a primary-side DC capacitor voltage average value of the cell of the j unit from the sum of the secondary-side DC capacitor voltage of the k-th cell of the j unit and the unbalance voltage command value of the k-th cell of the j unit to calculate a primary-side voltage deviation of the k-th cell of the j unit; a second subtractor that subtracts a secondary-side DC capacitor voltage average value of the cell of the j unit from the sum of the secondary-side DC capacitor voltage of the k-th cell of the j unit and the unbalance voltage command value of the k-th cell of the j unit to calculate a secondary-side voltage deviation of the k-th cell of the j unit; a first turns ratio multiplier that multiplies the secondary voltage deviation of the kth cell of the jth unit by -1/n, or that multiplies the secondary voltage deviation of the kth cell of the jth unit by -1 and that multiplies the primary voltage deviation of the kth cell of the jth unit by n; and a second turns ratio multiplier that outputs the primary voltage deviation of the kth cell of the yth unit when a power command value is greater than a first threshold value, outputs the secondary voltage deviation of the kth cell of the yth unit when the power command value is less than a second threshold value, and outputs the primary voltage deviation of the kth cell of the yth unit or the kth cell of the yth unit when the power command value is equal to or greater than the second threshold value and less than the first threshold value. The system comprises a first switch that outputs either or the sum of the secondary voltage deviations of the cells, or 0; an eighth adder that adds the jth unit voltage control deviation to the output of the first switch; a first amplifier that amplifies the output of the eighth adder and outputs it as the phase of the kth cell of the jth unit; and a second adder that adds a phase command value to the phase of the kth cell of the jth unit and outputs it as a phase difference command value for the kth cell of the jth unit, and controls the first inverter and the second inverter of the kth cell of the jth unit based on the phase difference command value.

In one aspect, the control unit includes a 14th subtractor that calculates a third energy deviation, which is the deviation between the energy stored in the primary DC capacitor and the secondary DC capacitor of the jth unit and the average value of the energy stored in the primary DC capacitor and the secondary DC capacitor of the unit; a 5th amplifier that amplifies the third energy deviation and outputs an unbalance voltage command value for the jth unit; a 15th subtractor that subtracts the average primary DC capacitor voltage of the unit from the sum of the primary DC capacitor voltage of the jth unit and the unbalance voltage command value of the jth unit to calculate the primary voltage deviation of the jth unit; a 16th subtractor that subtracts the average secondary DC capacitor voltage of the unit from the sum of the secondary DC capacitor voltage of the jth unit and the unbalance voltage command value of the jth unit to calculate the secondary voltage deviation of the jth unit; The system is characterized by comprising: a second turns ratio multiplier that multiplies the secondary voltage deviation of the j unit by -1/n when the secondary winding ratio is 1:n, or multiplies the secondary voltage deviation of the j unit by -1, and multiplies the primary voltage deviation of the j unit by n; a sixth switch that outputs the primary voltage deviation of the j unit if the power command value is greater than a first threshold, outputs the secondary voltage deviation of the j unit if the power command value is less than a second threshold, and outputs either the primary voltage deviation of the j unit or the secondary voltage deviation of the j unit, or the sum of both, or 0, if the power command value is greater than or equal to the second threshold and less than the first threshold; a ninth adder that adds the i-th (i = an integer from 1 to x) device voltage control deviation to the output of the sixth switch; and an eighth multiplier that multiplies the output of the ninth adder by the reciprocal of the number of cells in the unit and outputs the result as the j unit voltage control deviation.

Also, as one aspect of the invention, there is provided a ninth subtractor that calculates a second energy deviation, which is the deviation between the energy stored in the primary DC capacitor and the secondary DC capacitor of the kth cell of the jth unit and the minimum value of the energy stored in the primary DC capacitor and the secondary DC capacitor of each cell of the jth unit, a tenth adder that adds the jth unit energy deviation to the second energy deviation, a third amplifier that amplifies the output of the tenth adder, a seventh adder that adds the output of the third amplifier to the smaller of the primary pulse width command value of the kth cell of the jth unit and the secondary pulse width command value of the kth cell of the jth unit, a first limiter that limits the output of the seventh adder to within an upper limit and a lower limit, and a tenth subtractor that calculates a difference between an input value and an output value of the first limiter; an eleventh subtractor that subtracts the difference between an input value and an output value of the first limiter from the larger of the primary pulse width command value of the kth cell of the jth unit and the secondary pulse width command value of the kth cell of the jth unit; a second limiter that limits the output of the eleventh subtractor to within an upper limit value and a lower limit value; a twelfth subtractor that calculates the difference between an input value and an output value of the second limiter; a fourth switch that outputs the output of the second limiter when the primary pulse width command value of the kth cell of the jth unit is larger than the secondary pulse width command value of the kth cell of the jth unit, and otherwise outputs the output of the first limiter; a fifth switch that outputs the output of the first limiter if the value is greater than the secondary pulse width command value of the kth cell of the jth unit, and otherwise outputs the output of the second limiter; a first multiplier that multiplies the primary AC current detection value of the kth cell of the jth unit by 1/n when the turns ratio of the transformer is primary winding:secondary winding=1:n, or multiplies the secondary AC current detection value of the kth cell of the jth unit by n; a third subtractor that subtracts a DC component of the primary AC current detection value of the kth cell of the jth unit from a difference between an input value and an output value of the second limiter; and a fourth subtractor that subtracts a DC component of the secondary AC current detection value of the kth cell of the jth unit from a value obtained by inverting the sign of the difference between the input value and the output value of the second limiter. The power supply is characterized by comprising: a third adder that adds the amplified output of the third subtractor to the output of the fourth switch and outputs the result as a positive pulse width command value for the primary side of the kth cell of the jth unit; a fifth subtractor that subtracts the amplified output of the third subtractor from the output of the fourth switch and outputs the result as a negative pulse width command value for the primary side of the kth cell of the jth unit; a fourth adder that adds the amplified output of the fourth subtractor to the output of the fifth switch and outputs the result as a positive pulse width command value for the secondary side of the kth cell of the jth unit; and a sixth subtractor that subtracts the amplified output of the fourth subtractor from the output of the fifth switch and outputs the result as a negative pulse width command value for the secondary side of the kth cell of the jth unit.

In one aspect, the control unit is characterized by comprising: a 17th subtractor that subtracts the minimum value of the energy stored in the primary DC capacitor and the secondary DC capacitor of each unit from the energy stored in the primary DC capacitor and the secondary DC capacitor of the jth unit; an 11th adder that adds the i-th (i = integer from 1 to x) device energy deviation to the output of the 17th subtractor; and a 9th multiplier that multiplies the output of the 11th adder by the reciprocal of the number of cells in the unit to output the jth unit energy deviation.

In one aspect, the control unit includes an 18th subtractor that calculates a fourth energy deviation, which is the deviation between the energy stored in the primary DC capacitor and the secondary DC capacitor of the i-th device (i = an integer from 1 to x) and the average value of the energy stored in the primary DC capacitor and the secondary DC capacitor of the device; a 6th amplifier that amplifies the fourth energy deviation and outputs an unbalance voltage command value for the i-th device; a 19th subtractor that subtracts the average primary DC capacitor voltage of the device from the sum of the primary DC capacitor voltage of the i-th device and the unbalance voltage command value for the i-th device to calculate the primary voltage deviation of the i-th device; and a 20th subtractor that subtracts the average secondary DC capacitor voltage of the device from the sum of the secondary DC capacitor voltage of the i-th device and the unbalance voltage command value for the i-th device to calculate the secondary voltage deviation of the i-th device. a third turns ratio multiplier that multiplies the secondary voltage deviation of the i-th device by -1/n when the turns ratio of the transformer is primary winding:secondary winding = 1:n, or multiplies the secondary voltage deviation of the i-th device by -1 and multiplies the primary voltage deviation of the i-th device by n; a seventh switch that outputs the primary voltage deviation of the i-th device when the power command value is greater than the first threshold, outputs the secondary voltage deviation of the i-th device when the power command value is less than the second threshold, and outputs either the primary voltage deviation of the i-th device or the secondary voltage deviation of the i-th device, or the sum of both, or 0, when the power command value is equal to or greater than the second threshold and less than the first threshold; and a tenth multiplier that multiplies the output of the seventh switch by the reciprocal of the number of units of the device and outputs the result as the i-th device voltage control deviation.

In one aspect, the control unit is characterized by including a 21st subtractor that subtracts the minimum value of the energy stored in the primary DC capacitor and the secondary DC capacitor of each device from the energy stored in the primary DC capacitor and the secondary DC capacitor of the i-th device, and an 11th multiplier that multiplies the output of the 21st subtractor by the reciprocal of the number of units of the device to output the i-th device energy deviation.

In one aspect, the unit is an assembly of z (z = an integer greater than or equal to 2) of the cells, the device is an assembly of y (y = an integer greater than or equal to 2) of the units, and one of the devices is provided, and at least one of the phase difference or pulse width of the AC voltage output by the first inverter and the second inverter of each unit is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each cell in each unit are equal within the unit, and at least one of the phase difference or pulse width of the AC voltages output by the first inverter and the second inverter of each unit is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each unit are equal.

In one aspect, the system has one upper-level device, where a collection of z (z = an integer greater than or equal to 2) cells is defined as the unit, a collection of y (y = an integer greater than or equal to 2) units is defined as the device, and a collection of x (x = an integer greater than or equal to 2) devices is defined as a higher-level device, and in each unit, at least one of the phase difference or pulse width of the AC voltage output by the first inverter and the second inverter of each cell is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each cell are equal within the unit, and in each device, at least one of the phase difference or pulse width of the AC voltages output by the first inverter and the second inverter of each unit is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each unit are equal within the device, and at least one of the phase difference or pulse width of the AC voltages output by the first inverter and the second inverter of each device is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each device are equal.

This invention makes it possible to achieve equal capacitor voltage balance in a DAB-type bidirectional isolated DC/DC converter with both ends connected in series.

FIG. 2 is a diagram showing the main circuit configuration of a DAB bidirectional isolated DC/DC converter according to the first to fourth embodiments. FIG. 10 is a block diagram showing a phase difference command value calculation unit according to the first to fourth embodiments. FIG. 4 is a block diagram showing a pulse width command value calculation unit according to the first and second embodiments. FIG. 10 is a block diagram showing a gate signal generating unit according to the first to fourth embodiments. 10 is a diagram showing an example of a primary AC voltage V1k of the kth unit, a secondary AC voltage V2k of the kth unit, and gate signals T2k1, T2k2, T2k3, and T2k4. FIG. 10 is a diagram showing the influence of a primary-side DC capacitor voltage when power is transmitted from the primary side to the secondary side. 10 is a diagram showing the influence of a primary-side DC capacitor voltage when power is transmitted from the secondary side to the primary side. FIG. 10 is a block diagram showing an unbalanced voltage command value calculation unit according to a second embodiment. FIG. 11 is a block diagram showing a pulse width command value calculation unit according to a third embodiment. FIG. 10 is a block diagram showing a pulse width command value calculation unit according to a fourth embodiment. FIG. 10 is a diagram showing the main circuit configuration of a DAB bidirectional isolated DC/DC converter according to a fifth embodiment. FIG. 13 is a block diagram showing a phase difference command value calculation unit of the kth cell of the jth unit in the fifth embodiment. FIG. 13 is a block diagram showing a j-th unit voltage control deviation calculation unit in the fifth embodiment. FIG. 13 is a block diagram showing a pulse width command value calculation unit of the kth cell of the jth unit in the fifth embodiment. FIG. 13 is a block diagram showing a j-th unit energy deviation calculation unit in the fifth embodiment. FIG. 13 is a diagram showing the main circuit configuration of a DAB bidirectional isolated DC/DC converter according to a sixth embodiment. FIG. 13 is a block diagram showing a voltage control deviation calculation unit according to a sixth embodiment. FIG. 13 is a block diagram showing an energy deviation calculation unit according to a sixth embodiment.

Embodiments 1 to 6 of the DAB bidirectional isolated DC/DC converter of the present invention will be described in detail below with reference to Figures 1 to 18.

[Embodiment 1]
The first to fourth embodiments are based on the assumption that they are applied to the circuit shown in Fig. 1. The left side is the primary side, and the right side is the secondary side, with m cells (DAB converters) connected in series on both sides. The first to m-th cells are connected between the primary side DC power supply DC1 and the secondary side DC power supply DC2.

The primary-side DC capacitors C1 of the first to mth cells are connected in series across the primary-side DC power supply DC1. The first and second switching elements S1 and S2 are connected in series across the primary-side DC capacitor C1 of each cell. The third and fourth switching elements S3 and S4 are connected in series across the primary-side DC capacitor C1 of each cell. The first to fourth switching elements S1 to S4 form the first inverter.

Secondary-side DC capacitors C2 of the first to mth cells are connected in series across the secondary-side DC power supply DC2. Fifth and sixth switching elements S5 and S6 are connected in series across the secondary-side DC capacitor C2 of each cell, respectively. Seventh and eighth switching elements S7 and S8 are connected in series across the secondary-side DC capacitor C2 of each cell. The fifth to eighth switching elements S5 to S8 form a second inverter.

Note that in Figure 1, capacitors are connected in parallel to the first through eighth switching elements, but these capacitors can be omitted.

One end of reactor L1 is connected to the connection point between the first and second switching elements S1 and S2. One end of reactor L2 is connected to the connection point between the third and fourth switching elements S3 and S4. One end of reactor L3 is connected to the connection point between the fifth and sixth switching elements S5 and S6. One end of reactor L4 is connected to the connection point between the seventh and eighth switching elements S7 and S8.

The primary winding of the transformer Tr is connected between the other end of the reactor L1 and the other end of the reactor L2. The secondary winding of the transformer Tr is connected between the other end of the reactor L3 and the other end of the reactor L4. The first inverter, second inverter, transformer Tr, primary side DC capacitor C1, secondary side DC capacitor C2, and reactors L1 to L4 form one cell. In this embodiment 1, there are first to m-th cells (m: integer greater than or equal to 2).

In Figure 1, reactors L1 to L4 are connected in series between the first inverter, second inverter and transformer Tr, but the leakage inductance of the transformer Tr may be used instead of reactors L1 to L4. Also, both reactors L1 to L4 and the leakage inductance of the transformer Tr may be used.

The voltage of the primary DC power supply DC1 is Vdc1, the voltage of the secondary DC power supply DC2 is Vdc2, the primary DC capacitor voltages of the primary DC capacitor C1 of the first through mth cells are Vdc11 to Vdc1m, the secondary DC capacitor voltages of the secondary DC capacitor C2 of the first through mth cells are Vdc21 to Vdc2m, the primary AC voltage of the kth cell is V1k, the secondary AC voltage of the kth cell is V2k, the primary AC current of the kth cell is i1k, and the secondary AC current of the kth cell is i2k. Here, k is an integer between 1 and m.

Figures 2 to 4 show block diagrams of the control unit of the kth cell in the circuit configuration of Figure 1 in this embodiment 1. The control unit generates gate signals for the first and second inverters. Figure 2 is a block diagram of the phase difference command value (θk) calculation unit of the kth cell.

The first low-pass filter LPF1 removes ripple and noise at twice the frequency of the fundamental wave from the primary-side DC capacitor voltage Vdc1k of the kth cell.

The primary side DC capacitor voltage average value Vdc1avg is either the sum of the primary side DC capacitor voltages Vdc11 to Vdc1m or the primary side DC voltage Vdc1 divided by the number of cells m.

The first subtractor 1 subtracts the primary DC capacitor voltage average value Vdc1avg from the sum of the primary DC capacitor voltage Vdc1k of the kth cell to which the first low-pass filter LPF1 is applied and the unbalance voltage command value Vdck* of the kth cell to obtain the primary voltage deviation of the kth cell. In this embodiment 1, Vdck* = 0.

The second low-pass filter LPF2 removes ripple and noise at twice the frequency of the fundamental wave from the secondary-side DC capacitor voltage Vdc2k of the kth cell. The secondary-side DC capacitor voltage average value Vdc2avg is the sum of the secondary-side DC capacitor voltages Vdc21 to Vdc2m or the secondary-side DC voltage Vdc2 divided by the number of cells m.

The second subtractor 2 subtracts the secondary DC capacitor voltage average value Vdc2avg from the sum of the secondary DC capacitor voltage Vdc2k of the kth cell applied with the second low-pass filter LPF2 and the unbalance voltage command value Vdck* of the kth cell to obtain the secondary voltage deviation of the kth cell.

P* in Figure 2 is the power command value transmitted between the primary and secondary sides. If the power command value P* is positive, power is transmitted from the primary side to the secondary side, and if it is negative, power is transmitted from the secondary side to the primary side. The power command value P* can be provided externally, or it can be obtained by voltage control or current control of either the primary side DC voltage Vdc1 or the secondary side DC voltage Vdc2.

The first comparator 3 determines whether the power command value P* is positive. The first turns ratio calculator 4 multiplies the output of the second subtractor 2 (secondary voltage deviation) by the reciprocal of the turns ratio of the transformer Tr multiplied by -1. The first turns ratio calculator 4 may also multiply the output of the second subtractor 2 (secondary voltage deviation) by -1, and multiply the output of the first subtractor 1 (primary voltage deviation) by the turns ratio n of the transformer Tr. Here, the turns ratio of the transformer Tr is primary:secondary = 1:n.

The first switch SW1 outputs the primary voltage deviation of the kth cell if the power command value P* is positive, and outputs the output of the first turns ratio calculator 4 if the power command value P* is zero or negative.

To prevent frequent switching of the first switch SW1, if the power command value P* is near zero, the previous switch state may be maintained to provide hysteresis characteristics. Also, if the power command value P* is zero, the average value of the primary voltage deviation of the kth cell and the output of the first turns ratio calculator 4 may be output.

The first amplifier 5 amplifies the output of the first switch SW1 and outputs the phase θkb of the kth cell. In this example, the following two amplifiers are used in combination.

The proportional amplifier P1 outputs a value proportional to the output of the first switch SW1. The gain-added first-order lag filter 5a amplifies the low-frequency components of the output of the first switch SW1.

The first adder 6 adds the outputs of these two amplifiers and outputs the phase θkb. The second adder 7 adds a separately provided phase command value θ* to the phase θkb and outputs the phase difference command value θk for the kth cell.

The phase command value θ* may be given by feedback control of the DC side current or voltage. It may also be calculated from the power command value P*, the primary side DC capacitor voltage Vdc1k of the kth cell, and the secondary side DC capacitor voltage Vdc2k of the kth cell.

Here, when the phase θkb, phase command value θ*, and phase difference command value θk of the kth cell are positive, the phase of the primary AC voltage V1k of the kth cell leads relative to the secondary AC voltage V2k of the kth cell, and power is transmitted from the primary side to the secondary side.

Figure 3 shows a block diagram of the pulse width command value (W1kp, W1km, W2kp, W2km) calculation unit.

The third low-pass filter LPF3 extracts the DC component of the primary AC current detection value i1k of the kth cell.

The first multiplier 8 multiplies the secondary-side AC current detection value i2k of the kth cell by the turns ratio n. The fourth low-pass filter LPF4 extracts the DC component from the output (n × i2k) of the first multiplier 8.

In Figure 3, the secondary side AC current detection value i2k of the kth cell is multiplied by the turns ratio n of the transformer Tr, but the primary side AC current detection value i1k of the kth cell may also be multiplied by the reciprocal of the turns ratio n (1/n).

The third subtractor 9 subtracts the output of the third low-pass filter LPF3 from the DC component command value to obtain the deviation. The fourth subtractor 10 subtracts the output of the fourth low-pass filter LPF4 from the DC component command value to obtain the deviation. In embodiments 1, 2, and 3, the DC component command value is zero.

The PI amplifier 11 amplifies the deviation calculated by the third subtractor 9. The PI amplifier 12 amplifies the deviation calculated by the fourth subtractor 10.

The third adder 13 adds the output of the PI amplifier 11, which inputs the kth cell's primary side pulse width command value W1k and the kth cell's primary side AC current detection value i1k, and outputs the kth cell's primary side positive side pulse width command value W1kp.

The fifth subtractor 14 subtracts the output of the PI amplifier 11, which receives the primary AC current detection value i1k of the kth cell as input, from the primary pulse width command value W1k of the kth cell, and outputs the negative primary pulse width command value W1km of the kth cell.

The fourth adder 15 adds the output of the PI amplifier 12, which receives the kth cell's secondary pulse width command value W2k and the kth cell's secondary AC current detection value i2k as input, and outputs the kth cell's positive secondary pulse width command value W2kp.

The sixth subtractor 16 subtracts the output of the PI amplifier 12, which receives the secondary AC current detection value i2k of the kth cell as input, from the secondary pulse width command value W2k of the kth cell, and outputs the negative secondary pulse width command value W2km of the kth cell.

Figure 4 shows a block diagram of the gate signal generation unit.

The second multiplier 17 multiplies the phase difference command value θk of the kth cell by 0.5. The third multiplier 18 multiplies the output of the second multiplier 17 (0.5θk) by -1 and inverts the sign.

The gate generator 19 inputs the output of the second multiplier 17 (0.5θk), the positive pulse width command value W1kp for the primary side of the kth cell, and the negative pulse width command value W1km for the primary side of the kth cell, adds a dead time, and outputs gate signals T1k1, T1k2, T1k3, and T1k4. Gate signal T1k1 controls the first switching element S1 of the kth cell, gate signal T1k2 controls the second switching element S2, gate signal T1k3 controls the third switching element S3, and gate signal T1k4 controls the fourth switching element S4.

The gate generator 20 inputs the output (-0.5θk) of the third multiplier 18, the positive side pulse width command value W2kp for the secondary side of the kth cell, and the negative side pulse width command value W2km for the secondary side of the kth cell, adds dead time, and outputs gate signals T2k1, T2k2, T2k3, and T2k4. Gate signal T2k1 controls the fifth switching element S5 of the kth cell, gate signal T2k2 controls the sixth switching element S6, gate signal T2k3 controls the seventh switching element S7, and gate signal T2k4 controls the eighth switching element S8.

Figure 5 shows an example of the kth cell's primary AC voltage V1k, the kth cell's secondary AC voltage V2k, and gate signals T2k1, T2k2, T2k3, and T2k4. In this example, the kth cell's phase difference command value θk is positive, the phase of the kth cell's primary AC voltage V1k leads the phase of the kth cell's secondary AC voltage V2k, and power is transmitted from the primary side to the secondary side.

In this first embodiment, we will demonstrate capacitor voltage balance control under conditions where a certain amount of power is being transmitted. The balance control approach will be explained using Figures 6 and 7.

Figure 6 shows only the primary side extracted from Figure 1. Power is transmitted from the primary side to the secondary side, and the transmitted power of each cell is assumed to be equal. Consider the case where the primary side DC capacitor voltage Vdc1k of the kth cell exceeds the primary side DC capacitor voltage average value Vdc1avg, and the primary side DC capacitor voltage Vdc1m of the mth cell is insufficient compared to the primary side DC capacitor voltage average value Vdc1avg.

Because DAB cells are connected in series, the DC current flowing through each cell is constant. Because the primary-side DC capacitor voltage Vdc1k of the kth cell is greater than the primary-side DC capacitor voltages of the other cells, the power input to the kth cell also increases. However, because the power transmitted to the secondary side by the kth cell is equal to that of the other cells, the input power becomes excessive and charges the primary-side DC capacitor C1, further increasing the primary-side DC capacitor voltage Vdc1k of the kth cell.

The primary side DC capacitor voltage Vdc1m of the mth cell is smaller than the primary side DC capacitor voltages of the other cells, so the power input to the mth cell decreases. To transmit the same amount of power as the other cells, the primary side DC capacitor C1 of the mth cell must be discharged, which further reduces the primary side DC capacitor voltage Vdc1m of the mth cell.

As a result of the above, when power is transferred from the primary side to the secondary side, the voltage balance of the primary side DC capacitor C1 is unstable and requires control.

On the other hand, consider the case where power is transferred from the secondary side to the primary side, as shown in Figure 7. Figure 7 shows only the primary side extracted from Figure 1. The primary side DC capacitor voltage Vdc1k of cell k is greater than the primary side DC capacitor voltages of the other cells, and the power output by cell k also increases. However, because the power received by cell k from the secondary side is equal to that of the other cells, the input power is insufficient compared to the output power, and this is made up by the discharge of cell k's primary side DC capacitor C1. As a result, cell k's primary side DC capacitor voltage Vdc1k decreases.

The primary side DC capacitor voltage Vdc1m of the mth cell is smaller than the primary side DC capacitor voltages of the other cells, and the power output by the mth cell also decreases. Because the power received by the mth cell from the secondary side is equal to that of the other cells, the power received by the mth cell from the secondary side is in excess of the output, and the excess is charged to the primary side DC capacitor C1 of the mth cell, causing the primary side DC capacitor voltage Vdc1m of the mth cell to increase.

From the above, when power is transmitted from the secondary side to the primary side, the voltage balance of the primary-side DC capacitor C1 is stable, and although a certain degree of deviation occurs, it balances spontaneously without the need for control. This balancing effect increases as the transmitted power increases, but if the transmitted power is small, balancing becomes more difficult and the deviation increases. If the transmitted power is zero, the balancing effect disappears and the system becomes unstable.

In this first embodiment, when the power command value P* is positive and power is transmitted from the primary side to the secondary side, the primary-side DC capacitor voltage is balanced. As shown in FIG. 2, when the power command value P* is positive, the first switch SW1 switches to the upper side, and the deviation between the primary-side DC capacitor voltage Vdc1k of the kth cell and the primary-side DC capacitor voltage average value Vdc1avg is input to the first amplifier 5.

If the primary-side DC capacitor voltage Vdc1k of the kth cell is excessive, the deviation is positive, and the phase θkb amplified by the first amplifier 5 is also positive. As a result, the phase of the primary-side AC voltage V1k of the kth cell leads the secondary-side AC voltage V2k of the kth cell, and the phase difference is greater than that of the other cells. In the kth cell, more power is transmitted from the primary side to the secondary side than in the other cells, and the primary-side DC capacitor voltage Vdc1k of the kth cell decreases, reducing the deviation.

If the primary side DC capacitor voltage Vdc1k of the kth cell is insufficient, the deviation will be negative. The power transmitted from the primary side to the secondary side by the kth cell will be less than that of the other cells, and the primary side DC capacitor voltage Vdc1k of the kth cell will increase.

The above operation balances the primary-side capacitor voltage. However, the charge required to balance the primary-side capacitor voltage is supplied from the secondary-side capacitor, which worsens the secondary-side capacitor voltage balance.

However, as mentioned above, the secondary-side capacitor voltage balance is stable. Therefore, although some deviation occurs, the secondary-side capacitor voltage will converge to a point where the power transmitted from the cell and the power output are balanced.

When the power command value P* is zero or negative and power is transmitted from the secondary side to the primary side, the secondary-side capacitor voltage is balanced. When the power command value P* is negative, the first switch SW1 switches to the lower side, and the deviation between the kth cell's secondary-side DC capacitor voltage Vdc2k and the secondary-side DC capacitor voltage average value Vdc2avg is input to the first amplifier 5.

If the secondary-side DC capacitor voltage Vdc2k of the kth cell is excessive, the deviation will be negative and the phase θkb amplified by the first amplifier 5 will also be negative. The phase of the primary-side AC voltage V1k of the kth cell will lag behind the secondary-side AC voltage V2k of the kth cell, and the phase difference will be greater than that of the other cells. In the kth cell, more power is transmitted from the secondary side to the primary side than in the other cells, and the secondary-side DC capacitor voltage Vdc2k of the kth cell will decrease.

If the secondary-side DC capacitor voltage Vdc2k of the kth cell is insufficient, the deviation will be positive. The power transmitted from the primary side to the secondary side by the kth cell will be less than that of the other cells, and the secondary-side DC capacitor voltage Vdc2k of the kth cell will increase.

The voltage balance of the primary side DC capacitor C1 is not controlled but stabilizes spontaneously.

The first amplifier 5 in Figure 2 does not use an integrator. The reason for this is explained below. An integrator has the characteristic of having infinite DC gain, which reduces DC deviation to zero and makes the capacitor voltage, which is the object of control, equal to the command value.

However, in Figure 1, which is the control object in this case, the sum of the cell capacitor voltages (Vdc1 on the primary side) is determined by external factors such as the connected voltage source and a separately provided constant DC current control. Therefore, once the cell capacitor voltage of m-1 units is determined, the capacitor voltage of the remaining unit is inevitably determined. The controlled object has m-1 degrees of freedom, but if it is controlled using m controllers, there will not be enough degrees of freedom and the control will become unstable.

In particular, if there is an error in the detector, the integrating amplifier of one cell will increase its output in an attempt to reduce the deviation, including the error, to zero, which will increase the deviation of another cell, causing the integrating amplifier of that cell to increase its output, and the amplifier output may increase without limit.

As a countermeasure, the DC gain is limited and control is performed using a proportional amplifier P1 and a first-order lag filter with gain 5a to allow for any small remaining deviation. Another countermeasure is to perform balance control by replacing the amplifiers in Figure 2 with PI amplifiers in m-1 cells, and not perform the balance control in Figure 2 in the remaining cells (for example, the first cell) and fix the phase θ1b at zero.

In Figure 2, when the power command value P* is zero, the secondary-side DC capacitor voltage is balanced, but the primary-side DC capacitor voltage may also be balanced. When the power command value P* is close to zero and changes sign frequently, such as in a no-load standby state, the first switch SW1 may be given a hysteresis characteristic in its switching to prevent frequent sudden changes in the phase θkb.

Control may be performed by inputting the average value of the primary-side voltage deviation and the secondary-side voltage deviation to the first amplifier 5. That is, the first amplifier 5 amplifies the primary-side voltage deviation when the power command value P* is greater than the first threshold, amplifies the secondary-side voltage deviation when the power command value P* is less than the second threshold, and amplifies either the primary-side voltage deviation or the secondary-side voltage deviation, or the sum of both (average values), when the power command value P* is equal to or greater than the second threshold and less than the first threshold, or outputs 0 as the phase θkb of the kth cell.

However, this first embodiment alone cannot balance the capacitor voltage when the power command value P* = 0. To address this issue, it must be combined with the third embodiment, which will be described later.

In this first embodiment, if the absolute value of the transmitted power is sufficiently large, the balance deviation of the capacitor voltage on the non-controlled side can be kept sufficiently small. However, there is a problem in that the deviation becomes larger when the load becomes lighter and the absolute value of the transmitted power becomes smaller.

As described above, according to this embodiment 1, it is possible to maintain a balance between the DC capacitor voltages on both the primary and secondary sides when the transmission power is relatively high.

It also prevents voltage loads from being concentrated on specific cells, preventing overheating and component damage due to overvoltage, and damage to switching elements due to surges.

In addition, there is no need to increase the voltage resistance of components, reducing costs. Furthermore, compared to conventional technology, no auxiliary circuitry is required, which not only reduces costs but also allows the device to be made more compact.

[Embodiment 2]
FIG. 8 shows a block diagram of the unbalanced voltage command value (Vdck*) calculation unit of the kth cell in the second embodiment.

The fifth low-pass filter LPF5 extracts the DC component by removing ripple and noise at twice the frequency of the fundamental wave of the primary-side DC capacitor voltage Vdc1k of the kth cell. The sixth low-pass filter LPF6 extracts the DC component of the secondary-side DC capacitor voltage Vdc2k of the kth cell.

The fourth multiplier 21 calculates the square of the primary side DC capacitor voltage Vdc1k of the kth cell when the fifth low-pass filter LPF5 is applied. The fifth multiplier 22 calculates the square of the secondary side DC capacitor voltage Vdc2k of the kth cell when the sixth low-pass filter LPF6 is applied.

The sixth multiplier 23 multiplies the output of the fourth multiplier 21 by the value obtained by dividing the primary-side capacitor capacitance C1 by 2. The seventh multiplier 24 multiplies the output of the fifth multiplier 22 by the value obtained by dividing the secondary-side capacitor capacitance C2 by 2.

The fifth adder 25 adds the outputs of the sixth and seventh multipliers 23 and 24 to obtain the energy Ek stored in the primary side DC capacitor C1 and secondary side DC capacitor C2 connected on both sides of the kth cell.

The seventh subtractor 26 calculates the first energy deviation, which is the deviation between the energy Ek and the average value Eavg of the energy stored in the primary side DC capacitor C1 and secondary side DC capacitor C2 of all cells.

The second amplifier 27 amplifies the output of the seventh subtractor 26 by multiplying it by a gain G2. The gain G2 may be a fixed value, or, as shown in FIG. 8, the gain adjuster 28 may vary the value based on the power command value P*, such as by decreasing the gain when the power command value P* is near zero. The output of the second amplifier 27 becomes the unbalance voltage command value Vdck*.

In this second embodiment, we will explain a method for reducing deviation under light loads, which is one of the problems with the first embodiment.

In this second embodiment, the energy Ek stored in the primary-side DC capacitor C1 and secondary-side DC capacitor C2 of the kth cell is first calculated. Next, the deviation between the average energy Eavg of each cell calculated in the same way and the energy Ek is calculated. This is amplified by a gain G2, and the obtained value is used as the unbalanced voltage command value Vdck* of the kth cell.

The operation of this second embodiment will be explained. As an example, assume that P*>0 and the primary-side DC capacitor voltage is the control target. In this case, Vdc11 to Vdc1m have approximately equal values due to the control of the first embodiment, so the stored energy of the primary-side DC capacitors is approximately equal.

The energy Ek reflects the magnitude of the secondary DC capacitor voltage Vdc2k of the kth cell. If the secondary DC capacitor voltage Vdc2k of the kth cell is greater than the average secondary DC capacitor voltage Vdc2avg, the energy Ek will also be greater than the average energy Eavg, and the unbalance voltage command value Vdck* will be positive.

This unbalance voltage command value Vdck* is input to the first and second subtractors 1 and 2 in Figure 2. The first subtractor 1 subtracts the primary side DC capacitor voltage average value Vdc1avg from the sum of the primary side DC capacitor voltage Vdc1k of the kth cell after applying the first low-pass filter LPF1 and the unbalance voltage command value Vdck* of the kth cell, to obtain the primary side voltage deviation of the kth cell.

As a result, the balance control command value (Vdc1avg - Vdck*) decreases, and the primary DC capacitor voltage Vdc1k of cell k also decreases. Because the DC current flowing through each cell is constant, the power received by cell k from the primary DC voltage Vdc1 decreases. Because cell k's primary DC capacitor voltage Vdc1k is the object of control, the decrease in received power is reflected in the magnitude of cell k's secondary DC capacitor voltage Vdc2k, and cell k's secondary DC capacitor voltage Vdc2k decreases, allowing it to approach the average secondary DC capacitor voltage Vdc2avg.

When P*<0 and the secondary capacitor voltage is the control target of embodiment 1, the magnitude of the primary DC capacitor voltage Vdc1k of the kth cell is reflected in the energy Ek. If the primary DC capacitor voltage Vdc1k of the kth cell is smaller than the primary DC capacitor voltage average value Vdc1avg, the energy Ek will also be smaller than the average energy Eavg, and the unbalance voltage command value Vdck* will be negative.

This unbalance voltage command value Vdck* is input to the first and second subtractors 1 and 2 in Figure 2. The second subtractor 2 subtracts the secondary DC capacitor voltage average value Vdc2avg from the sum of the secondary DC capacitor voltage Vdc2k of the kth cell after applying the second low-pass filter LPF2 and the unbalance voltage command value Vdck* of the kth cell, thereby obtaining the secondary voltage deviation of the kth cell.

As a result, the balance control command value (Vdc2avg - Vdck*) increases, and the secondary DC capacitor voltage Vdc2k of the kth cell also increases. The power that the kth cell receives from the secondary DC voltage Vdc2 increases, increasing the primary DC capacitor voltage Vdc1k of the kth cell and bringing it closer to the primary DC capacitor voltage average value Vdc1avg.

In this second embodiment, a small amount of capacitor voltage imbalance is intentionally generated on the primary side when P*>0 and on the secondary side when P*<0, i.e., on the upstream side of power transmission. This makes it possible to improve the capacitor voltage imbalance on the secondary side when P*>0 and on the primary side when P*<0, i.e., on the downstream side.

In this second embodiment, when the energy Ek stored in the primary side DC capacitor and secondary side DC capacitor of the kth cell (k = an integer from 1 to m) is greater than that of the other cells, the phase difference between the AC voltages output by the first inverter and second inverter of the kth cell is controlled so that the DC capacitor voltage upstream of the kth cell's power transmission is reduced; and when the energy Ek stored in the primary side DC capacitor and secondary side DC capacitor of the kth cell is less than that of the other cells, the phase difference between the AC voltages output by the first inverter and second inverter of the kth cell is controlled so that the DC capacitor voltage upstream of the kth cell's power transmission is increased.

In this second embodiment, the input to the second amplifier 27 is not the downstream capacitor voltage in the power transmission, but the total energy stored in the cell's primary-side DC capacitor C1 and secondary-side DC capacitor C2. The reason for this is explained below. If P*>0, it is also possible to set the input to the second amplifier 27 to Vdc2k-Vdc2avg.

However, for example, if the secondary DC capacitor voltage Vdc2k of the kth cell is large, reducing the primary DC capacitor voltage Vdc1k of the kth cell will reduce the power received by the secondary DC capacitor C2 of the kth cell. However, to lower the primary DC capacitor voltage Vdc1k of the kth cell, the primary DC capacitor C1 of the kth cell must be discharged. The discharged charge moves to the secondary DC capacitor C2 of the kth cell via the DAB converter, causing the secondary DC capacitor voltage Vdc2k of the kth cell to increase further.

As a result, the above-mentioned operation will attempt to further reduce the primary-side DC capacitor voltage Vdc1k of the kth cell. This makes the control system more likely to become unstable, making it impossible to set a large value for gain G2, and resulting in very little effect.

On the other hand, the energy Ek stored in the primary side DC capacitor C1 and secondary side DC capacitor C2 is constant even when the charge is transferred, unlike the capacitor voltage, so the control system is more stable, a high gain can be set, and sufficient effect can be obtained.

As mentioned above, it is preferable to use energy Ek as the input to the second amplifier 27, but the input to the second amplifier 27 may also be the downstream DC capacitor voltage. In this case, if the DC capacitor voltage downstream of the kth cell's power transmission is higher than that of the other cells, the phase difference between the AC voltages output by the first inverter and second inverter of the kth cell is controlled so that the DC capacitor voltage upstream of the kth cell's power transmission is reduced; and if the DC capacitor voltage downstream of the kth cell's power transmission is lower than that of the other cells, the phase difference between the AC voltages output by the first inverter and second inverter of the kth cell is controlled so that the DC capacitor voltage upstream of the kth cell's power transmission is increased.

In this second embodiment, the effect is obtained when there is a load, but when there is no load, even if the capacitor voltage on the upstream side of the power transmission is changed, the received power is zero and no difference occurs, so no effect is obtained. Therefore, when the power command value P* is near zero, the gain G2 can be set to zero to prevent unnecessary deviations from occurring.

By combining this second embodiment with the first embodiment, it is possible to keep the capacitor voltage balance deviation sufficiently small even when the absolute value of the transmitted power is small. However, there is a problem in that when there is no load, the control means is lost and the deviation becomes large.

By combining embodiment 1 and embodiment 2, it is possible to maintain voltage balance between the DC capacitors on both the primary and secondary sides even when the transmission power is low.

Compared to embodiment 1, the balance on the side where the balance was evenly achieved will be slightly worse, but embodiment 1 can improve the voltage balance on the side where deviation occurred.

This allows the withstand voltage of the components to be lower than in embodiment 1. Compared to when embodiment 3 is used alone or in combination with embodiment 1, losses can be reduced under conditions of low transmission power.

[Embodiment 3]
9 shows a block diagram of a calculation unit for pulse width command values (W1kp, W1km, W2kp, W2km) according to the third embodiment. FIG. 9 differs from FIG. 3 in the following respects.

In this third embodiment, it is assumed that the primary pulse width command value W1k of the kth cell and the secondary pulse width command value W2k of the kth cell are calculated as follows:

The primary DC voltage Vdc1 is compared with the secondary DC voltage Vdc2/n, which takes the winding ratio into account, and the pulse width command value for the smaller voltage is set to a fixed value close to 1, for example, between 0.7 and 1. Alternatively, it may be set to a variable value with an upper limit of between 0.7 and 1 that is small when the power command value P* is close to zero and increases as the power command value P* moves away from zero.

The pulse width command value for the higher voltage is _W1 in the following equation (1). Note that _W2 in equation (1) is the pulse width command value for the lower voltage. Also, θ in equation (1) is the value obtained by amplifying, by a PI amplifier, the deviation between the power command value P* and the product of the secondary DC voltage Vdc2 and the secondary DC current Idc2, after noise has been removed using a low-pass filter.

The eighth subtractor 29 subtracts the secondary pulse width command value W2k of the kth cell from the primary pulse width command value W1k of the kth cell. The second comparator 30 inputs the output of the eighth subtractor 29 and determines whether W1k > W2k. The second comparator 30 may have a hysteresis characteristic to avoid frequent switching of the switch described below.

The second switch SW2 inputs the primary pulse width command value W1k of the kth cell and the secondary pulse width command value W2k of the kth cell, and outputs W2k if W1k > W2k, or W1k if W1k ≦ W2k, i.e., the smaller of W1k and W2k. The third switch SW3 inputs the primary pulse width command value W1k of the kth cell and the secondary pulse width command value W2k of the kth cell, and outputs W1k if W1k > W2k, or W2k if W1k ≦ W2k, i.e., the larger of W1k and W2k.

The ninth subtractor 31 calculates a second energy deviation, which is the deviation between the energy Ek stored in the primary DC capacitor and secondary DC capacitor of the kth cell and the minimum value Emin of the energy stored in the primary DC capacitor and secondary DC capacitor of each cell among all cells.

The third amplifier 32 that amplifies the second energy deviation uses the following two amplifiers in combination in this example: The proportional amplifier P2 outputs a value proportional to the second energy deviation calculated by the ninth subtractor 31. The first-order lag filter with gain 32a amplifies the low-frequency components of the second energy deviation calculated by the ninth subtractor 31. The sixth adder 33 adds the output of the proportional amplifier P2 and the output of the first-order lag filter with gain 32a.

The seventh adder 34 adds the output of the third amplifier 32 and the output of the second switch SW2. The first limiter 35 limits the output of the seventh adder 34. The upper limit of the first limiter 35 is usually 1, and the lower limit is a value greater than zero, such as 0.2. The upper limit may also be a value slightly smaller than 1.

The tenth subtractor 36 calculates the difference between the input and output of the first limiter 35 and outputs the value that exceeds the first limiter 35. The eleventh subtractor 37 subtracts the output of the tenth subtractor 36 from the output of the third switch SW3. The second limiter 38 limits the output of the eleventh subtractor 37. The upper and lower limits of the second limiter 38 are set in the same way as the first limiter 35.

The fourth switch SW4 inputs the outputs of both the first limiter 35 and the second limiter 38, and outputs the output of the second limiter 38 if W1k > W2k; otherwise, it outputs the output of the first limiter 35.

The value output by the fourth switch SW4 is the sum of the amplifier output and the primary pulse width command value W1k of the kth cell, regardless of the magnitude relationship between the primary pulse width command value W1k of the kth cell and the secondary pulse width command value W2k of the kth cell.

The fifth switch SW5 inputs the outputs of both the first limiter 35 and the second limiter 38, and outputs the output of the first limiter 35 if W1k > W2k, and outputs the output of the second limiter 38 otherwise.

The value output by the fifth switch SW5 is the value obtained by subtracting the amplifier output from the secondary pulse width command value W2k of the kth cell, regardless of the magnitude relationship between the primary pulse width command value W1k of the kth cell and the secondary pulse width command value W2k of the kth cell.

The third adder 13 adds the value obtained by amplifying the DC component of the primary side AC current detection value i1k of the kth cell using the PI amplifier 11 to the output of the fourth switch SW4, and outputs the result as the primary side positive side pulse width command value W1kp. The fifth subtractor 14 subtracts the value obtained by amplifying the DC component of the primary side AC current detection value i1k of the kth cell using the PI amplifier 11 from the output of the fourth switch SW4, and outputs the result as the primary side negative side pulse width command value W1km.

The fourth adder 15 adds the DC component of the secondary AC current detection value i2k of the kth cell, amplified by the PI amplifier 12, to the output of the fifth switch SW5, and outputs the result as the secondary side positive pulse width command value W2kp. The sixth subtractor 16 subtracts the DC component of the secondary AC current detection value i2k of the kth cell, amplified by the PI amplifier 12, from the output of the fifth switch SW5, and outputs the result as the secondary side negative pulse width command value W2km.

In this third embodiment, we will explain a method for reducing the capacitor voltage imbalance when there is no load, which was a problem with the first and second embodiments.

First, as in embodiment 2, the energy Ek stored in the primary side DC capacitor and secondary side DC capacitor of the kth cell is calculated and input. Then, the minimum value Emin of the energy stored in the primary side DC capacitor and secondary side DC capacitor of each cell is determined, and a second energy deviation, which is the deviation from the energy Ek of the kth unit, is input to the third amplifier 32.

The pulse widths of the primary AC voltage V1k of the kth cell and the secondary AC voltage V2k of the kth cell are manipulated based on the output of the third amplifier 32. The narrower pulse width is first widened, and once the limiter is exceeded, the wider pulse width is narrowed.

The operation of this embodiment 3 will be explained using an example where the secondary DC voltage Vdc2 is small, the secondary pulse width command value W2k = 0.7 to 1, the primary DC voltage Vdc1 is large, the primary pulse width command value W1k = (1), and the DC capacitor stored energy Ek of the kth cell is not minimum.

When the output of the third amplifier is zero, the pulse width of the kth cell's secondary inverter output voltage is set wide, and the AC side operates at a power factor of 1. The primary inverter output voltage has a narrow pulse width, and all of the reactive power supplied to the transformer and reactor is shared. This reduces the primary AC current detection value i1k and the secondary AC current detection value i2k, reducing copper loss and conduction loss.

Here, if the DC capacitor stored energy Ek of the kth cell is not minimum, the output of the third amplifier becomes positive, and by widening the narrow pulse width of the primary inverter output voltage of the kth cell, the reactive power supplied to the AC side becomes excessive, and the secondary inverter of the kth cell operates at a leading power factor.

The occurrence of unnecessary reactive power exchange increases the amplitude of the primary side AC current detection value i1k and the secondary side AC current detection value i2k, which also increases copper loss and conduction loss, accelerating the discharge of the capacitor voltage.

If the capacitor voltage is not sufficiently discharged even when the pulse width of the primary inverter output voltage of the kth cell is widened to 1, the pulse width of the secondary inverter output voltage of the kth cell is narrowed. This further increases the reactive power supplied to the AC side, further reducing the capacitor voltage.

For cells with the smallest capacitor stored energy, the output of the third amplifier is zero, so the pulse width is not changed, and the secondary pulse width command value W2k = 0.7 to 1 and the primary pulse width command value W1k = (1) operate in the same way, reducing losses and suppressing capacitor discharge. This operation improves the balance of the capacitor voltage.

In this embodiment 3, for cells other than those with the smallest energy Ek stored in the primary side DC capacitor and secondary side DC capacitor, the smaller pulse width of the primary side pulse width command value W1k and the secondary side pulse width command value W2k is widened, or the larger pulse width is narrowed, or both are done, to correct the primary side pulse width command value W1k and the secondary side pulse width command value W2k so that the reactive power output from the cell is increased (so that the operating power factor is reduced), and the corrected values are output as the primary side positive side pulse width command value W1kp, the primary side negative side pulse width command value W1km, the secondary side positive side pulse width command value W2kp, and the secondary side negative side pulse width command value W2km.

Furthermore, for cells other than those with the smallest DC capacitor voltage downstream of the kth cell in power transmission, the smaller pulse width of the primary pulse width command value W1k and the secondary pulse width command value W2k may be widened, or the larger pulse width may be narrowed, or both may be done, to correct the primary pulse width command value W1k and the secondary pulse width command value W2k so that the reactive power output by that cell is increased (so that the operating power factor is reduced), and the results may be output as the primary side positive pulse width command value W1kp, the primary side negative pulse width command value W1km, the secondary side positive pulse width command value W2kp, and the secondary side negative pulse width command value W2km.

In this third embodiment, first and second limiters 35, 38 are set for the pulse width. The upper limits of the first and second limiters 35, 38 are usually 1, but may be set to approximately 0.7 to 0.95. If the lower limits of the first and second limiters 35, 38 are set to 0, no AC voltage will be output, power transmission will be impossible, and control will become impossible. For this reason, they are set to a value greater than 0, such as approximately 0.2.

In this third embodiment, priority is given to widening the narrower pulse width when manipulating the pulse width, but priority may also be given to narrowing the wider pulse width. Alternatively, both pulse widths may be manipulated equally.

In this embodiment, the gains P2 and G2 of the third amplifier 32 are constant. However, in the case of embodiments 1 and 2, if there is a load, the capacitor voltage can be balanced without applying embodiment 3. Therefore, if the power command value P* is not 0, the gain can be switched to 0, thereby reducing losses. The gain can also be set to 0 under relatively large conditions, such as when the absolute value of the power command value P* is 0.1 or greater. By intentionally generating losses even under light loads, efficiency will decrease slightly, but the deviation in the capacitor voltage balance can be reduced. The gain switching can be given a hysteresis characteristic, and the gain can be changed based on the absolute value of the power command value P*.

In embodiment 3, losses are intentionally generated, which naturally increases the thermal load of the cells. However, embodiment 3 is applied assuming no load or light load, and in this case copper loss, conduction loss, and switching loss are very small, with no-load losses such as iron loss accounting for the majority of losses. Therefore, the losses of the other cells are simply adjusted to match the cell with the largest no-load loss, and the increase in loss is small.

For example, unless an extreme increase in loss occurs due to an abnormality such as a crack in the transformer Tr iron core increasing the magnetic flux density at the relevant location and increasing hysteresis loss, or the insulation of the laminated steel plate being damaged by impact and increasing eddy current loss, or deterioration over time increasing the leakage current of a capacitor, there is no need to enlarge the cooling mechanism.

According to this third embodiment, even when the transmission power is zero, the voltage balance between the primary and secondary DC capacitors can be maintained and operation can continue. A converter with this configuration can also be used in applications where no-load standby situations occur frequently.

By using this in combination with embodiment 1 or embodiment 2, the voltage balance deviation of the DC capacitor can be reduced, although losses will increase under certain conditions of transmission power.

Furthermore, under conditions where the transmission power is relatively high, the control gain of this embodiment 3 can be reduced to disable this embodiment and prevent a decrease in efficiency. Furthermore, unlike the fourth embodiment described below, the ripple generated on the DC side is twice the fundamental frequency, so it can be removed with a small filter.

[Embodiment 4]
10 shows a block diagram of a calculation unit for pulse width command values (W1kp, W1km, W2kp, W2km) according to the fourth embodiment. FIG. 10 differs from FIG. 9 in the following respects.

In this fourth embodiment, a twelfth subtractor 39 is added. The twelfth subtractor 39 calculates the difference between the input and output of the second limiter 38 and outputs the value that exceeds the second limiter 38.

The output of this twelfth subtractor 39 is used as the DC component command value for the primary AC current of the kth cell and is used by the third subtractor 9. Furthermore, the signal with the sign of the output of the twelfth subtractor 39 inverted is used as the DC component command value for the secondary AC current of the kth cell and is used by the fourth subtractor 10.

The third subtractor 9 subtracts the output of the third low-pass filter LPF3 from the output of the twelfth subtractor 39. The fourth subtractor 10 subtracts the output of the fourth low-pass filter LPF4 from the value obtained by inverting the output of the twelfth subtractor 39.

In embodiment 3, the pulse width is changed to intentionally increase losses and reduce the capacitor voltage balance deviation when there is no load. However, there is a limit to the pulse width that can be changed, and it cannot deal with capacitor voltage balance disturbances that exceed this limit, as described above.

This fourth embodiment describes a method for reducing the balance deviation of the capacitor voltage even when a larger balance disturbance occurs at no load.

In embodiment 3, the narrower pulse width is widened, but if the manipulated variable exceeds the limiter, the wider pulse width is narrowed by the amount; again, if the limiter is exceeded, no operation is performed for that amount.

In this fourth embodiment, even when narrowing the wider pulse width, the amount that exceeds the limiter is detected, and the excess amount is used as the command value for the DC component of the primary side AC current detection value i1k of the kth cell and the secondary side AC current detection value i2k of the kth cell.

By superimposing a DC component on the primary side AC current detection value i1k of the kth cell and the secondary side AC current detection value i2k of the kth cell, a larger loss can be generated and the capacitor can be discharged.

The DC component command value to be applied is set in opposite directions for the primary AC current detection value i1k of the kth cell and the secondary AC current detection value i2k of the kth cell. In this fourth embodiment, the first multiplier 8 multiplies the primary AC current detection value i1k by 1/n, or the secondary AC current detection value i2k by n. This causes the DC components of the magnetic flux generated by both the primary and secondary currents in the iron core inside the high-frequency transformer to cancel each other out, preventing magnetic saturation of the iron core.

In this fourth embodiment, for cells other than those in which the energy Ek stored in the primary side DC capacitor and secondary side DC capacitor is the smallest among all cells, the primary side pulse width command value W1k and secondary side pulse width command value W2k are corrected so that the DC component of the current output by the cell in question is increased, and these are output as the primary side positive side pulse width command value W1kp, the primary side negative side pulse width command value W1km, the secondary side positive side pulse width command value W2kp, and the secondary side negative side pulse width command value W2km.

In addition, for cells other than those with the smallest DC capacitor voltage downstream in power transmission, the primary pulse width command value W1k and secondary pulse width command value W2k may be corrected so that the DC component of the current output by the cell is increased, and the corrected values may be output as the primary positive pulse width command value W1kp, the primary negative pulse width command value W1km, the secondary positive pulse width command value W2kp, and the secondary negative pulse width command value W2km.

In this fourth embodiment, increasing reactive power on the AC side is given high priority as a means of generating losses, while superimposing DC on AC current is given low priority. The reason for this is explained below. When reactive power is increased, ripples of twice the fundamental frequency are generated on the DC side. When DC is superimposed, ripples of a frequency equal to the fundamental frequency are generated. If the ripple frequency is low, problems arise such as the amplitude of the voltage ripple becoming larger even with the same capacitor capacity, and a large filter being required to remove it. For this reason, priority is given to means that generate a higher ripple frequency.

Possible balance disturbances large enough to require the application of this embodiment 4 include abnormalities in the transformer or capacitor, discharge due to the intrusion of foreign matter into the cell, and cell insulation breakdown. Therefore, it is possible to integrate the DC component command values of the primary side AC current detection value i1k of the kth cell and the secondary side AC current detection value i2k of the kth cell, and periodically check these values during maintenance, etc. If a cell has a large integrated value, it can be assumed that deterioration or an abnormality has occurred in the other cells, and the cell with the smallest integrated value can be replaced to prevent a malfunction.

According to this fourth embodiment, even if a large balance disturbance occurs when the transmission power is zero, the voltage balance of the DC capacitors on both the primary and secondary sides can be maintained and operation can be continued.

In addition, ripples with a frequency equal to the fundamental frequency occur on the DC side, but this can be minimized.

The present invention can also be applied to a configuration such as that shown in Non-Patent Document 1, in which one end of multiple DAB converters are all connected in series, and the other end is a combination of series and parallel connections. In this case, the multiple DAB converters are considered to be connected in series as multiple unit cells, with one end connected in series and the other in parallel, and existing control methods are applied to series capacitor voltage balance control within the unit cells. The present invention is applied to capacitor voltage balance control for each unit cell.

[Embodiment 5]
The first to fourth embodiments are control methods for maintaining an equal capacitor voltage balance in multiple cells (DAB converters) connected in series at both ends. They are applicable regardless of the direction or magnitude of the transmitted power, and have the advantage of not requiring an auxiliary circuit.

However, this control method has problems such as an increase in the communication load between cells and the complexity of the wiring cables as the number of cells increases. This control method requires as input the primary and secondary DC capacitor voltage average values Vdc1avg and Vdc2avg, and the average energy Eavg stored in the primary and secondary DC capacitors C1 and C2. To calculate the primary and secondary DC capacitor voltage average values Vdc1avg and Vdc2avg and the average energy Eavg, the primary and secondary DC capacitor voltages of all other cells must be input to each cell.

Another option would be to prepare a separate means of calculating the average value, such as a host board. However, this host board would need to input the primary and secondary DC capacitor voltages of all cells. In addition, the average value output from the host board would need to be input to all cells.

Embodiment 3 of Non-Patent Document 1 discloses a control method for a power conversion device in which a single unit is made up of multiple DAB converters, one side of which is connected in series and the other side in parallel, and multiple such units are connected in series on both sides.

Because the series-parallel control within each unit and the series control of the units are independent, there is no need to know all of the DC voltages of each converter when controlling the units in series, which reduces the amount of wiring cables and communication information required. However, this method cannot be used in configurations where all converters are connected in series on both sides. Furthermore, a separate auxiliary circuit is required for series control of the units.

In this fifth embodiment, we describe a method for simplifying the wiring cables and reducing the amount of communication information in a control method for maintaining equal voltage balance in a configuration in which both sides of all cells (DAB converters) are connected in series.

Figure 11 shows a configuration in which y x z DAB converters are connected in series on both sides. This embodiment 5 is applied to the circuit in Figure 11. In Figure 11, one DAB converter is called a cell, and a collection of z cells, which are constituent elements, is called a unit. Furthermore, a collection of y units, which are constituent elements, makes up one device.

In other words, the DAB bidirectional isolated DC/DC converter of this fifth embodiment comprises a primary-side DC power supply DC1, a secondary-side DC power supply DC2, and a first unit to a y-th unit (y = an integer greater than or equal to 2) connected between the primary-side DC power supply DC1 and the secondary-side DC power supply DC. The first unit to the y-th unit each have a first cell to a z-th cell (z = an integer greater than or equal to 2), respectively.

In Figure 11, DCP is the primary DC power supply, DCS is the secondary DC power supply, Cp is the primary DC capacitor, Cs is the secondary DC capacitor, Vdcp is the primary DC voltage of the primary DC power supply DCP, and Vdcs is the secondary DC voltage of the secondary DC power supply DCS. Also, 11 is the first unit, 12 is the second unit, and 1y is the yth unit. Furthermore, 111 is the first cell of the first unit, 112 is the second cell of the first unit, 11z is the zth cell of the first unit, 121 is the first cell of the second unit, 12z is the zth cell of the second unit, 1y1 is the first cell of the yth unit, and 1yz is the zth cell of the yth unit.

Vdcp111 is the primary side DC capacitor voltage, Vdcs111 is the secondary side DC capacitor voltage, ip111 is the primary side AC current detection value, and is111 is the secondary side AC current detection value. The three-digit alphanumeric character at the end of each symbol indicates the cell number, and the two-digit alphanumeric character indicates the unit number. For example, Vdcp111 indicates the primary side DC capacitor voltage of the first cell of the first unit, and Vdcp11 indicates the primary side DC capacitor voltage of the first unit (the sum of the primary side DC capacitor voltages of the first cell to the zth cell of the first unit).

Figures 12 to 15 show the control unit of this fifth embodiment. Figure 12 is a block diagram of the phase difference command value (θ1jk) calculation unit for the kth (k = integer from 1 to z) cell of the jth (j = integer from 1 to y) unit. Figure 12 corresponds to embodiment 1 (Figure 2) and embodiment 2 (Figure 8). Figure 12 is composed of the following:

E1jk is the energy stored in both the primary and secondary DC capacitors Cp and Cs of the kth cell of the jth unit. Energy E1jk is calculated as follows (not shown):

An LPF is applied to the primary-side DC capacitor voltage Vdcp1jk and secondary-side DC capacitor voltage Vdcs1jk of the kth cell of the jth unit, the results are squared, multiplied by the primary-side and secondary-side DC capacitor capacitances Cp and Cs, respectively, and the results divided by 2 are added together. That is, E1jk = Cp × Vdcp1jk ² /2 + Cs × Vdcs1jk ² /2.

E1javg is the average value of the energy stored in both the primary and secondary DC capacitors Cp and Cs of each cell in the jth unit.

The thirteenth subtractor 40 calculates the first energy deviation, which is the deviation between the energy E1jk and the average energy value E1javg. The fourth amplifier 41 amplifies the output of the thirteenth subtractor 40 by multiplying it by a gain G2. The gain G2 may be a fixed value, or it may be varied based on the power command value P*, such as by reducing it when the power command value P* is near zero, as shown by the gain adjuster 42. The output of the fourth amplifier 41 becomes the unbalanced voltage command value Vdc1jk for the DC capacitor voltage of the kth cell of the jth unit.

Vdcp1jk is the primary side DC capacitor voltage of the kth cell of the jth unit. The low-pass filter LPF1 removes ripples and noise with a frequency twice that of the fundamental wave from the primary side DC capacitor voltage Vdcp1jk of the kth cell of the jth unit.

Vdcp1javg is the average primary DC capacitor voltage of each cell of the jth unit. The average primary DC capacitor voltage Vdcp1javg of each cell of the jth unit is either the sum of the primary DC capacitor voltages Vdcp1j1 to Vdcp1jz of each cell of the jth unit or the primary DC capacitor voltage Vdcp1j of the jth unit divided by the number z of cells in one unit.

The first subtractor 1 calculates the deviation between the primary DC capacitor voltage Vdcp1jk of the kth cell of the jth unit and the average primary DC capacitor voltage Vdcp1javg of each cell of the jth unit, and then adds the unbalanced voltage command value Vdc1jk for the DC capacitor voltage of the kth cell of the jth unit to the deviation to output the primary voltage deviation of the kth cell of the jth unit. The primary voltage deviation of the kth cell of the jth unit is input to the upper terminal of the first switch SW1.

Vdcs1jk is the secondary-side DC capacitor voltage of the kth cell of the jth unit. The second low-pass filter LPF2 removes ripple and noise at twice the frequency of the fundamental wave from the secondary-side DC capacitor voltage Vdcs1jk of the kth cell of the jth unit.

Vdcs1javg is the average secondary DC capacitor voltage of each cell of the jth unit. The average secondary DC capacitor voltage Vdcs1javg of each cell of the jth unit is either the sum of the secondary DC capacitor voltages Vdcs1j1 to Vdcs1jz of each cell of the jth unit or the secondary DC capacitor voltage Vdcs1j of the jth unit divided by the number z of cells in one unit.

The second subtractor 2 calculates the deviation between the secondary DC capacitor voltage Vdcs1jk of the kth cell of the jth unit and the average secondary DC capacitor voltage Vdcs1javg of each cell of the jth unit, and then adds the unbalanced voltage command value Vdc1jk for the DC capacitor voltage of the kth cell of the jth unit to the deviation to output the secondary voltage deviation of the kth cell of the jth unit.

The first turns ratio calculator 4 multiplies the output of the second subtractor 2 by the reciprocal of the transformer turns ratio, 1/n, and inverts the sign. The output of the first turns ratio calculator 4 is input to the lower terminal of the first switch SW1.

The first comparator 3 determines whether the power command value P* is positive. The first switch SW1 outputs the input to its upper terminal if the power command value P* is positive, and outputs the input to its lower terminal if the power command value P* is zero or negative.

To prevent frequent switching of the first switch SW1, if the power command value P* is near zero, the previous state of the first switch SW1 may be maintained to provide hysteresis characteristics. Furthermore, if the power command value P* is zero, the average value of the primary voltage deviation of the kth cell of the jth unit and the secondary voltage deviation of the kth cell of the jth unit may be output.

The eighth adder 43 adds the jth unit voltage control deviation Vd1j (described later) to the output of the first switch SW1.

The first amplifier 5 amplifies the output of the eighth adder 43 and outputs the phase θ1jkb of the kth cell of the jth unit. In this example, the following two amplifiers are used in combination: The proportional amplifier P1 outputs a value proportional to the output of the eighth adder 43. The first-order lag filter with gain 5a amplifies the low-frequency components of the output of the eighth adder 43. The first adder 6 adds the outputs of these two amplifiers and outputs the phase θ1jkb.

The second adder 7 adds a separately provided phase command value θ* to the phase θ1jkb and outputs a phase difference command value θ1jk for the kth cell of the jth unit. The phase command value θ* may also be provided by feedback control of the DC current or voltage.

Here, when the phase θ1jkb, phase command value θ*, and phase difference command value θ1jk are positive, the phase of the primary AC voltage leads the phase of the secondary AC voltage, and power is transmitted from the primary side to the secondary side.

Figure 12 of this embodiment 5 differs from embodiment 1 in the following respects. The average primary side DC capacitor voltage Vdcp1javg of each cell of the jth unit and the average secondary side DC capacitor voltage Vdcs1javg of each cell of the jth unit are not average values for all y × z cells, but are average values for z cells belonging to the jth unit. Similarly, the average energy E1javg is also an average value for z cells belonging to the jth unit.

The jth unit voltage control deviation Vd1j (described later) is added to the output of the first switch SW1 and input to the first amplifier 5.

Figure 13 is a block diagram of the jth unit voltage control deviation (Vd1j) calculation unit. Figure 13 has the same configuration as Figure 12 up to the input of the first amplifier 5, with only the input signal differing as shown in Table 1 below.

In Figure 13, 40a represents the 14th subtractor, 1a represents the 15th subtractor, 2a represents the 16th subtractor, 41a represents the 5th amplifier, 4a represents the second turns ratio calculator, 3a represents the third comparator, SW1a represents the sixth switch, and 43a represents the 9th adder. The output of the 14th calculator 40a is the third energy deviation.

The difference in configuration is that the first amplifier 5, which outputs phase θ1jkb, is removed.

The eighth multiplier 44, instead of the first amplifier 5, multiplies the reciprocal of the number of cells constituting one unit, 1/z, and inputs the resulting value as the jth unit voltage control deviation Vd1j in Figure 12.

Figure 14 shows a block diagram of the calculation unit for the pulse width command values (Wp1jkp, Wp1jkm, Ws1jkp, Ws1jkm) of the kth cell of the jth unit. Figure 14 corresponds to embodiment 4 (Figure 9).

The differences from embodiment 4 (Figure 9) are as follows: the primary pulse width command value W1k of the kth cell is the primary pulse width command value Wp1jk of the kth cell of the jth unit; the secondary pulse width command value W2k of the kth cell is the secondary pulse width command value Ws1jk of the kth cell of the jth unit; the energy Ek stored in the primary DC capacitor and secondary DC capacitor of the kth cell is the energy E1jk stored in both the primary and secondary DC capacitors Cp, Cs of the kth cell of the jth unit; the minimum value Emin of the energy of each cell is the minimum value E1jmin of the energy of each cell of the jth unit; the primary AC current detection value i1k of the kth cell is the primary AC current detection value ip1jk of the kth cell of the jth unit; The AC current detection value i2k has been changed to the secondary AC current detection value is1jk of the kth cell of the jth unit, the positive side pulse width command value W1kp of the primary side of the kth cell has been changed to the positive side pulse width command value Wp1jkp of the primary side of the kth cell of the jth unit, the negative side pulse width command value W1km of the primary side of the kth cell has been changed to the negative side pulse width command value Wp1jkm of the primary side of the kth cell of the jth unit, the positive side pulse width command value W2kp of the secondary side of the kth cell of the jth unit has been changed to the positive side pulse width command value Ws1jkp of the secondary side of the kth cell of the jth unit, and the negative side pulse width command value W2km of the secondary side of the kth cell has been changed to the negative side pulse width command value Ws1jkm of the secondary side of the kth cell of the jth unit.

Furthermore, the tenth adder 45 adds the jth unit energy deviation Ed1j (described later) to the second energy deviation output by the ninth subtractor 31.

Figure 14 differs from embodiments 1 to 4 in the following ways:

The minimum energy value E1jmin is the smallest value among the energies E1j1, E1j2, ..., E1jz of the cells belonging to the jth unit.

The tenth adder 45 adds the jth unit energy deviation Ed1j (described later) to the deviation between the energy E1jk and the minimum value E1jmin, and inputs the result to the third amplifier 32.

Figure 15 is a block diagram of the jth unit energy deviation (Ed1j) calculation unit. Figure 15 consists of the following:

E1j is the total energy of all z cells belonging to the jth unit. E1min is the minimum value of the energy of y units. The 17th subtractor 46 calculates the deviation between the total energy E1j and the minimum value E1min.

The eleventh adder 47 adds the energy deviation Ed1 of the first device to the output of the seventeenth subtractor 46. However, in this fifth embodiment, Ed1 = 0. The ninth multiplier 48 multiplies the output of the eleventh adder 47 by the reciprocal of the number z of cells constituting the unit. The output of the ninth multiplier 48 is the jth unit energy deviation Ed1j.

In this fifth embodiment, the phase difference between the AC voltages output by the first inverter and second inverter of each component is controlled so that the DC capacitor voltages upstream of the power transmission of each component in each assembly are equal within the assembly.

In other words, the phase difference between the AC voltages output by the first and second inverters of each cell is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each cell in each unit are equal within the unit, and the phase difference between the AC voltages output by the first and second inverters of each unit is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each unit are equal.

In embodiment 5, a total of z cells, cells 111 to 11z, are collectively regarded as unit 11, and control is performed by regarding these units as y units connected in series. The voltage balance control of each cell within the unit is shown in Figures 12 and 14, and the operation is the same as in embodiments 1 to 4.

In Figure 12, when power flows from the primary side to the secondary side, the DC voltage of the primary side cells is kept uniform, performing the same operation as in embodiment 1. Also, in Figure 12, when power flows from the primary side to the secondary side, the primary side DC voltage of cells with low energy is increased, allowing them to receive more power. This is the same operation as in embodiment 2.

Figure 14 shows how the power factor on the AC side is reduced in high-energy cells (embodiment 3), a DC component is superimposed on the AC current (embodiment 4), and losses are intentionally increased to promote the discharge of the DC voltage.

As the difference, the jth unit voltage control deviation Vd1j can be input in Figure 12, and the jth unit energy deviation Ed1j can be input in Figure 14. The output result of the unit's voltage balance control is input here.

The voltage balance control of the unit is shown in Figures 13 and 15, and is also the same as in embodiments 1 to 4.

In Figure 13, the primary side DC capacitor voltage Vdcp1j and secondary side DC capacitor voltage Vdcs1j of the jth unit to be controlled are compared with the primary side and secondary side DC capacitor voltage average values Vdcp1avg and Vdcs1avg of each of the y units, and the appropriate deviation from the primary side or secondary side is output depending on the direction of the power command value P* (interchangeable power), and distributed to each cell as the voltage control deviation Vd1j of the jth unit.

The jth unit voltage control deviation Vd1j is added to the deviation in Figure 12 (output of the first switch SW1) and then amplified by the first amplifier 5. The control block in Figure 13 evens out the unit voltage balance on the side aligned with the direction of the power command value P* (interchangeable power), and for units with low energy, the unit DC voltage on the side receiving power increases. Since the jth unit voltage control deviation Vd1j is input to the zth cell of the jth unit, it is multiplied by 1/z in advance to prevent the manipulated variable from becoming excessive.

Figure 15 shows a control block that balances the unit DC voltage by performing discharge operations under light load or no load conditions. In units with large energy, the energy deviation Ed1j of the jth unit becomes large, is output as shown in Figure 14, is amplified by the third amplifier 32, and increases loss in the zth cell of the jth unit.

Cell voltage balance control within a unit is implemented using the controls shown in Figures 12 and 14. The information required for cell voltage balance control is limited to the DC voltage and energy of the cells within the same unit (energy can be calculated from the DC voltage), and control can be performed without inputting information about other units.

The unit voltage balance control is equipped with the blocks shown in Figures 13 and 15. This control can be performed using information on the DC voltage and total stored energy value of each unit, and does not require information on each cell. The signals passed from the cell voltage balance control to the unit voltage balance control are Vdcp1javg x z = Vdcp1j, Vdcs1javg x z = Vdcs1j, E1javg x z = E1j (3 signals x y units = 3y signals). The unit voltage balance control outputs Vd1j and Ed1j (2 signals x y units = 2y signals).

As a method for reducing the number of signals passed from the cell voltage balance control to the unit voltage balance control, instead of communicating the energy E1j of the jth unit, it is possible to assume that the average cell DC capacitor voltages Vdcp1javg and Vdcs1javg of each unit are applied to the primary and secondary DC capacitors Cp and Cs in each cell and calculate this as (Cp × Vdcp1javg ² /2 + Cs × Vdcs1javg ² /2) × z. This eliminates the need to communicate the energy E1j of the jth unit, but since an error occurs in the unit stored energy, one possible method for preventing instability is to set the gain G2 in Figure 13 to a smaller value than that in Figure 12.

Embodiment 5 allows for two-stage hierarchical control in a series-connected DAB converter configuration, reducing the amount of wiring and communication information required between cells for control. Furthermore, the control blocks before the first switch SW1 and sixth switch SW1a in Figures 12 and 13 have the same configuration, and the control unit in Figure 15 is small in scale and does not include adjustment elements such as gain. Therefore, the same control design can be used to control the voltage balance of both cells and units.

If the board on which the control unit is mounted is equipped with input/output functions for the jth unit voltage control deviation Vd1j, the jth unit energy deviation Ed1j, the jth unit primary side DC capacitor voltage average value Vdcp1javg, the jth unit secondary side DC capacitor voltage average value Vdcs1javg, and the energy average value E1javg, it will be possible to control the voltage balance of both cells and units on the same board. For example, if one board is equipped with control functions for four cells, using five boards will allow for series operation of 16 units.

As described above, according to this fifth embodiment, the series connection configuration of DAB converters can be considered as a "series connection configuration of units in which DAB converter cells are connected in series," allowing for a two-stage hierarchy of control, simplifying the wiring between converters and reducing the amount of communication information. Because the series control of cells and units is the same, control design is simplified and it becomes possible to flexibly accommodate an increase in the number of series.

[Embodiment 6]
16 shows a configuration in which a group of z cells, which are the components connected in series as shown in FIG. 11, is a unit, a group of y components, which are units, is a device, and a group of x components, which are devices, is a higher-level device. This embodiment 6 is applied to the circuit of FIG.

In other words, the DAB-type bidirectional isolated DC/DC converter of this sixth embodiment comprises a primary-side DC power supply DCP, a secondary-side DC power supply DCS, and first to xth devices (x = an integer greater than or equal to 2) connected between the primary-side DC power supply DCP and the secondary-side DC power supply DCS. The first to xth devices comprise a first to yth unit, respectively. The first to yth units have a first to zth cell, respectively.

In addition, the single-digit alphanumeric character at the end of each reference symbol in this embodiment 6 indicates the device number. For example, Vdcp1 indicates the primary-side DC capacitor voltage of the first device.

In this sixth embodiment, the phase difference between the AC voltages output by the first inverter and second inverter of each cell is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each cell in each unit are equal within the unit. Furthermore, the phase difference between the AC voltages output by the first inverter and second inverter of each unit is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each unit in each device are equal within the device. Furthermore, the phase difference between the AC voltages output by the first inverter and second inverter of each device is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each device are equal.

In this sixth embodiment, the control units in Figures 12 and 14 can be used as they are as the control unit for the kth cell 1jk of the jth unit of the first device. The control units in Figures 13 and 15 can also be used as the control unit for the jth unit of the first device. However, in this sixth embodiment, values are substituted for the first device voltage control deviation Vd1 and the first device energy deviation Ed1, which were set to zero in the fifth embodiment.

Figure 17 is a block diagram of the i-th (i = integer from 1 to x) device voltage control deviation (Vdi) calculation unit. Figure 17 and Figure 13 have the same configuration, but the input signals are different, and the differences are explained below.

The output signal is also different; in Figure 13, it is input to Figure 12 as the jth unit voltage control deviation Vd1j. In Figure 17, it becomes the ith device voltage control deviation command Vdi, which is input to Figure 13 when i = 1. If i is a different value, it becomes the voltage control deviation of the corresponding device.

In Figure 17, 40b represents the 18th subtractor, 41b represents the 6th amplifier, 42b represents the gain adjuster, 1b represents the 19th subtractor, 2b represents the 20th subtractor, 4b represents the 3rd turns ratio calculator, 3b represents the 4th comparator, SW1b represents the 7th switch, 43b represents the 10th adder, and 44b represents the 10th multiplier. The output of the 18th subtractor 40b is the 4th energy deviation.

Figure 18 is a block diagram of the i-th device energy deviation (Edi) calculation unit. The differences between Figure 18 and Figure 15 are shown below.

The output signal is also different; in Figure 15, it is input to Figure 14 as the jth unit energy deviation Ed1j. In Figure 18, it is the ith device energy deviation Edi, which is input to Figure 15 when i = 1. If i is a different value, it becomes the energy deviation of the corresponding device.

As described above, according to this sixth embodiment, the control of the series-connected configuration of DAB converters can be hierarchically structured into three levels, further simplifying the wiring between converters and reducing the amount of information communicated. A hierarchy of four or more levels can also be achieved, allowing for an increase in the number of series-connected units.

In embodiment 6, control is performed assuming that x more devices of embodiment 5 are connected in series. Device voltage balance control is also the same as in embodiments 1 to 4. Embodiment 6 is an example of control hierarchized into three stages. Cell voltage balance control can be performed without inputting information about other units or devices, and device voltage balance control does not require information about individual units or cells.

As a result, the amount of wiring and communication information required for control between cells can be further reduced compared to embodiment 5. In an example where one board is configured to have control functions for four cells, using 21 boards can support series operation of 64 units.

In embodiment 6, 0 is added in Figures 17 and 18, but by replacing this 0 with a higher voltage deviation, further hierarchical structures can be achieved. As long as communication delays do not affect control stability, deeper hierarchical structures can be created and the number of series-connected cells can be increased.

The present invention has been described in detail above, only with reference to the specific examples. However, it will be obvious to those skilled in the art that numerous variations and modifications are possible within the scope of the technical concept of the present invention, and it is natural that such variations and modifications fall within the scope of the claims.

DCP, DCS...Primary side DC power supply, Secondary side DC power supply Cp, Cs...Primary side DC capacitor, Secondary side DC capacitor L1 to L4...Reactor Tr...Transformer LPF1 to LPF4...1st to 4th low pass filters

Claims (13)

A DAB bidirectional isolated DC/DC converter including a primary side DC power supply, a secondary side DC power supply, and a plurality of cells connected between the primary side DC power supply and the secondary side DC power supply,
a primary DC capacitor for each cell connected in series between the positive and negative electrodes of the primary DC power supply;
a secondary DC capacitor for each cell connected in series between the positive and negative electrodes of the secondary DC power supply;
a first inverter for each cell connected to the primary side DC capacitor of each cell;
a second inverter for each cell connected to the secondary-side DC capacitor of each cell;
a transformer for each cell, the primary winding of which is connected to the AC side of the first inverter of each cell, and the secondary winding of which is connected to the AC side of the second inverter of each cell;
a control unit that generates gate signals for the first and second inverters;
Equipped with
The system is hierarchically structured into first to nth stages (n = an integer of 2 or more), with the first stage being the cell and the second stage being a unit that is an aggregate of a predetermined number of the cells that are components ,
The control unit
A DAB type bidirectional isolated DC/DC converter characterized in that at least one of the phase difference or pulse width of the AC voltage output from the first inverter and the second inverter of each component is controlled so that the DC capacitor voltages upstream of the power transmission of each component in each assembly are equal within the assembly. The control unit
When the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component is larger than that of other components in the assembly, the phase difference between the AC voltages output by the first inverter and the second inverter of the specific component is controlled so that the DC capacitor voltage on the upstream side of the power transmission of the specific component becomes smaller;
2. The DAB bidirectional isolated DC/DC converter according to claim 1, wherein when the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component is smaller than that of other components within the assembly, the phase difference between the AC voltages output by the first inverter and the second inverter of the specific component is controlled so that the DC capacitor voltage on the upstream side of the power transmission of the specific component becomes larger. The control unit
3. The DAB bidirectional isolated DC/DC converter according to claim 1, wherein the energy stored in the primary side DC capacitor and the secondary side DC capacitor is a component other than the smallest among all components, and the operating power factor of the component is reduced. The control unit
The DAB bidirectional isolated DC/DC converter according to any one of claims 1 to 3, characterized in that the energy stored in the primary side DC capacitor and the secondary side DC capacitor is a component other than the smallest among all components, and the DC component of the current output by the component is increased. The third level of the hierarchy is a device that is an assembly of a predetermined number of the above-mentioned units, which are components,
The control unit
a thirteenth subtractor that calculates a first energy deviation, which is a deviation between the energy stored in the primary side DC capacitor and the secondary side DC capacitor of the kth (k is an integer from 1 to y) cell of the jth (j=an integer from 1 to z) unit and the average value of the energy stored in the primary side DC capacitor and the secondary side DC capacitor of the cell of the jth unit;
a fourth amplifier that amplifies the first energy deviation and outputs an unbalanced voltage command value for the k-th cell of the j-th unit;
a first subtractor that subtracts a primary DC capacitor voltage average value of the cells of the j unit from the sum of the primary DC capacitor voltage of the kth cell of the j unit and the unbalance voltage command value of the kth cell of the j unit, to calculate a primary voltage deviation of the kth cell of the j unit;
a second subtractor that subtracts an average value of the secondary DC capacitor voltage of the cell of the j unit from the sum of the secondary DC capacitor voltage of the kth cell of the j unit and the unbalance voltage command value of the kth cell of the j unit, and calculates a secondary voltage deviation of the kth cell of the j unit;
a first turns ratio multiplier that multiplies the secondary voltage deviation of the kth cell of the jth unit by −1/n when the turns ratio of the transformer is primary winding:secondary winding=1:n, or multiplies the secondary voltage deviation of the kth cell of the jth unit by −1 and multiplies the primary voltage deviation of the kth cell of the jth unit by n;
a first switch that outputs a primary voltage deviation of the kth cell of the y unit when a power command value is greater than a first threshold, that outputs a secondary voltage deviation of the kth cell of the y unit when the power command value is less than a second threshold, and that outputs either the primary voltage deviation of the kth cell of the y unit or the secondary voltage deviation of the kth cell of the y unit, or the sum of both, or 0, when the power command value is equal to or greater than the second threshold and less than the first threshold;
an eighth adder that adds a j-th unit voltage control deviation to the output of the first switch;
a first amplifier that amplifies the output of the eighth adder and outputs the amplified output as the phase of the kth cell of the jth unit;
a second adder that adds a phase command value to the phase of the kth cell of the jth unit and outputs the result as a phase difference command value of the kth cell of the jth unit;
and controlling the first inverter and the second inverter of the kth cell of the jth unit based on the phase difference command value. The fourth and subsequent levels of the hierarchy are higher-level devices that are aggregates of a predetermined number of the above-mentioned devices that are components,
The control unit
a fourteenth subtractor that calculates a third energy deviation, which is the deviation between the energy stored in the primary DC capacitor and the secondary DC capacitor of the jth unit and the average value of the energy stored in the primary DC capacitor and the secondary DC capacitor of the unit;
a fifth amplifier that amplifies the third energy deviation and outputs an unbalance voltage command value for the j-th unit;
a fifteenth subtractor that subtracts an average primary DC capacitor voltage value of the unit from the sum of the primary DC capacitor voltage of the jth unit and the unbalance voltage command value of the jth unit to calculate a primary voltage deviation of the jth unit;
a sixteenth subtractor that subtracts an average value of the secondary DC capacitor voltage of the j-th unit from the sum of the secondary DC capacitor voltage of the j-th unit and the unbalance voltage command value of the j-th unit to calculate a secondary voltage deviation of the j-th unit;
a second turns ratio multiplier that multiplies the secondary voltage deviation of the j unit by -1/n when the turns ratio of the transformer is primary winding:secondary winding=1:n, or multiplies the secondary voltage deviation of the j unit by -1 and multiplies the primary voltage deviation of the j unit by n;
a sixth switch that outputs a primary voltage deviation of the j unit when the power command value is greater than a first threshold, outputs a secondary voltage deviation of the j unit when the power command value is less than a second threshold, and outputs either the primary voltage deviation of the j unit or the secondary voltage deviation of the j unit, or the sum of both, or 0 when the power command value is equal to or greater than the second threshold and less than the first threshold;
a ninth adder that adds an i-th (i=an integer from 1 to x) device voltage control deviation to the output of the sixth switch;
an eighth multiplier that multiplies the output of the ninth adder by the reciprocal of the number of cells in the unit and outputs the result as the jth unit voltage control deviation;
6. The DAB bidirectional isolated DC/DC converter according to claim 5, further comprising: The third level of the hierarchy is a device that is an assembly of a predetermined number of the above-mentioned units, which are components,
a ninth subtractor that calculates a second energy deviation, which is a deviation between the energy stored in the primary DC capacitor and the secondary DC capacitor of the kth cell of the jth unit and the minimum value of the energy stored in the primary DC capacitor and the secondary DC capacitor of each cell of the jth unit;
a tenth adder that adds the j-th unit energy deviation to the second energy deviation;
a third amplifier that amplifies the output of the tenth adder;
a seventh adder that adds the output of the third amplifier to the smaller of a primary pulse width command value of the kth cell of the jth unit and a secondary pulse width command value of the kth cell of the jth unit;
a first limiter that limits the output of the seventh adder to within an upper limit value and a lower limit value;
a tenth subtractor that calculates a difference between an input value and an output value of the first limiter;
an eleventh subtractor that subtracts a difference between an input value and an output value of the first limiter from the larger of the primary pulse width command value of the kth cell of the jth unit and the secondary pulse width command value of the kth cell of the jth unit;
a second limiter that limits the output of the eleventh subtractor to an upper limit value and a lower limit value;
a twelfth subtractor that calculates a difference between an input value and an output value of the second limiter;
a fourth switch that outputs the output of the second limiter when the primary pulse width command value of the kth cell of the jth unit is greater than the secondary pulse width command value of the kth cell of the jth unit, and outputs the output of the first limiter otherwise;
a fifth switch that outputs the output of the first limiter when the primary pulse width command value of the kth cell of the jth unit is greater than the secondary pulse width command value of the kth cell of the jth unit, and outputs the output of the second limiter otherwise;
a first multiplier that multiplies the primary side AC current detection value of the kth cell of the jth unit by 1/n or multiplies the secondary side AC current detection value of the kth cell of the jth unit by n when the turns ratio of the transformer is primary winding:secondary winding=1:n;
a third subtractor that subtracts a DC component of the primary side AC current detection value of the kth cell of the jth unit from a difference between an input value and an output value of the second limiter;
a fourth subtractor that subtracts a DC component of the secondary-side AC current detection value of the kth cell of the jth unit from a value obtained by inverting the sign of a difference between an input value and an output value of the second limiter;
a third adder that adds a value obtained by amplifying the output of the third subtractor to the output of the fourth switch and outputs the result as a positive side pulse width command value on the primary side of the kth cell of the jth unit;
a fifth subtractor that subtracts a value obtained by amplifying the output of the third subtractor from the output of the fourth switch and outputs the result as a negative side pulse width command value on the primary side of the kth cell of the jth unit;
a fourth adder that adds a value obtained by amplifying the output of the fourth subtractor to the output of the fifth switch and outputs the result as a positive side pulse width command value on the secondary side of the kth cell of the jth unit;
a sixth subtractor that subtracts a value obtained by amplifying the output of the fourth subtractor from the output of the fifth switch and outputs the result as a negative side pulse width command value on the secondary side of the kth cell of the jth unit;
7. The DAB bidirectional isolated DC/DC converter according to claim 1, further comprising: The fourth and subsequent levels of the hierarchy are higher-level devices that are aggregates of a predetermined number of the above-mentioned devices that are components,
The control unit
a seventeenth subtractor that subtracts the minimum value of the energy stored in the primary DC capacitor and the secondary DC capacitor of each unit from the energy stored in the primary DC capacitor and the secondary DC capacitor of the j unit;
an eleventh adder that adds an i-th (i=an integer from 1 to x) device energy deviation to the output of the seventeenth subtractor;
a ninth multiplier that multiplies the output of the eleventh adder by the reciprocal of the number of cells in the unit and outputs the j-th unit energy deviation;
8. The DAB bidirectional isolated DC/DC converter according to claim 7, further comprising: The fourth and subsequent levels of the hierarchy are higher-level devices that are aggregates of a predetermined number of the above-mentioned devices that are components,
The control unit
an eighteenth subtractor that calculates a fourth energy deviation, which is the deviation between the energy stored in the primary side DC capacitor and the secondary side DC capacitor of the i-th device (i=an integer from 1 to x) and the average value of the energy stored in the primary side DC capacitor and the secondary side DC capacitor of the device;
a sixth amplifier that amplifies the fourth energy deviation and outputs an unbalance voltage command value of the i-th device;
a nineteenth subtractor that subtracts an average value of the primary side DC capacitor voltage of the i-th device from the sum of the primary side DC capacitor voltage of the i-th device and the unbalance voltage command value of the i-th device to calculate a primary side voltage deviation of the i-th device;
a twentieth subtractor that subtracts an average value of the secondary DC capacitor voltage of the i-th device from the sum of the secondary DC capacitor voltage of the i-th device and the unbalance voltage command value of the i-th device to calculate a secondary voltage deviation of the i-th device;
a third turns ratio multiplier that multiplies the secondary voltage deviation of the i-th device by -1/n when the turns ratio of the transformer is primary winding:secondary winding=1:n, or multiplies the secondary voltage deviation of the i-th device by -1 and multiplies the primary voltage deviation of the i-th device by n;
a seventh switch that outputs a primary voltage deviation of the i-th device when the power command value is greater than a first threshold, outputs a secondary voltage deviation of the i-th device when the power command value is less than a second threshold, and outputs either the primary voltage deviation of the i-th device or the secondary voltage deviation of the i-th device, or the sum of both, or 0, when the power command value is equal to or greater than the second threshold and less than the first threshold;
a tenth multiplier that multiplies the output of the seventh switch by the reciprocal of the number of units of the device and outputs the result as the i-th device voltage control deviation;
7. The DAB bidirectional isolated DC/DC converter according to claim 6, further comprising: The control unit
a 21st subtractor that subtracts a minimum value of the energy stored in the primary DC capacitor and the secondary DC capacitor of each device from the energy stored in the primary DC capacitor and the secondary DC capacitor of the i-th device;
an 11th multiplier that multiplies the output of the 21st subtractor by the reciprocal of the number of units of the apparatus and outputs the i-th apparatus energy deviation;
9. The DAB bidirectional isolated DC/DC converter according to claim 8, further comprising: A collection of z (z = an integer of 2 or more) cells is defined as the unit, a collection of y (y = an integer of 2 or more) units is defined as the device, and one device is provided;
9. The DAB bidirectional isolated DC/DC converter according to any one of claims 1 to 8, characterized in that either a phase difference or a pulse width of the AC voltages output by the first inverter and the second inverter of each unit is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each cell in each unit are equal within the unit, and at least either a phase difference or a pulse width of the AC voltages output by the first inverter and the second inverter of each unit is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each unit are equal. A collection of z (z = an integer of 2 or more) of the cells is defined as the unit, a collection of y (y = an integer of 2 or more) of the units is defined as the device, a collection of x (x = an integer of 2 or more) of the devices is defined as a higher-level device, and the system has one higher-level device;
11. The DAB bidirectional isolated DC/DC converter according to claim 1, wherein at least one of a phase difference and a pulse width of the AC voltage output by the first inverter and the second inverter of each cell is controlled so that in each unit, the DC capacitor voltages on the upstream side of the power transmission of each cell are equal within the unit; at least one of a phase difference and a pulse width of the AC voltage output by the first inverter and the second inverter of each unit is controlled so that in each device, the DC capacitor voltages on the upstream side of the power transmission of each unit are equal within the device; and at least one of a phase difference and a pulse width of the AC voltage output by the first inverter and the second inverter of each device is controlled so that the DC capacitor voltages on the upstream side of the power transmission of each device are equal. a primary side DC power supply;
A secondary DC power supply;
a plurality of cells connected between the primary side DC power supply and the secondary side DC power supply,
a primary DC capacitor for each cell connected in series between the positive and negative electrodes of the primary DC power supply;
a secondary DC capacitor for each cell connected in series between the positive and negative electrodes of the secondary DC power supply;
a first inverter for each cell connected to the primary side DC capacitor of each cell;
a second inverter for each cell connected to the secondary-side DC capacitor of each cell;
a transformer for each cell, the primary winding of which is connected to the AC side of the first inverter of each cell, and the secondary winding of which is connected to the AC side of the second inverter of each cell;
a control unit that generates gate signals for the first and second inverters;
Equipped with
A control method for a DAB bidirectional isolated DC/DC converter, which is hierarchically divided into 1st to nth stages (n=2 or more integer), the 1st stage being a cell, and the 2nd stage being a unit which is an aggregate of a predetermined number of the cells which are components,
The control unit
A control method for a DAB type bidirectional isolated DC/DC converter, characterized in that at least one of the phase difference or pulse width of the AC voltage output from the first inverter and the second inverter of each component is controlled so that the DC capacitor voltages upstream of the power transmission of each component in each assembly are equal within the assembly.