JP7796572B2 - Semiconductor device manufacturing method and visual inspection device for semiconductor device - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device manufacturing method and a visual inspection device for semiconductor devices.

During the manufacturing process of semiconductor devices, defects such as foreign matter may form on the surface of the semiconductor device. Patent Document 1 discloses an example of an appearance inspection device for detecting such defects.

JP 2014-190821 A

Defects formed on the surface of a semiconductor device affect the electrical characteristics of the semiconductor device. The magnitude of the effect on the electrical characteristics of the semiconductor device is thought to depend on the relative position of the defect with respect to the internal structure of the semiconductor device. Conventional technology can extract feature quantities such as the shape of defects formed on the surface of a semiconductor device, but cannot extract feature quantities related to the relative position of the defect with respect to the internal structure of the semiconductor device. This specification provides technology that can extract feature quantities related to the relative position of the defect with respect to the internal structure of a semiconductor device.

This specification provides a method for manufacturing a semiconductor device having an electrode covering one of its principal surfaces. This semiconductor device manufacturing method can include a forming step of forming a reference mark in a scribe line corresponding to the position of the internal structure of the semiconductor device, an acquisition step of acquiring an image of the electrode of the semiconductor device, and an extraction step of extracting a feature of a defect present in the image. In the extraction step, the feature related to the relative position of the defect with respect to the internal structure of the semiconductor device is extracted based on the reference mark. The reference mark may be a reference trench corresponding to the positions of multiple trench gates provided in the semiconductor device. The reference trench may also include identification information indicating the absolute position of the trench gate within the semiconductor device. In this semiconductor device manufacturing method, the reference mark corresponding to the position of the internal structure of the semiconductor device is formed in the forming step in the scribe line. Therefore, in the extraction step, the feature related to the relative position of the defect with respect to the internal structure of the semiconductor device can be extracted by referring to the reference mark.

This specification provides an appearance inspection device for inspecting the appearance of a semiconductor device having an electrode covering one of its main surfaces. The appearance inspection device may include an image acquisition device that acquires an image of the electrode of the semiconductor device, and a processing device that extracts feature quantities of defects present in the image. A reference mark corresponding to the position of the internal structure of the semiconductor device is formed in a scribe line of the semiconductor device. The reference mark may be a reference trench corresponding to the positions of multiple trench gates provided in the semiconductor device. The reference trench may also include identification information indicating the absolute position of the trench gate within the semiconductor device. The processing device is configured to execute a process that extracts the feature quantities related to the relative position of the defect with respect to the internal structure of the semiconductor device based on the reference mark. This appearance inspection device can extract the feature quantities related to the relative position of the defect with respect to the internal structure of the semiconductor device by referencing the reference mark formed in the scribe line of the semiconductor device.

1 is a diagram showing a schematic configuration of a visual inspection apparatus according to an embodiment of the present invention; FIG. 2 is a diagram schematically showing a plan view of a device wafer. FIG. 2 is a diagram schematically showing a plan view of the semiconductor device, in which the positions of a plurality of trench gates, which are an internal structure of the semiconductor device, are overlapped. FIG. 1 is a schematic enlarged cross-sectional view of a main part of a semiconductor device. FIG. 2 is a diagram schematically showing a plan view of a reference trench. FIG. 2 is a diagram showing a flow of processing executed by the visual inspection apparatus according to the present embodiment. 10A and 10B are diagrams for explaining processing executed by the visual inspection apparatus according to the present embodiment, in which an image of a defect is extracted from an acquired enlarged image. 10A and 10B are diagrams for explaining a process executed by the visual inspection apparatus according to the present embodiment, which extracts a feature amount of a defect.

As shown in FIG. 1, the visual inspection device 10 includes a stage 12, an image acquisition device 14, and a processing device 16. The visual inspection device 10 is configured to detect defects such as foreign matter formed on the surface of a device wafer 2 placed on the stage 12.

The image acquisition device 14 is not particularly limited, but may be, for example, a camera. The image acquisition device 14 is positioned above the stage 12 and is configured to acquire images of the surface of the device wafer 2 while scanning the surface of the device wafer 2.

The processing device 16 is communicatively connected to the image acquisition device 14 and is configured to input images acquired by the image acquisition device 14. The processing device 16 is configured as a computer and includes a CPU, memory, etc. The processing device 16 is configured to execute various processes described below by running programs stored in the memory on the CPU.

Figure 2 shows a plan view of the device wafer 2. Multiple semiconductor devices 20 (also called "chips" or "dies") are formed on the device wafer 2. Each of the multiple semiconductor devices 20 is formed in an area defined by dicing lines 30 that are parallel to the main surface of the device wafer 2 and extend in two mutually orthogonal directions (in this example, the x and y directions). For the purpose of clarity, only some of the repeating structures are labeled with reference numerals. This also applies to other drawings.

Figure 3 shows an enlarged view of semiconductor device 20. Semiconductor device 20 is not particularly limited, but may be, for example, a vertical power device in which current flows between a pair of main surfaces (between the bottom and top surfaces). Semiconductor device 20 may also be, for example, a field-effect transistor, specifically a MOSFET (Metal Oxide Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor).

The semiconductor device 20 has multiple trench gates 22 formed therein. When viewed from a direction perpendicular to the top surface of the semiconductor device 20 (hereinafter referred to as "when viewed in a plan view"), each of the multiple trench gates 22 extends in one direction (the x direction in this example). When viewed in a plan view, each of the multiple trench gates 22 is positioned at a predetermined distance from adjacent trench gates 22 in the y direction. As such, the multiple trench gates 22 have a striped layout when viewed in a plan view. Note that while Figure 3 illustrates multiple trench gates 22, in the actual semiconductor device 20, an electrode is formed in the area surrounded by dashed lines 24 so as to cover the top surface of the semiconductor device 20. For this reason, the positions of the multiple trench gates 22 cannot be determined when the semiconductor device 20 is covered with the electrode 24.

4 shows an enlarged cross-sectional view of a key portion of the active region of the semiconductor device 20 (a region through which current flows and in which multiple trench gates 22 are disposed). The semiconductor device 20 includes a semiconductor layer 26 made of, but not limited to, silicon, silicon carbide, or gallium nitride. Multiple trench gates 22 are formed on the upper surface of the semiconductor layer 26. The semiconductor device 20 also includes an interlayer insulating film 28 formed to cover the upper surface of the semiconductor layer 26. Contact holes 29 are formed in the interlayer insulating film 28 at positions corresponding to the spaces between the trench gates 22. Thus, the interlayer insulating film 28 is selectively disposed above the trench gates 22 in the active region. An electrode 24 is formed to cover the upper surface of the interlayer insulating film 28. The electrode 24 contacts the upper surface of the semiconductor layer 26 through the contact holes 29. The electrode 24 is formed using vapor deposition after the interlayer insulating film 28 is formed. As a result, the surface of the electrode 24 has irregularities that reflect the shape of the interlayer insulating film 28.

Returning to Figure 3, a plurality of reference trenches 32 are formed in dicing lines 30 around the periphery of the semiconductor device 20. Each of the plurality of reference trenches 32 is positioned to correspond to the position of a corresponding trench gate 22. Specifically, each of the plurality of reference trenches 32 is positioned on a portion of the dicing line 30 that extends the corresponding trench gate 22 in its longitudinal direction (the x-direction in this example). In other words, each of the plurality of reference trenches 32 is positioned to coincide with the corresponding trench gate 22 in the x-direction. The plurality of reference trenches 32 are formed simultaneously during the etching process for forming the plurality of trench gates 22 in the process of manufacturing the semiconductor device 20. Therefore, the relative positional relationship between the plurality of reference trenches 32 and the plurality of trench gates 22 is accurately fixed. In this example, the reference trenches 32 are formed only in the dicing lines 30 extending in the y direction (dicing lines 30 located to the left and right of the semiconductor device 20 on the page), but multiple reference trenches 32 may also be formed in the dicing lines 30 extending in the x direction (dicing lines 30 located above and below the semiconductor device 20 on the page). The reference trenches 32 provided in the dicing lines 30 extending in the x direction are also formed simultaneously in the etching process for forming the multiple trench gates 22, thereby accurately fixing their relative positional relationship with the multiple trench gates 22.

Figure 5 shows an enlarged plan view of a reference trench 32. In this example, one reference trench 32 is composed of, for example, 14 split trench formation areas 34. In each of the 14 split trench formation areas 34, the presence of a split trench (shown by a solid line) corresponds to "1," and the absence of a split trench (shown by a dashed line) corresponds to "0." In this way, one reference trench 32 represents 14 bits and stores information about which trench gate 22 it corresponds to, counting in the y direction from the trench gate 22 at either end. In other words, the reference trench 32 contains identification information that represents the absolute position of the trench gate 22 within the semiconductor device 20. This example illustrates a reference trench 32 that corresponds to the 3555th trench gate 22 in decimal notation.

Next, the visual inspection process performed by the processing device 16 of the visual inspection device 10 will be described. Figure 6 shows a flowchart of the visual inspection process performed by the processing device 16. Note that this visual inspection process is performed prior to the process of dividing the device wafer 2 by dicing, which is one of the processes for manufacturing the semiconductor device 20.

First, in step S1, the processing device 16 inputs multiple images captured by the image acquisition device 14. Each of the multiple images is an image of a range corresponding to one semiconductor device 20.

Next, in step S2, the processing device 16 determines whether or not there is a defect on the surface of the semiconductor device 20. The processing device 16, for example, calculates the difference between the image to be inspected and a reference image that does not contain any defects, and determines that the image to be inspected has a defect if there is a difference, and determines that the image to be inspected does not have a defect if there is no difference. If there is no difference, the visual inspection of that semiconductor device 20 ends. If there is a difference, the process proceeds to step S3. The presence or absence of a defect may also be determined by calculating the difference between the images of adjacent semiconductor devices 20, and determining that a defect exists if there is a difference.

Next, in step S3, the processing device 16 registers the defect position information in memory. The defect position information is the coordinate information of the pixel in the image where a difference was found.

Next, in step S4, the processing device 16 acquires an enlarged image of the area near the defect based on the defect position information registered in memory. The enlarged image may be acquired by enlarging a portion of an already acquired image that includes the defect. Alternatively, the enlarged image may be acquired by driving a separate high-magnification camera included in the image acquisition device 14.

Next, in step S5, the processing device 16 extracts defect features using the enlarged image. This step has two steps. The first step is to extract an image of the defect from the enlarged image. The second step is to extract features related to the relative position of the defect with respect to the trench gate 22 of the semiconductor device 20, with reference to the reference trench 32.

Referring to Figure 7, the steps for extracting a defect image from an enlarged image are described. As described with reference to Figure 4, the surface of the electrode 24 of the semiconductor device 20 has irregularities that reflect the shape of the interlayer insulating film 28 covering the trench gate 22. These irregularities are low-frequency steady-state components among the spatial frequency components contained in the enlarged image. Therefore, the enlarged image is first Fourier transformed to generate a filtered enlarged image (Figure 7(A)) consisting of high-frequency components obtained by removing the low-frequency steady-state components caused by the irregularities and the ultra-high-frequency noise components using a band-pass filter. Next, the generated filtered enlarged image is binarized using a specific pixel value as a threshold (Figure 7(B)). In this example, components corresponding to pixel values higher than the specific pixel value are shown in white. This makes it possible to clearly identify components estimated to be defects in the filtered enlarged image. Next, the defect of interest is selected and extracted (Figure 7(C)). Through these steps, an image of the defect is extracted from the enlarged image.

Referring to Figure 8, the steps for extracting defect features are described. First, an image of the reference trench 32 located in the x direction of the enlarged image is acquired, and by referencing the image of the reference trench 32, a trench gate position image is generated that indicates the position of the trench gate 22 corresponding to the enlarged image (Figure 8(A)). Note that in this example, the white portion indicates the position of the trench gate 22. Because the generated trench gate position image is generated by referencing the image of the reference trench 32, it accurately represents the position of the trench gate 22 relative to the enlarged image and has clear edges. Next, a composite image is generated by superimposing the image of the previously extracted defect and an image indicating the position of the trench gate 22 (Figure 8(B)). This results in an image that accurately represents the relative position of the defect with respect to the trench gate 22 of the semiconductor device 20. Note that instead of such a composite image, a single image may be generated by performing an inverse Fourier transform on the frequency components of the image of the defect and the frequency components of the image indicating the position of the trench gate 22.

The processing device 16 extracts, from the generated composite image, feature quantities related to the relative position of the defect with respect to the trench gate 22 of the semiconductor device 20. For example, the processing device 16 can extract data on the area of the defect present between the trench gates 22 (i.e., directly above the contact hole 29 in the interlayer insulating film 28) from the generated composite image. A defect directly above the contact hole 29 strongly affects the on-resistance of the semiconductor device 20. Therefore, the processing device 16 can estimate the effect on the on-resistance of the semiconductor device 20 based on the area of the defect present directly above the contact hole 29 and determine whether the semiconductor device 20 is defective. Furthermore, the processing device 16 can extract data on which trench gate 22 in the semiconductor device 20 the defect is located near by referring to the identification information of the trench gate 22 (see Figure 5). Note that these feature quantities are merely examples. Because the processing device 16 can accurately determine the relative position of the defect with respect to the trench gate 22, it can accurately extract various feature quantities related to the relative position of the defect with respect to the trench gate 22.

As such, the above-described visual inspection process utilizes multiple reference trenches 32 formed on the dicing lines 30 of the device wafer 2. Because the multiple reference trenches 32 are formed on the dicing lines 30, they do not affect the electrical characteristics of the semiconductor device 20. Furthermore, because the multiple reference trenches 32 are formed simultaneously with the multiple trench gates 22, their relative positional relationship to the multiple trench gates 22 is accurately fixed. Therefore, by referencing the reference trenches 32, the above-described visual inspection process can generate an image that accurately indicates the position of the trench gates 22 corresponding to the enlarged image. Alternatively, for example, low-frequency steady-state components from the spatial frequency components contained in the enlarged image can be extracted to generate an image showing the uneven shape of the surface of the electrode 24, and this image can be treated as the position of the trench gates 22. However, images generated in this manner tend to contain a lot of noise and have unclear edges. On the other hand, by referencing the reference trenches 32, the image generated by the above-described visual inspection process accurately indicates the position of the trench gates 22 relative to the enlarged image and has clear edges. Therefore, the above-described visual inspection process can accurately extract features related to the relative position of the defect with respect to the trench gate 22. As a result, the above-described visual inspection process can accurately estimate, for example, the effect of the defect on the electrical characteristics of the semiconductor device 20.

In the above, the trench gate 22 is shown as an example of an internal structure of the semiconductor device 20. Alternatively, the reference trench 32 or a reference mark that performs a similar function may be formed corresponding to another internal structure of the semiconductor device 20 (e.g., a source region, etc.).

In the above example, when extracting an image of a defect from a magnified image, noise components were removed using frequency filtering techniques. Alternatively, other algorithms (e.g., machine learning models such as neural networks) may be used to remove noise components.

The above provides a detailed description of examples of the technology disclosed in this specification, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations set forth in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving any one of those objectives is itself technically useful.

1: Visual inspection device, 2: Device wafer, 10: Visual inspection device, 12: Stage, 14: Image acquisition device, 16: Processing device, 20: Semiconductor device, 22: Trench gate, 24: Electrode, 26: Semiconductor layer, 28: Interlayer insulating film, 29: Contact hole, 30: Dicing line, 32: Reference trench, 34: Dividing trench formation area

Claims (6)

A method for manufacturing a semiconductor device having one main surface covered with an electrode, comprising:
a forming step of forming a reference mark in a scribe line corresponding to a position of an internal structure of the semiconductor device;
acquiring an image of the electrode of the semiconductor device;
an extraction step of extracting a feature amount of a defect present in the image,
In the extracting step, the feature amount relating to the relative position of the defect with respect to the internal structure of the semiconductor device is extracted based on the reference mark. The method for manufacturing a semiconductor device according to claim 1, wherein the reference mark is a reference trench corresponding to the positions of multiple trench gates provided in the semiconductor device. The method for manufacturing a semiconductor device according to claim 2, wherein the reference trench includes identification information representing the absolute position of the trench gate within the semiconductor device. A visual inspection apparatus for inspecting the visual appearance of a semiconductor device having one main surface covered with an electrode,
an image acquisition device for acquiring an image of the electrode of the semiconductor device;
a processing device that extracts feature quantities of defects present in the image,
a reference mark corresponding to a position of an internal structure of the semiconductor device is formed on a scribe line of the semiconductor device;
The visual inspection apparatus, wherein the processing device is configured to execute a process of extracting the feature amount relating to a relative position of the defect with respect to the internal structure of the semiconductor device based on the reference mark. The visual inspection device of claim 4, wherein the reference mark is a reference trench corresponding to the positions of multiple trench gates provided in the semiconductor device. The visual inspection device of claim 5, wherein the reference trench includes identification information representing the absolute position of the trench gate within the semiconductor device.