JP7809274B2 - Manufacturing method of semiconductor laminate and semiconductor laminate - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor laminate and a semiconductor laminate.

Light-emitting and receiving elements with wavelengths in the mid-infrared region (e.g., wavelengths of 3 μm to 5 μm) are widely used in applications such as sensors and gas analysis.

The active layer of such light-emitting and receiving elements uses an InGaAsSb-based III-V semiconductor containing In, As, and Sb. Conventionally, when epitaxially growing an InGaAsSb-based III-V semiconductor layer such as an InAsSb layer, an InAs substrate or GaSb substrate was used as the growth substrate to achieve lattice matching. However, in recent years, the use of inexpensive GaAs substrates that are not lattice-matched to InAsSb layers has also been considered.

Patent Document 1 describes a compound semiconductor device. In this compound semiconductor device, an i-InGaAs layer, an n-InGaP layer, or the like, which have mismatched lattice constants, is grown on a GaAs substrate, and a first n-GaAs layer thinner than the desired thickness is grown on top of that. Growth is interrupted and the layer is annealed in an arsenic atmosphere, after which a second n-GaAs layer is grown to the desired thickness. It is described that this compound semiconductor device can prevent holes from forming in the second n-GaAs layer, the top layer.

Patent Document 2 describes a method for fabricating a III-V compound semiconductor optical device. This method for fabricating a III-V compound semiconductor optical device includes the steps of: forming a well layer for a quantum well structure made of a first III-V compound semiconductor containing nitrogen and arsenic as group V elements on a III-V compound semiconductor region by molecular beam epitaxy; after forming the well layer, forming a semiconductor layer made of a second III-V compound semiconductor containing arsenic by molecular beam epitaxy; after growing the semiconductor layer, subjecting the quantum well structure to a heat treatment at a heat treatment temperature of 650 degrees Celsius or higher in _an AsH atmosphere using a metal-organic vapor phase epitaxy reactor without film formation; after subjecting the quantum well structure to a heat treatment, lowering the temperature of the metal-organic vapor phase epitaxy reactor to a growth temperature at which a second conductivity type III-V compound semiconductor region is grown in an H atmosphere; and, after lowering the temperature, growing a second conductivity type III-V compound semiconductor region at the growth temperature using a metal-organic vapor phase epitaxy reactor. The quantum well structure in this III-V compound semiconductor optical device may include GaInNAs, GaNAs, GaInNAsSb, GaAs, or GaNAs.

Patent Document 3 describes an infrared light-emitting device. This infrared light-emitting device includes an n-type contact layer formed on one surface of a single-crystal substrate such as a GaAs substrate or a Si substrate, an n-type barrier layer formed on the surface of the n-type contact layer opposite the substrate (on the n-type contact layer), an active layer made of InAsSb formed on the surface of the n-type barrier layer opposite the n-type contact layer (on the n-type barrier layer), a p-type barrier layer formed on the surface of the active layer opposite the n-type barrier layer (on the active layer), and a p-type contact layer made of a compound semiconductor layer primarily composed of GaSb or GaInSb and formed on the p-type barrier layer. The p-type contact layer functions as a contact layer with the electrode, and examples of its materials include InSb, InAs, InAsSb, AlInSb, GaInSb, AlGaInSb, AlInAsSb, GaInAsSb, AlGaInAsSb, AlSb, GaSb, AlGaSb, AlAsSb, GaAsSb, and AlGaAsSb.

It is generally known that if an InGaAsSb layer or InAsSb layer is maintained at a temperature higher than its growth temperature (e.g., 500°C or lower), the Sb evaporates.

Japanese Unexamined Patent Publication No. 7-135304 Japanese Patent Application Laid-Open No. 2008-283078 Japanese Patent Application Laid-Open No. 2018-67632

In the conventional technology described above, there were cases where the light-emitting device including a semiconductor laminate in which an InGaAsSb layer was formed on a GaAs substrate did not provide sufficient light output.

The present invention was made in consideration of these circumstances, and its purpose is to provide a method for manufacturing a semiconductor laminate with high light emission output, and a semiconductor laminate manufactured by this method.

As a result of intensive research conducted by the inventors to achieve the above objectives, it was discovered that when an InGaAsSb layer is annealed (heat-treated) at a temperature higher than its growth temperature to improve its crystallinity, or when another layer is formed after the InGaAsSb layer at a temperature higher than the growth temperature of the InGaAsSb layer, heating the InGaAsSb layer at a temperature higher than its growth temperature can make it difficult to properly control the composition and crystallinity of the InGaAsSb layer, leading to reduced light-emitting output power of the light-emitting diode. Furthermore, even if a cap layer containing no Sb is formed to suppress the evaporation of Sb from the InGaAsSb layer, the evaporation of As from the cap layer can degrade the surface morphology, e.g., smoothness, of other layers containing As but no Sb (e.g., InAs or GaAs) formed after the formation of the InGaAsSb layer. In light of the need to perform annealing while suppressing the evaporation of Sb from the InGaAsSb layer and As from the cap layer, the following invention was completed.

That is, the method for producing a semiconductor laminate according to the present invention for achieving the above object comprises:
an active layer forming step of forming an InGaAsSb layer containing at least In, Sb, and As on a GaAs substrate;
a cap layer formation step of forming an InGaAs layer having a thickness of 10 nm to 40 nm on the InGaAsSb layer;
and a heating step, which is carried out after the cap layer forming step, of heating at a temperature of 520° C. or more and 800° C. or less in an arsenic atmosphere.

In order to achieve the above object, the semiconductor laminate according to the present invention comprises:
a GaAs substrate;
an InGaAsSb layer containing at least In, Sb, and As;
an InGaAs layer having a thickness of 10 nm or more and 40 nm or less;
a GaAs layer;
The InGaAsSb layer, the InGaAs layer, and the GaAs layer are stacked in this order on the GaAs substrate.

We can provide a method for manufacturing a semiconductor laminate with high light emission output, and a semiconductor laminate manufactured using this method.

1A and 1B are diagrams illustrating a configuration of a semiconductor laminate according to an embodiment of the present invention. 10A and 10B are explanatory diagrams of an active layer forming step of forming an InGaAsSb layer. 10A and 10B are explanatory diagrams of a cap layer forming step for forming an InGaAs layer. 10A and 10B are explanatory diagrams of a GaAs layer forming step for forming a GaAs layer. 10A and 10B are diagrams illustrating a configuration of a semiconductor laminate according to another embodiment. 10 is a graph showing differences in temperature changes of the stage in Examples 1 to 4. 1 shows spectra of light emitted from semiconductor laminates according to an example and a comparative example. 10 is an AFM image of the surface of a GaAs layer of a semiconductor laminate according to Example 2. 10 is an AFM image of the surface of a GaAs layer of a semiconductor laminate according to Example 3. 10 is an AFM image of the surface of a GaAs layer of a semiconductor laminate according to Example 4.

Before describing embodiments of the present invention, the following points will be explained in advance.

In this embodiment, the InGaAsSb layer containing at least In, Sb, and As refers to a compound also expressed as an In _x Ga _{1- x} As _1-y Sb _y layer (0<x≦1, 0<y<1). When the layer is simply referred to as an InGaAs layer without specifying at least the elements contained, it refers to a layer made of In _z Ga 1-z As (0≦z≦1). When the layer is referred to as an InGaAs layer, it means that Sb is not included in the composition ratio, but it is acceptable if no Sb source gas is used during growth, and Sb is included as an impurity element due to remaining Sb in the chamber or diffusion from an adjacent layer containing Sb.

In this embodiment, GaAs refers to a III-V compound consisting of Ga as the group III element and As as the group V element. GaAs is permitted to contain impurity elements as long as the effects of the present invention are achieved.

For example, the concentration of impurities such as Zn is determined by SIMS analysis (Secondary Ion Mass Spectrometry).

The thickness of each layer formed by epitaxial growth can be measured using a SEM (electron microscope). If the composition of adjacent layers is sufficiently different, the thickness can be calculated from cross-sectional observation of the grown layer using a SEM or TEM (transmission electron microscope). It is preferable to use an SEM when the layer thickness is 10 nm or more, and a TEM when the layer thickness is less than 10 nm. Furthermore, the thickness of each layer can also be determined based on the thickness measurement results using the SEM (or TEM) described above, using an optical interference film thickness meter attached to the growth apparatus, or calculating the growth rate using XRD.

The root mean square roughness (RMS) value can be a value measured using an atomic force microscope (AFM). In this embodiment, an atomic force microscope (AFM5200S manufactured by Hitachi High-Tech Corporation) is used to measure the surface irregularities of a square area (10 nm x 10 nm square range) with a side length of 10 μm. The root mean square roughness is calculated and used as the RMS value. The RMS value is calculated using the analysis software (SPIWin) that comes with the AFM5200S.

Embodiments of the present invention will now be described with reference to the drawings. For ease of explanation, the aspect ratios of the substrate and each layer in each drawing are exaggerated relative to their actual proportions.

(Summary)
1 shows a semiconductor laminate 100 according to this embodiment. The semiconductor laminate 100 is a semiconductor laminate that can be a component of a light emitting/receiving element (so-called LED) having a wavelength range in the mid-infrared region (for example, a wavelength range of 3 μm to 5 μm).

The semiconductor laminate 100 includes a GaAs substrate 1, an InGaAsSb layer 2 containing at least In, Sb, and As, an InGaAs layer 3 having a thickness of 10 nm to 40 nm, and a GaAs layer 4. In the semiconductor laminate 100, the InGaAsSb layer 2, the InGaAs layer 3, and the GaAs layer 4 are stacked in this order on the GaAs substrate 1.

The method for manufacturing the semiconductor laminate 100 includes an active layer formation process in which an InGaAsSb layer 2 containing at least In, Sb, and As is formed on a GaAs substrate 1; a cap layer formation process in which an InGaAs layer 3 having a thickness of 10 nm to 40 nm is formed on the InGaAsSb layer 2; and a heating process, which is performed after the cap layer formation process, in which the substrate is heated at a temperature of 500°C to 800°C in an arsenic atmosphere.

Note that the manufacturing method for the semiconductor laminate 100 in this embodiment further includes a GaAs layer formation process, which is performed after the cap layer formation process, in which a GaAs layer 4 is formed on the InGaAs layer 3 at a temperature higher than that used when the InGaAs layer 3 was formed.

The GaAs substrate 1, InGaAsSb layer 2, InGaAs layer 3, and GaAs layer 4 may be formed by epitaxial growth using, for example, an MOCVD apparatus.

The method for manufacturing the semiconductor laminate 100 in this embodiment can increase the light emission output of the semiconductor laminate 100.

(Explanation of each part)
Each part of the semiconductor laminate 100 will be described below.

As shown in FIG. 1, GaAs substrate 1 may be a substrate made of GaAs single crystal or a template substrate including a plate-shaped layer of GaAs formed on its surface. As described below, an InGaAsSb layer 2, an InGaAs layer 3, and a GaAs layer 4 are stacked in this order on GaAs substrate 1. In the following description, the stack of other layers, such as the InGaAsSb layer 2, on GaAs substrate 1 may be collectively referred to simply as a laminate.

The GaAs substrate 1 can be n-type. The surface orientation of the GaAs substrate 1 on which the InGaAsSb layer 2 is grown (epitaxially) can be (100), or an off-axis angle can be applied.

The InGaAsSb layer 2 is an active layer of the semiconductor laminate 100 that contains at least In, Sb, and As. The InGaAsSb layer 2 is also expressed as an In _x Ga _1-x As _1-y Sb _y layer (0<x≦1, 0<y<1). An example of the InGaAsSb layer 2 is an InAsSb layer made of InAsSb (InAs _1-y Sb _y , 0<y<1).

The InGaAsSb layer 2 is formed on one side of the GaAs substrate 1. That is, in the active layer formation process for forming the InGaAsSb layer 2, the InGaAsSb layer 2 is formed on one side of the GaAs substrate 1 (see Figure 2). The InGaAsSb layer 2 is formed to a thickness of, for example, 200 nm or more and 700 nm or less. The InGaAsSb layer 2 is preferably formed at a temperature below 520°C, for example, at 500°C.

The InGaAs layer 3 is a layer made of _{InzGa1 -} zAs (0≦z≦1). To reduce the lattice constant difference between the layers sandwiching the InGaAs layer 3, it preferably contains In, and most preferably InAs. The InGaAs layer 3 is formed on the surface of the InGaAsSb layer 2 opposite to the surface facing the GaAs substrate 1. That is, in the cap layer formation step of forming the InGaAs layer 3, the InGaAs layer 3 is formed on the surface of the InGaAsSb layer 2 opposite to the surface facing the GaAs substrate 1 (see FIG. 3). The InGaAs layer 3 is a cap layer that suppresses evaporation of Sb from the InGaAsSb layer 2. The InGaAs layer 3 is preferably formed to a thickness of 10 nm to 40 nm. The growth temperature during the formation of the InGaAs layer 3 is preferably less than 550°C to prevent Sb from evaporating, more preferably less than 520°C, and is preferably lower than the growth temperature of the GaAs layer 4 described below. The same temperature (e.g., 500°C) as the growth temperature of the InGaAsSb layer 2 is most preferable. That is, in the cap layer formation step for forming the InGaAs layer 3, the InGaAs layer 3 is grown at less than 550°C, and the InGaAs layer 3 is formed to a thickness of 10 nm to 40 nm.

The GaAs layer 4 is a layer made of GaAs. The GaAs layer 4 is formed on the surface of the InGaAs layer 3 opposite the surface facing the GaAs substrate 1. That is, the GaAs layer formation process for forming the GaAs layer 4 is performed after the cap layer formation process, and the GaAs layer 4 is formed on the surface of the InGaAs layer 3 opposite the surface facing the GaAs substrate 1 (see Figures 1 and 4). In this embodiment, the GaAs layer formation process is preferably performed in an arsenic atmosphere (see Figure 4).

When a light-emitting/receiving element is formed using the semiconductor laminate 100, the GaAs layer 4 forms a surface base for forming another layer (e.g., a contact layer for reducing contact resistance with an electrode) on the GaAs layer 4 surface of the semiconductor laminate 100. The GaAs layer 4 can also serve as part of the cladding layer of the light-emitting/receiving element, for example. Although the difference in lattice constant between the GaAs layer 4 and the InGaAsSb layer 2 is large, sandwiching the InGaAsSb layer 2 between the GaAs substrate 1 and the GaAs layer 4 can sometimes suppress the occurrence of cracks in the InGaAsSb layer 2. The thickness of the GaAs layer 4 is preferably 150 nm or more and 1000 nm or less. The thickness of the GaAs layer 4 is more preferably 300 nm or more and 800 nm or less.

If the heating process described below is performed during the GaAs layer formation process, it is recommended that the thickness of the GaAs layer 4 be 300 nm or greater. This may prevent cracks in the GaAs layer 4. It may also improve the flatness of the surface of the GaAs layer 4 (the surface of the GaAs layer 4 opposite the surface facing the GaAs substrate 1).

The GaAs layer formation process is a process in which the GaAs layer 4 is grown at a growth temperature that exceeds the growth temperature used to form the InGaAs layer 3.

The GaAs layer formation process may include a first film formation process in which the GaAs layer 4 is grown at a growth temperature that exceeds the growth temperature used to form the InGaAs layer 3 but is less than 550°C, and a second film formation process in which the GaAs layer 4 is grown at a growth temperature of 550°C or higher. The first film formation process suppresses evaporation of As from the InGaAs layer 3 during the GaAs layer formation process, thereby improving the light emission output from the InGaAs layer 3. The second film formation process improves the flatness of the surface of the GaAs layer 4 (the surface of the GaAs layer 4 opposite the surface facing the GaAs substrate 1). When the surface flatness of the GaAs layer 4 is improved, the abruptness of the interfaces between each layer and the crystallinity of each layer are improved, thereby improving the light emission output of the semiconductor stack 100.

In the first deposition step, deposition of the GaAs layer 4 may begin at a temperature preferably equal to or higher than 520°C and lower than 550°C. The first deposition step is preferably carried out for at least one minute. A GaAs layer, which is less susceptible to As loss than InAs at high temperatures, is formed on the InAs layer at a lower temperature than in the second deposition step, thereby better suppressing the evaporation of As from the InGaAs layer 3 in the subsequent second deposition step.

The growth temperature of the GaAs layer 4 in the second film formation process is preferably 550°C or higher and 800°C or lower. Setting the temperature at 550°C or higher improves the crystallinity of the InGaAsSb layer 2 through heat treatment, while setting the growth temperature of the GaAs layer 4 in the second film formation process to 800°C or lower suppresses the evaporation of As from the InGaAs layer 3 and GaAs layer 4 during the second film formation process.

In the second film formation step, it is preferable to have a period during which the growth temperature of the GaAs layer 4 is 600°C or higher, and it is even more preferable for this period to be 8 minutes or longer. This may further improve the flatness of the surface of the GaAs layer 4 (the surface of the GaAs layer 4 opposite the surface facing the GaAs substrate 1).

In the second film formation process, there may be a period during which the growth temperature of the GaAs layer 4 is kept constant, or there may be a period during which the growth temperature is increased continuously or in stages (e.g., in a stepwise manner). For example, following the first film formation process, the growth temperature of the GaAs layer 4 may be increased to a predetermined temperature of 550°C or higher and 800°C or lower, and then this predetermined temperature may be maintained until the end of the second film formation process, or the growth temperature of the GaAs layer 4 may be increased continuously or in stages within the range of 550°C to 800°C.

The first and second film formation processes may be performed consecutively. For example, formation of the GaAs layer 4 may be initiated at a growth temperature equal to or higher than the growth temperature used to form the InGaAs layer 3 but lower than 550°C (e.g., 520°C), and then the temperature may be continuously increased to a predetermined temperature lower than 800°C (e.g., 650°C).

After the cap layer formation process, a heating process is performed in which the stack is heated at a temperature of 520°C to 800°C in an arsenic atmosphere. This heating process may be performed separately from the GaAs layer formation process, or simultaneously with the GaAs layer formation process. During the heating process, it is preferable for there to be a period during which the stack is heated to a temperature of 550°C or higher, and it is even more preferable for the period during which the stack is heated to a temperature of 600°C or higher to be 8 minutes or longer. This may further improve the light emission output from the InGaAs layer 3.

If the heating step is performed separately from the GaAs layer formation step, it can be performed before the GaAs layer formation step. If the heating step is performed simultaneously with the GaAs layer formation step, it can be performed simultaneously with the first and second film formation steps of the GaAs layer formation step. For example, when performing the GaAs layer formation step, arsenic-containing gas is used as the GaAs layer source, so the arsenic partial pressure is high, which is equivalent to heating in an arsenic atmosphere. Therefore, the first and second film formation steps can include a heating step. Note that even during the temperature rise time from the completion of formation of the InGaAs layer 3 to the temperature of the heating step (the temperature of the first film formation step), heating in an arsenic atmosphere is required to prevent As from being lost from the InGaAs layer 3.

As described above, the heating step heats the stack in an arsenic atmosphere. One example of an arsenic atmosphere is an AsH ₃ (arsine) atmosphere. The heating step is performed, for example, by flowing AsH ₃ gas through a space (e.g., an MOCVD apparatus) containing the stack, while setting the temperature of a pedestal (e.g., a stage within the MOCVD apparatus) on which the stack is placed to 520°C or higher and 800°C or lower. When the heating step is performed as the second film formation step, the space containing the stack can also be filled with a gallium atmosphere. For example, Ga(CH ₃ ) ₃ (triethylgallium, TEG) gas can be flowed through the space containing the stack together with AsH ₃ gas. The heating step may also be performed in an arsenic-antimony atmosphere (e.g., a mixed atmosphere of AsH ₃ gas and Sb(C ₂ H ₅ ) ₃ (triethylantimony, TESb)).

After the second film formation process, the surface of the GaAs layer 4 (the surface of the GaAs layer 4 opposite the surface facing the GaAs substrate 1) can have a flatness of 5.0 nm or less, as evaluated by the root-mean-square roughness (RMS) value obtained by analyzing a square area with a side length of 10 μm using an AFM.

The semiconductor laminate 100 described above suppresses evaporation of Sb in the InGaAsSb layer 2 and As in the InGaAs layer 3, and the InGaAsSb layer 2 maintains the desired composition and crystalline state, resulting in high light emission output. Furthermore, the flatness of the surface opposite the GaAs substrate 1 is improved, improving the abruptness of the interfaces between each layer in the semiconductor laminate 100 and the crystallinity of each layer, thereby increasing the light emission output of the semiconductor laminate 100.

Other Embodiments
In the above embodiment, the semiconductor laminate 100 is described as having the GaAs substrate 1, the InGaAsSb layer 2, the InGaAs layer 3, and the GaAs layer 4 laminated in this order, and further described as having the InGaAsSb layer 2 formed directly on the surface of the GaAs substrate 1. However, the semiconductor laminate 100 can be modified so as to form a buffer layer 5 between the GaAs substrate 1 and the InGaAsSb layer 2, as shown in FIG. 5 . In this case, the InGaAsSb layer 2 may be formed on the surface of the buffer layer 5.

The buffer layer 5 may include a compound semiconductor layer capable of reducing the lattice constant difference between the GaAs substrate 1 and the InGaAsSb layer 2. Examples of compound semiconductor layers capable of reducing the lattice constant difference between the GaAs substrate 1 and the InGaAsSb layer 2 include InAs, GaSb, InP, and their ternary and quaternary compounds. The buffer layer 5 may include a thin GaAs layer instead of or in addition to the compound semiconductor layer capable of reducing the lattice constant difference between the GaAs substrate 1 and the InGaAsSb layer 2. When forming a thin GaAs layer together with a compound semiconductor layer capable of reducing the lattice constant difference between the GaAs substrate 1 and the InGaAsSb layer 2, the thin GaAs layer may be formed first on the GaAs substrate 1. The thin GaAs layer can clean the surface of the GaAs substrate 1.

The buffer layer 5 is doped with Zn to a Zn concentration of 1 x 10 atoms/cm ^or more, as described in, for example, Japanese Patent Application No. 2021-024641. It can also be an InAs layer formed of a III-V compound consisting mainly of In as the group III and As as the group V. The buffer layer 5 may have a thickness of, for example, 100 nm or more and 600 nm or less. The buffer layer 5 may include a first buffer layer and a second buffer layer having different growth conditions for the epitaxial growth of the InAs layer. By including such a buffer layer 5 in the semiconductor stack 100, the light emission output and surface flatness of the present invention can be further improved in some cases.

The embodiments disclosed in this specification are merely examples, and the present invention is not limited to these. Appropriate modifications can be made without departing from the scope of the present invention. For example, not only may there be a buffer layer 5 between the GaAs substrate 1 and the InGaAsSb layer 2 as in the other embodiments described above, but other layers (not shown) may be inserted between the layers on the GaAs substrate 1, or additional layers may be formed on the GaAs layer 4. Furthermore, the growth temperature may be gradually increased not only in the GaAs layer formation process, but also in the cap layer formation process.

Below, we will explain examples of the semiconductor laminate and the method for manufacturing the semiconductor laminate according to this embodiment.

Example 1
A GaAs substrate was prepared as a template substrate for producing a semiconductor laminate, and an InAsSb layer was formed on this GaAs substrate.

First, a GaAs substrate was placed on a stage inside the chamber of the MOCVD apparatus. Next, the stage temperature was set to 500°C, and the reactor pressure inside the chamber was set to 76 Torr.

(Active layer formation process)
Then, while simultaneously flowing TMI (trimethylindium) gas, _AsH3 (arsine) gas, TESb (triethylantimony) gas, and hydrogen as a carrier gas into the chamber, an InAsSb layer serving as an active layer was grown on the GaAs substrate to a thickness of 300 nm. The composition of the InAsSb layer was _InAs0.9Sb0.1 . The time _for which these gases were flowed, i.e., the growth time, was 692.3 seconds. The flow rates of TMI gas, _AsH3 gas, TESb gas, and hydrogen were 100 sccm, 14 sccm, 175 sccm, and 3000 SLM, respectively. The unit "sccm" represents the gas flow rate ( ^cm3 /min) converted to values at 1 atmosphere and 0°C. The unit "SLM" represents the gas flow rate (L/min) converted to values at 1 atmosphere and 0°C.

(Cap layer forming process)
Subsequently, an InAs layer was grown as a cap layer on the InAsSb layer to a thickness of 30 nm while simultaneously flowing TMI gas, _AsH3 gas, and hydrogen as a carrier gas into the chamber. The flow rates of TMI gas, _AsH3 gas, and hydrogen were 100 sccm, 100 sccm, and 3000 SLM, respectively. The growth time was 112 seconds. The stage temperature was 500°C.

(Heating process)
Thereafter, while AsH ₃ gas and hydrogen as a carrier gas were simultaneously flowing through the chamber, the stage temperature was changed to 600 °C, which is higher than the growth temperature during the formation of the InAs layer as the cap layer, and while AsH ₃ gas and hydrogen as a carrier gas were simultaneously flowing through the chamber, the stack was annealed (heat-treated) at 600 °C. The flow rates of AsH ₃ gas and hydrogen were 100 sccm and 3000 SLM, respectively. The annealing time (heating time) was 1800 seconds from the point when the stage temperature reached 600 °C. The annealed stack was used as the semiconductor stack of Example 1.

Example 2
In Example 2, the steps after the cap layer forming step (after the heating step) are different from those in Example 1, but the steps before the cap layer forming step are the same. The steps after the cap layer forming step will be described below.

(GaAs layer formation process)
After the cap layer formation process, the stage temperature was first raised to 520°C, exceeding the growth temperature for the InAs layer as the cap layer, while simultaneously flowing _AsH3 gas and hydrogen as a carrier gas. The temperature was then linearly increased from 520°C to 650°C over 1904 seconds. Simultaneously with the start of the stage temperature increase from 520°C, TEG (triethylgallium) gas, _AsH3 gas, and hydrogen as a carrier gas were simultaneously flowed into the chamber to grow a GaAs layer on the InAs layer as the cap layer. The GaAs layer thickness was 560 nm. The flow rates of TEG gas, _AsH3 gas, and hydrogen were 75 sccm, 100 sccm, and 3000 SLM, respectively. The growth time was 1904 seconds. In the GaAs layer formation process, the period during which the stage temperature is less than 600° C. corresponds to the first film formation process, and the period after the stage temperature reaches 600° C. corresponds to the second film formation process. The stack after the GaAs layer formation was used as the semiconductor stack according to Example 2.

Example 3
In Example 3, the temperature conditions in the GaAs layer formation step are different from those in Example 2, but the rest are the same. The GaAs layer formation step will be described below.

(GaAs layer formation process)
After the cap layer formation process, the stage temperature was raised to 520°C while simultaneously flowing _AsH gas and hydrogen as a carrier gas, and then the temperature was set to increase linearly from 520°C to 600°C over 1904 seconds. Simultaneously with the start of the stage temperature increase, TEG gas, _AsH gas, and hydrogen as a carrier gas were simultaneously flowed into the chamber to form a GaAs layer, and the resulting stack was used as the semiconductor stack of Example 3.

Example 4
In Example 4, the temperature conditions after the cap layer formation step and in the GaAs layer formation step are different from those in Example 2, but the rest are the same. The steps after the cap layer formation step will be described below.

(GaAs layer formation process)
After the cap layer formation process, the stage temperature was set to 520°C from 500°C immediately after the cap layer formation process while simultaneously flowing _AsH gas and hydrogen as a carrier gas. When the stage temperature reached 520°C, TEG gas, _AsH gas, and hydrogen as a carrier gas were simultaneously flowed into the chamber to form a GaAs layer while maintaining the stage temperature at 520°C. The resulting stack was used as the semiconductor stack of Example 4.

(Comparative Example 1)
In Comparative Example 1, the heating step in Example 1 was not carried out, and the stacked body at the time when the cap layer forming step was completed was used as the semiconductor stacked body of Comparative Example 1.

Figure 6 shows a graph illustrating the differences in stage temperature change in Examples 1 to 4. In Figure 6, the horizontal axis represents process time, and the vertical axis represents stage temperature. In the graph, Section A is the section in which the active layer formation process and cap layer formation process are carried out. Section B is the section in which the heating process (Example 1) or GaAs layer formation process (Examples 2-4) is carried out. Note that while the graph for Comparative Example 1 is not shown in Figure 6, the stage temperature change in the comparative example is the same as the temperature change within Section A in Example 1.

For comparison purposes, the semiconductor laminates of Examples 1 to 4 and Comparative Example 1 were evaluated for photoluminescence (PL) and surface flatness. Photoluminescence (PL) is an evaluation item related to light output; the higher the value, the higher the light output when used as an LED. The flatter the surface, the better the abruptness of the interfaces between layers during epitaxial growth and the crystallinity of each layer (i.e., the better the quality of the epitaxial growth), resulting in higher light output when used as an LED. These results are shown in Table 1 below. In Table 1, the "Presence or Absence of a Heating Step and Its Temperature (°C)" column is marked "Present" for cases where only a heating step was performed and cases where a heating step was performed in the GaAs layer formation process, and marked "Absent" otherwise. Additionally, the "two-stage film formation" category is categorized as "applicable" if, during the GaAs layer formation process, GaAs layer formation is initiated at a temperature of 550°C or less (first film formation process), and then the GaAs layer is grown at a temperature above 550°C and not exceeding 800°C (second film formation process), and otherwise is categorized as "not applicable."

Photoluminescence (PL) evaluation was performed by using an infrared light source with a center wavelength of 1064 nm, irradiating the semiconductor laminate of each example with light of 1064 nm wavelength from the light source, and measuring the intensity of light emitted by excitation of the semiconductor laminate (active layer). Table 1 shows the intensity of infrared light with wavelengths of 4800 nm and 4900 nm emitted from the semiconductor laminate of each example. Figure 7 shows the spectra of light emitted from the semiconductor laminates of the examples and comparative examples. In Figure 7, the horizontal axis represents wavelength (nm) and the vertical axis represents intensity (V). Spectroscopy was performed using a diffraction grating with 150 gratings and a grating spacing of 8 μm and a slit width of 3.0 mm, and intensity was measured using an InSb photodetector.

Surface flatness was evaluated as the root mean square roughness (RMS value) obtained by measuring the unevenness of a square area (10 nm x 10 nm square area) with sides measuring 10 μm on the surface of the semiconductor laminate of each example, opposite the GaAs substrate. The unevenness of the square area was measured using an atomic force microscope (AFM, Hitachi High-Technologies Corporation's AFM5200S), and the RMS value was calculated using the analysis software (SPIWin) provided with the AFM5200S. For the semiconductor laminates of Example 1 and Comparative Example 1, the surface of the InAs layer serving as the cap layer was evaluated. For the semiconductor laminates of Examples 2-4, the surface of the GaAs layer was evaluated. AFM images of the surfaces of the GaAs layers of the semiconductor laminates of Examples 2-4 are shown in Figures 8 to 10.

The results shown in Figures 6 to 10, i.e., the results shown in Table 1, indicate that the semiconductor laminates according to the examples all have high and favorable PL strength compared to the semiconductor laminate according to Comparative Example 1.

In particular, a comparison between Example 1 and Comparative Example 1 shows that the heating process significantly improves the PL strength.

Comparing the individual examples, when a GaAs layer is formed (Examples 2-4), the RMS is 5 nm or less and flatness is better than when a GaAs layer is not formed (Example 1). Furthermore, when a GaAs layer is formed (Examples 2-4), when the first and second film formation processes are performed (Examples 2 and 4), the PL intensity and flatness are better than when the first and second film formation processes are not performed (Example 4). When the first and second film formation processes are performed (Examples 2 and 4), when the temperature in the second film formation process is higher, exceeding 600°C (Example 2), the RMS is 2 nm or less, the flatness is better, and the PL intensity is also higher than when the temperature in the second film formation process is higher and relatively low (Example 3).

These results show that the heating process in an arsenic atmosphere after forming an InAs cap layer has the effect of improving PL intensity. It also shows that forming a GaAs layer after forming the cap layer can be beneficial for improving flatness. It also shows that setting the temperature slightly higher in the latter half of the GaAs layer formation process can be effective in improving both PL intensity and flatness.

In this way, we can provide a method for manufacturing a semiconductor laminate with high light emission output, and a semiconductor laminate manufactured using this method.

The present invention can be applied to semiconductor laminate manufacturing methods and semiconductor laminates.

1: GaAs substrate 100: Semiconductor laminate 2: InGaAsSb layer 3: InGaAs layer 4: GaAs layer 5: Buffer layer A: Section B: Section

Claims (6)

an active layer formation step of forming an InGaAsSb layer (excluding quantum dots) containing at least In, Sb, and As on a GaAs substrate;
a cap layer formation step of forming an InGaAs layer having a thickness of 10 nm to 40 nm directly on the InGaAsSb layer;
a heating step, which is carried out after the cap layer forming step, of heating at a temperature of 520° C. or more and 800° C. or less in an arsenic atmosphere. 2. The method for manufacturing a semiconductor laminate according to claim 1, further comprising a GaAs layer forming step, which is performed after the cap layer forming step, of forming a GaAs layer directly on the InGaAs layer at a temperature higher than that used when forming the InGaAs layer. The GaAs layer forming step includes:
a first deposition step in which deposition of the GaAs layer is initiated at a temperature less than 550°C;
3. The method for producing a semiconductor laminate according to claim 2, further comprising: a second film formation step, which is performed after the first film formation step, of growing the GaAs layer at a temperature of 550° C. or higher and 800° C. or lower. The method for manufacturing a semiconductor laminate described in claim 3, wherein the second film formation step grows the GaAs layer at a temperature of 600°C or higher and 800°C or lower. a GaAs substrate;
an InGaAsSb layer containing at least In, Sb, and As (excluding quantum dots) ;
an InGaAs layer having a thickness of 10 nm or more and 40 nm or less;
a GaAs layer;
the InGaAsSb layer, the InGaAs layer, and the GaAs layer are stacked in this order on the GaAs substrate ;
the InGaAs layer is stacked directly on the InGaAsSb layer,
The GaAs layer is stacked directly on the InGaAs layer , forming a semiconductor laminate. The semiconductor laminate described in claim 5, wherein the root-mean-square roughness value obtained by AFM analysis of a square region with a side length of 10 μm on the surface of the GaAs layer opposite the side facing the InGaAs layer is 5.0 nm or less.