JP7843151B2 - Ceramic electronic components and methods for manufacturing the same - Google Patents

Description

This invention relates to ceramic electronic components and methods for manufacturing the same.

There is a multilayer ceramic capacitor with a pair of external electrodes provided on its lower surface facing the circuit board (see, for example, Patent Documents 1 and 2). Multiple internal electrodes inside the multilayer ceramic capacitor are connected alternately to a pair of external electrodes along the stacking direction via lead electrodes. This type of multilayer ceramic capacitor can reduce the mounting area on the circuit board compared to, for example, a multilayer ceramic capacitor with a pair of external electrodes on each side.

Japanese Patent Publication No. 2017-175105 Japanese Patent Publication No. 2014-123694

However, when the above-mentioned multilayer ceramic capacitor is mounted on a circuit board, if the circuit board flexes due to, for example, a change in ambient temperature, stress from the circuit board will concentrate on the bottom surface, potentially causing fracture between the external and internal electrodes.

Therefore, the present invention has been made in view of the above problems, and aims to provide a ceramic electronic component and a method for manufacturing the same that can suppress fracture between the internal electrode and the external electrode.

The multilayer ceramic capacitor of the present invention comprises a substantially rectangular parallelepiped laminate including a plurality of alternately stacked internal electrode layers and a plurality of dielectric layers, and a pair of external electrodes provided in a pair of substantially rectangular regions on one face of the laminate other than the end faces in the stacking direction, wherein each of the plurality of internal electrode layers has a plurality of lead electrode portions that are alternately connected to the pair of external electrodes along the stacking direction, and in a front view of the one face, the ends of the two lead electrode portions that are connected to one of the pair of external electrodes and are closest to each of the end faces are curved convexly with respect to the end faces so as to move away from the four corners of the rectangular region on which one of the external electrodes is provided .

In the multilayer ceramic capacitor described above, in a front view of the adjacent faces adjacent to both end faces and one of the faces, the pair of ends of the lead electrode portion that is connected to one of the external electrodes and is closest to one of the end faces, on the external electrode side, may be bent so as to protrude toward one of the end faces.

In the above-described multilayer ceramic capacitor, in a front view of one of the surfaces, the ratio of the length of the lead electrode closest to one of the end faces to the length of the lead electrode that is not bent at both ends may be within the range of 1.006 to 1.032.

In the multilayer ceramic capacitor described above, in a front view of one of the surfaces, the ratio of the length of the lead electrode closest to one of the end faces to the length of the lead electrode that is not bent at both ends may be within the range of 1.012 to 1.022.

In the multilayer ceramic capacitor described above, the ratio of the size of the bent portion of the lead electrode closest to one of the end faces in the direction perpendicular to the stacking direction to the size in the stacking direction may be within the range of 3.0 to 5.0 when viewed from the front of one of the faces.

The present invention provides a method for manufacturing a multilayer ceramic capacitor, comprising the steps of: printing an internal electrode pattern including a lead electrode pattern on the surface of a dielectric green sheet using a metal conductive paste ; forming a substantially rectangular parallelepiped laminate by stacking a plurality of dielectric green sheets on which the internal electrode pattern is printed; pressing the laminate to press the plurality of dielectric green sheets together; and forming a pair of external electrodes in a pair of substantially rectangular regions on one face of the laminate other than the end faces in the stacking direction, wherein the lead electrode patterns are alternately connected along the stacking direction, and the step of pressing the plurality of dielectric green sheets together is performed such that, in a front view of the one face, the ends of the two lead electrode patterns of each of the plurality of dielectric green sheets that are connected to one of the pair of external electrodes and are closest to each of the end faces are brought from the four corners of the rectangular region on which one of the external electrodes is provided.
This method involves bending the two end faces in a convex shape so that they move away from the surface .

In the step of pressing together the plurality of dielectric green sheets in the above manufacturing method, a plate-shaped rigid body may be placed along one of the surfaces of both end faces of the laminate.

In the step of pressing together a plurality of dielectric green sheets in the above manufacturing method, a plate-shaped elastic member may be placed between one surface of the end faces of the laminate and the rigid body.

One aspect of this approach is that it can suppress fracture between the internal and external electrodes.

This is a front view showing the multilayer ceramic capacitor of this embodiment. This is a cross-sectional view along the line A-A in Figure 1. This is a cross-sectional view along the line B-B in Figure 1. This is a cross-sectional view along the line C-C in Figure 1. Figure 2 shows a cross-sectional view of a multilayer ceramic capacitor used for comparison. Figure 4 shows a cross-sectional view of a multilayer ceramic capacitor used for comparison. This diagram schematically shows the shape of the lead-out electrode section when the bottom surface of the stacked chip is viewed from the front. This diagram schematically shows other shapes of the lead-out electrode section when the bottom surface of the stacked chip is viewed from the front. This shows an example of the manufacturing process for multilayer ceramic capacitors. This is a front view showing an example of an internal electrode pattern corresponding to one of the internal electrode layers. This is a front view showing an example of an internal electrode pattern corresponding to the other internal electrode layer. This figure shows an example of the lamination process. This figure shows an example of a laminate that has been pressed using hydrostatic pressure.

[Embodiment]
(Configuration of multilayer ceramic capacitors)
Figure 1 is a front view showing the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view along line A-A in Figure 1, Figure 3 is a cross-sectional view along line B-B in Figure 1, and Figure 4 is a cross-sectional view along line C-C in Figure 1. In Figures 1 to 3, the Z axis indicates the stacking direction of the multilayer ceramic capacitor 1. The X and Y axes are the directions in which the two pairs of opposing surfaces, other than the end faces in the stacking direction of the multilayer ceramic capacitor 1, face each other.

The multilayer ceramic capacitor 1 is an example of a ceramic electronic component, comprising a substantially rectangular parallelepiped-shaped multilayer chip 10 and a pair of external electrodes 40 and 41 provided on the lower surface 10A of the multilayer chip 10. The multilayer chip 10 is an example of a laminate, containing a plurality of alternately stacked internal electrode layers 20 and 21 and a plurality of dielectric layers 31. Cover layers 30 and 32 are stacked at both ends of the multilayer chip 10 in the stacking direction (Z-axis direction). Each internal electrode layer 20 and 21 contains a base metal material, while the cover layers 30 and 32 and each dielectric layer 31 contain ceramic material as their main component.

The cover layers 30, 32 and the dielectric layer 31 mainly consist of a ceramic material having a perovskite structure represented by the general formula _ABO3 . This perovskite structure includes ABO3 _-α , which is outside the stoichiometric composition. For example, at least one of the following ceramic materials can be selected and used: _BaTiO3 (barium titanate), _CaZrO3 (calcium zirconate), _CaTiO3 (calcium titanate), _SrTiO3 (strontium titanate), _MgTiO3 (magnesium titanate), Ba _1-x-y Ca _x Sr _y Ti _1-z Zr _{z O3} (0≦x≦1, 0≦y≦1, 0≦z≦1), etc., which form a perovskite structure. Ba _1-x-y Ca _x Sr _y Ti _1-z Zr _z O ₃ includes barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, and barium calcium zirconate titanate.

Each internal electrode layer 20, 21 is primarily composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Precious metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layers 20, 21.

The external electrodes 40 and 41 are mainly composed of Ni, Cu, etc. The surfaces of the external electrodes 40 and 41 may be provided with a plating layer mainly composed of metals such as Cu, Ni, Al, Zn, Sn, or alloys of two or more of these.

The external electrodes 40 and 41 have a substantially flat shape extending in the Z-axis direction and are arranged on the lower surface 10A so as to be adjacent to each other in the X-axis direction. The lower surface 10A is one of the four surfaces of the multilayer chip 10 in the stacking direction (Z-axis direction), excluding the end faces 10B and 10C, that faces the mounting surface of the circuit board W. The multilayer ceramic capacitor 1 is mounted on the circuit board W by solder S attached to the external electrodes 40 and 41. In this case, when the circuit board W bends, for example due to a change in ambient temperature, the stress Fv from the circuit board concentrates on the lower surface 10A.

The internal electrode layers 20 and 21 have a substantially rectangular shape when viewed from the front in the stacking direction of the multilayer chip 10. The internal electrode layer 20 has lead-out electrode portions 200a and 200b connected to the external electrode 40, and the internal electrode layer 21 has lead-out electrode portions 210a and 210b connected to the external electrode 41. The internal electrode layers 20 and 21 are arranged alternately along the stacking direction of the multilayer chip 10.

In a front view of the stacked chip 10 in the stacking direction, the internal electrode layers 20 and 21 overlap each other, while the lead electrode portions 200a and 200b are arranged so as not to overlap with the lead electrode portions 210a and 210b. The lead electrode portions 200a and 200b and the lead electrode portions 210a and 210b are alternately connected to the external electrodes 40 and 41 along the stacking direction of the stacked chip 10.

The lead-out electrode portions 200a and 200b extend toward the external electrode 40 from one end of the side facing the lower surface 10A, one of the four sides forming the outer edge of the internal electrode layer 20, and are exposed to the lower surface 10A. The lead-out electrode portions 210a and 210b extend toward the external electrode 41 from the other end of the side facing the lower surface 10A, one of the four sides forming the outer edge of the internal electrode layer 20, and are exposed to the lower surface 10A.

Figure 3 shows the lower surface 10A when the external electrodes 40 and 41 are removed from the laminated chip 10. The external electrodes 41 and 40 are provided in a pair of approximately rectangular regions Sa and Sb within the lower surface 10A, respectively. That is, the laminated chip 10 is joined to the external electrodes 41 and 40 in regions Sa and Sb of the lower surface 10A. Regions Sa and Sb are set to be spaced apart from each other in the X-axis direction. When the circuit board B is deflected, a greater stress Fv is applied to the corner Cf on the end face 10B side and the corner Cb on the end face 10C side of regions Sa and Sb than to other parts.

In a front view of the lower surface 10A, both ends 200R, 200L, 210R, and 210L of the lead electrode portions 200a and 210a on one end face 10B in the stacking direction are curved so as to be convex toward end face 10B. Specifically, both ends 200R, 200L, 210R, and 210L are curved in an arc toward the other end face 10C. On the other hand, the other lead electrode portion 200b is substantially straight overall, with no curves at either end. In this embodiment, the two lead electrode portions 200a and 210a on the end face 10B side are curved, but it is sufficient that at least the lead electrode portions 200a and 210a closest to end face 10B are curved.

On the other hand, Figure 5 is a cross-sectional view of the multilayer ceramic capacitor 1a used for comparison in Figure 2. In Figure 5, components common to both Figure 2 and Figure 2 are denoted by the same reference numerals, and their explanations are omitted. In a front view of the multilayer chip 10, all lead-out electrode portions 200b are substantially straight overall, with no bends at either end.

In the multilayer ceramic capacitor 1 of this embodiment, the ends 200R, 200L, 210R, and 210L of the lead electrode portions 200a and 210a closest to one end face 10B are bent so as to protrude toward the end face 10B. Therefore, compared to the multilayer ceramic capacitor 1a used for comparison, the ends 200R, 200L, 210R, and 210L can be moved further away from the corner Cf on the end face 10B side in the regions Sa and Sb where the external electrodes 41 and 40 are provided.

This reduces the stress Fv applied to the lead electrode portions 200a and 210a on the end face 10B side, thereby suppressing fracture between the lead electrode portions 200a and 210a and the external electrodes 40 and 41. In this embodiment, there are two lead electrode portions 200a and 210a, each with bent ends 200R, 200L, 210R, and 210L, but this is not limited to this; there may be only one, or three or more.

When there are multiple lead electrode portions 200a, 210a with bent ends (200R, 200L, 210R, 210L), the degree of bending decreases as the lead electrode portions 200a, 210a are further from the end face 10B. Therefore, the conductivity with the external electrodes 40, 41 improves as the lead electrode portions 200a, 210a are further from the end face 10B. Furthermore, the lead electrode portions 200a, 210a closer to the end face 10B are more susceptible to bending in the direction indicated by arrow T in Figure 2, and thus subjected to larger loads. However, as the size of the bent portion in the stacking direction (see v in Figure 7, described later) increases as the lead electrode portions 200a, 210a closer to the end face 10B, their durability against loads increases.

Furthermore, both ends of the lead-out electrode portions 200b and 210b closest to the other end face 10C may also be curved to protrude toward the end face 10C, similar to the lead-out electrode portions 200a and 210a. In this case, since both ends of the lead-out electrode portions 200b and 210b can be moved away from the corner Cb on the end face 10C side in regions Sa and Sb, fracture between the lead-out electrode portions 200a and 210a and the external electrodes 40 and 41 is further suppressed.

Figure 4 shows the internal electrode layers 20 and 21 when viewed from the front, on one of the two side surfaces 10E and 10D adjacent to the bottom surface 10A and end surfaces 10B and 10C (10E). The internal electrode layer 20 is connected to one of the external electrodes 40 via the lead-out electrode portions 200a and 200b. The external electrode 40 extends in the Z-axis direction, and a larger stress Fv is applied to its pair of ends Ef and Eb due to the deflection of the circuit board W.

In the lead electrode portion 200a on the end face 10B side, the end Td on the external electrode 40, 41 side is curved in an arc toward the end face 10C side. On the other hand, the other lead electrode portion 200b is substantially straight overall, with neither end curved.

On the other hand, Figure 6 is a cross-sectional view of the multilayer ceramic capacitor 1a used for comparison in Figure 4. In Figure 6, components common to both Figure 4 and Figure 4 are denoted by the same reference numerals, and their descriptions are omitted. In the comparison multilayer ceramic capacitor 1a, all lead electrode portions 200b are substantially straight overall, and the ends on the external electrode 40, 41 side are not bent.

In the multilayer ceramic capacitor 1 of this embodiment, the end Td of the lead electrode portion 200a closest to one end face 10B is curved in an arc toward the end face 10C. Therefore, compared to the multilayer ceramic capacitor 1a used for comparison, the end Td can be moved further away from the end Ef of the external electrode 40 on the end face 10B side.

This reduces the stress Fv applied to the lead-out electrode portions 200a and 210a on the end face 10B side, thereby suppressing fracture between the lead-out electrode portions 200a and 210a and the external electrodes 40 and 41. In this embodiment, there are two lead-out electrode portions 200a and 210a with bent ends Td, but this is not limited to one, and there may be one or three or more.

When there are multiple bent lead electrode portions 200a and 210a with their ends Td on the external electrode 40 and 41 side, the degree of bending decreases for lead electrode portions 200a and 210a further from the end face 10B. Therefore, the conductivity with the external electrodes 40 and 41 improves for lead electrode portions 200a and 210a further from the end face 10B.

Furthermore, while this embodiment mentions the lead electrode portion 200a connected to one external electrode 40, the end of the lead electrode portion 210a connected to the other external electrode 41 can also be bent in the same way as the lead electrode portion 200a. This similarly reduces the stress Fv and suppresses fracture between the lead electrode portions 200a, 210a and the external electrodes 40, 41.

Furthermore, the ends of the lead-out electrode portions 200b and 210b on the other end face 10C side, specifically the ends on the external electrode 40 and 41 side, may also be curved to protrude toward the end face 10C, similar to the lead-out electrode portions 200a and 210a. In this case, the ends of the lead-out electrode portions 200b and 210b can be moved away from the end Eb of the external electrode 40 on the end face 10C side, further suppressing fracture between the lead-out electrode portions 200a and 210a and the external electrodes 40 and 41.

The bent shape of the lead electrode portions 200a and 210a is formed by the compression process during the manufacturing of the multilayer ceramic capacitor 1. Due to the compression process, in the stacking direction of the multilayer chip 10, the areas where lead electrode portions 200a, 200b, 210a, and 210b are not present are compressed more than the areas where lead electrode portions 200a, 200b, 210a, and 210b are present. Therefore, as shown in Figure 3, a recess 100 is formed between the lead electrode portions 200a, 200b and 210a, 210b at the end face 10B due to compression.

Figure 7 schematically shows the shape of the lead electrode portion 210a when the lower surface 10A of the stacked chip 10 is viewed from the front. 'a' represents the length of the substantially straight lead electrode portion 210b, which is not bent at both ends. 'b' represents the length of the lead electrode portion 210a, which has bent ends 210R and 210L. Here, length 'b' is the length of the lead electrode portion 210a closest to the end face 10B in the stacking direction. Furthermore, the positions of both ends of the lead electrode portions 210a and 210b are aligned in the stacking direction. In this embodiment, lengths 'a' and 'b' are 100.0 (μm) or greater.

A ratio of length b to length a within the range of 1.006 to 1.032 is preferable because it effectively suppresses poor conductivity due to temperature changes. Furthermore, a ratio of length b to length a within the range of 1.012 to 1.022 is even more preferable because it suppresses the load generated by the deflection of the circuit board W.

v and h represent the vertical and horizontal dimensions of the bent portions 210R and 210L at both ends of the lead electrode portion 210a closest to the end face 10B in the stacking direction. Size v is the size of the bent portion in the stacking direction, and size h is the size in the direction perpendicular to the stacking direction, i.e., the direction s in which the lead electrode portion 210a extends approximately in a straight line.

In other words, h represents the distance from the starting point Ps to the ending point Pe of the bend in the direction s in which the lead electrode portion 210a extends substantially linearly. In this embodiment, the distance h is 5.0 μm or more. Furthermore, v represents the distance from the starting point Ps to the ending point Pe of the bend in the direction perpendicular to the direction s in which the lead electrode portion 210a extends substantially linearly. In this embodiment, the distance v is 1.0 μm or more. The same a, b, h, and v are defined for the other lead electrode portions 200a and 200b as described above.

Setting the ratio of distance h to length b within the range of 0.149 to 0.291, and the ratio of distance v to length b within the range of 0.030 to 0.097, is preferable because it allows for sufficient junction area of the multilayer ceramic capacitor 1 while suppressing the load generated by the deflection of the circuit board W.

Figure 8 schematically shows another shape of the lead electrode portion 210a when the lower surface 10A of the multilayer chip 10 is viewed from the front. In Figure 8, the explanation of parameters common to Figure 7 is omitted. In this embodiment, the multilayer ceramic capacitor 1 has lead electrode portions 200a and 210a, with their ends 210R and 210L bent, provided on both ends of the lower surface 10A of the multilayer chip 10 in the stacking direction. That is, the lead electrode portions 200a and 210a closest to the end faces 10B and 10C are bent.

(Manufacturing process of multilayer ceramic capacitors)
Figure 9 shows an example of the manufacturing process for a multilayer ceramic capacitor 1. The manufacturing process for the multilayer ceramic capacitor 1 is an example of a method for manufacturing ceramic electronic components.

(Green sheet molding process)
First, the green sheet molding process St1 is performed. For example, in the green sheet molding process St1, a dielectric material obtained by adding various additive compounds (such as sintering aids) to ceramic powder is wet-mixed with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer. Using the resulting slurry, a dielectric green sheet with a thickness of, for example, 4 μm or more is coated onto a substrate using a die coater or doctor blade method and dried. The substrate is, for example, a PET (polyethylene terephthalate) film.

Furthermore, the additive compounds used in ceramic powders include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holomium), Er (erbium), Tm (thulium), and Yb (ytterbium)), as well as oxides or glass of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

(Internal electrode printing process)
Next, the internal electrode printing process St2 is performed. The internal electrode printing process St2 is an example of a process in which an internal electrode pattern, including an extraction electrode pattern, is printed on the surface of the dielectric green sheet using a metal conductive paste. In the internal electrode printing process St2, a metal conductive paste for forming internal electrodes, which contains an organic binder, is printed onto the dielectric green sheet on the substrate by screen printing, gravure printing, or the like, thereby forming a film with multiple internal electrode patterns spaced apart from each other. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but it is preferable that it is the same as the main component ceramic of the dielectric layer 31.

Figure 10 is a front view showing an example of an internal electrode pattern 60 corresponding to one of the internal electrode layers 20. Multiple internal electrode patterns 60 are printed vertically and horizontally on the dielectric green sheet 51. The dielectric green sheet 51 is cut along the dotted lines in the cutting process St5 described later. At the ends of each internal electrode layer pattern 60, a lead electrode pattern 600 corresponding to the lead electrode portions 200a and 200b is provided.

Figure 11 is a front view showing an example of an internal electrode pattern 61 corresponding to the other internal electrode layer 21. Multiple internal electrode patterns 61 are printed vertically and horizontally on the dielectric green sheet 52. The dielectric green sheet 52 is cut along the dotted lines in the cutting process St5 described later. At the ends of each internal electrode pattern 61, a lead electrode pattern 610 corresponding to the lead electrode portions 210a and 210b is provided. Note that the internal electrode layers 20 and 21 may be printed on a common dielectric green sheet.

(Lamination process)
Referring again to Figure 9, the next step is the lamination process St3. Lamination process St3 is an example of a process in which a laminated body in a substantially rectangular parallelepiped shape is formed by laminating a plurality of dielectric green sheets 51, 52 on which internal electrode patterns 60, 61 are printed.

Figure 12 shows an example of the lamination process St3. Figure 12 shows portions of dielectric green sheets 50-53 corresponding to one laminated chip 10 minutes. Dielectric green sheet 51, with one internal electrode pattern 60 printed on it, and dielectric green sheet 52, with the other internal electrode pattern 61 printed on it, are laminated alternately. At both ends of the laminated dielectric green sheets 51 and 52 in the lamination direction, dielectric green sheets 53 and 50, corresponding to cover layers 30 and 32, are laminated, respectively. This forms a laminated body 7 corresponding to the laminated chip 10.

Referring again to Figure 9, the next step is the crimping process St4. The crimping process St4 is an example of a process in which the multiple dielectric green sheets 50-53 are crimped together by applying pressure to the laminate 7. The laminate 7 is crimped, for example, by a hydrostatic press.

Figure 13 shows an example of a laminated body 7 that has been hydrostatically pressed. In Figure 13, components common to Figures 10 to 12 are denoted by the same reference numerals, and their explanations are omitted. Furthermore, during hydrostatic pressing, the laminated body 7 is sandwiched between, for example, a resin film, but the resin film is not shown in the figure.

Figure 13 shows the end face 7A of the laminated body 7 when viewed from the front in the Y-axis direction, as shown in Figure 10. End face 7A corresponds to the lower surface 10A of the laminated chip 0, while end faces 7B and 7C correspond to the end faces 10B and 10C of the laminated chip 10, respectively. The line Lc indicates the position where the laminated body 7 is cut in the cutting process St5, which will be described later.

The end face 7A exposes the lead electrode patterns 600 and 610. The laminate 7 is subjected to pressure mainly from both end faces 7B and 7C in the stacking direction. Here, the dielectric green sheets 51 and 52 do not have a dielectric layer to eliminate the step difference with the internal electrode patterns 60 and 61. Therefore, the regions 70 and 71 where the lead electrode patterns 600 and 610 are not present are compressed more than the regions where the lead electrode patterns 600 and 610 are present.

During the hydrostatic pressing of the laminate 7, a plate-shaped support 9 is positioned along the surface of the end face 7C on the dielectric green sheet 50 side. The support 9 is, for example, a rigid material such as stainless steel. This allows the support 9 to support the laminate 7 against the pressure applied to its opposite end face 7B.

Therefore, the laminate 7 is compressed by the pressure on the end face 7B. This creates recesses 530 and 531 on the end face 7B. Recess 530 corresponds to recess 100 of the laminate chip 10.

Furthermore, in the lead electrode patterns 600 and 610 on the end face 7B side, the ends 600R, 600L, 610R, and 610L adjacent to regions 70 and 71 are bent in an arc shape toward the other end face 7C side in accordance with the compression of regions 70 and 71. These lead electrode patterns 600 and 610 correspond to the lead electrode portions 200a and 210a of the laminated chip 10, and their ends 600R, 600L, 610R, and 610L correspond to the ends 200R, 200L, 210R, and 210L of the lead electrode portions 200a and 210a.

Thus, in the crimping process St4, in a front view of the end face 7A of the laminate 7, both ends 600R, 600L, 610R, 610L of the lead electrode patterns 600 and 610 on one end face 7B side are bent in an arc shape so that they protrude toward the end face 7B side. At this time, if at least both ends 600R, 600L, 610R, 610L of the lead electrode patterns 600 and 610 closest to the end face 7B are bent, the same effects as those of the multilayer ceramic capacitor 1 described above can be obtained; however, multiple lead electrode patterns 600 and 610 on the end face 7B side may also be bent.

Furthermore, in this embodiment, since the support 9 is placed on the end face 7C side, only the ends 600R, 600L, 610R, and 610L of the lead electrode patterns 600 and 610 on the end face 7B side are bent. However, this is not limited to this, and the support 9 may not be provided. In this case, the ends 600R, 600L, 610R, and 610L of the lead electrode patterns 600 and 610 on the other end face 7C side can also be bent by pressure in the same manner as described above.

Furthermore, when the support 9 is placed, the degree of bending at both ends 600R, 600L, 610R, 610L can be adjusted by placing a plate-shaped elastic member 90 between the support 9 and the laminate 7. For example, if rubber is used as the elastic member, the degree of bending at both ends 600R, 600L, 610R, 610L will be greater than when PET (Polyethylene Terephthalate) film is used. Note that the degree of bending is not limited to this; it can be adjusted, for example, by relatively changing the thickness of the dielectric green sheets 51, 52 and the thickness of the internal electrode patterns 60, 61.

(Cutting process)
Referring again to Figure 7, the next step is cutting step St5. In cutting step St5, the laminated body 7, which has completed the crimping process, is cut (diced) along the line Lc mentioned above.

(polishing process)
Next, polishing step St6 is performed. In polishing step St6, the individual laminated bodies 7 after cutting are polished using a method such as barrel polishing. This gives the corners of the laminated bodies 7 a rounded shape.

(Firing process)
Next, firing process St7 is performed. In firing process St7, the laminate 7 is debindered in an _N2 atmosphere at 250 to 500°C, and then fired in a reducing atmosphere with an oxygen partial pressure of ^10⁻⁸ to ^10⁻¹³ atm at 1100 to 1300°C for 10 minutes to 2 hours, thereby sintering each particle within the laminate 7. As a result, the dielectric green sheets 50 to 53 become the dielectric layers 31 and cover layers 30 and 32, and the internal electrode patterns 60 and 61 become the internal electrode layers 20 and 21, thereby obtaining the laminated chip 10.

(External electrode formation process)
Next, the external electrode formation step St8 is performed. The external electrode formation step St8 is an example of a step in which a pair of external electrodes 41 and 40 are formed in a pair of substantially rectangular regions Sa and Sb within the lower surface 10A of the laminated chip 10.

In the external electrode formation step St8, external electrodes 40 and 41 are formed by applying a metal paste containing, for example, metal powder, glass frit, binder, and solvent to the lower surface 10A of the laminated chip 10 and drying it. The binder and solvent evaporate during baking. Examples of methods for applying the metal paste include sputtering and dipping. When using the dipping method, the external electrode formation step St8 may be performed before the firing step St7, as in this example.

In this way, the multilayer ceramic capacitor 1 is manufactured. According to the manufacturing process of the multilayer ceramic capacitor 1, the same effects as those of the multilayer ceramic capacitor 1 can be obtained.

Next, the evaluation results of the seismic resistance test and heat cycle test of the multilayer ceramic capacitor 1 are presented. For the evaluation, 1000 samples each of sample No. 1 of the comparative ceramic capacitor 1a and samples No. 2 to 7 of the example ceramic capacitor 1 were used. Furthermore, the dielectric layer 31 and cover layers 30, 32 of the multilayer chip 10 were mainly composed of barium titanate, the internal electrode layers 20, 21 were mainly composed of nickel, and the external electrodes 40, 41 were mainly composed of nickel. The size of the multilayer ceramic capacitors 1 and 1a was set to 1005 size.

Furthermore, the heat cycle test involved operating the test apparatus in a 25°C environment for 15 minutes, then in a 40°C environment for 30 minutes, then in a 25°C environment for 15 minutes, then in a 140°C environment for 30 minutes, and finally in a 25°C environment for 15 minutes, with each cycle being considered one cycle. Meanwhile, the seismic resistance test involved vibrating ceramic capacitors 1 and 1a for 20 minutes in three mutually perpendicular directions with vibration frequencies ranging from 10 to 2000 Hz and an acceleration of 5G.

Table 1 shows the evaluation results for samples No. 1 to 7. In the table, a, b, h, and v represent parameters related to the lead-out electrode sections 200a, 200b, 210a, and 210b, as described with reference to Figures 7 and 8. In this example, the degree of bending is expressed as the ratio of length b to length a. Lengths a, b, and sizes v and h were calculated from the shape of the lead-out electrode section closest to the end face 10B.

Since the multilayer ceramic capacitor 1a of sample No. 1 does not have a bent lead electrode portion 210a, only the length b of the unbent lead electrode portion 210b is valid among the above parameters. The shape of the lead electrode portion 210a when the lower surface 10A of the multilayer chip 10 of samples No. 2 to 6 is as shown in Figure 7. The shape of the lead electrode portion 210a when the lower surface 10A of the multilayer chip 10 of sample No. 7 is as shown in Figure 8.

In sample No. 1, the multilayer ceramic capacitor 1a has nearly straight lead electrodes 200b and 210b, with no bends at either end. Therefore, in the heat cycle test, when stress Fv was applied to the lead electrodes 200b and 210b from the external electrodes 40 and 41 due to the bending of the circuit board B caused by temperature changes, fracture occurred between the external electrodes 40 and 41 and the lead electrodes 200b and 210b, resulting in poor conductivity and a failure (NG). Furthermore, in the seismic resistance test, the stress Fv could not be relieved, resulting in a decrease from the initial performance and a failure (NG). Here, initial performance refers to the performance in the initial state. Therefore, the evaluation result for sample No. 1 was deemed unacceptable.

Sample No. 2, a multilayer ceramic capacitor 1, showed no decrease in performance from its initial state during the seismic resistance test, as the ends 200R, 200L, 210R, and 210L of the lead electrodes 200a and 210a were bent. However, in the heat cycle test, the degree of bending at both ends 200R, 200L, 210R, and 210L was smaller than that of samples No. 3 to 7, resulting in insufficient reduction of stress Fv. This caused fracture between the external electrodes 40 and 41 and the lead electrodes 200b and 210b, resulting in poor conductivity and a failure. Therefore, the evaluation result for sample No. 2 was deemed acceptable.

In the multilayer ceramic capacitor 1 of samples No. 6 and 7, the ends 200R, 200L, 210R, and 210L of the lead electrodes 200a and 210a were bent. However, no decrease in performance from the initial stage was observed in the seismic resistance test, and therefore it was deemed OK.

However, in sample No. 6, the degree of bending at both ends (200R, 200L, 210R, 210L) was greater than in samples No. 2-5, resulting in a reduced contact area with the external electrodes 40 and 41. Similarly, in sample No. 7, the bending at both ends (200R, 200L, 210R, 210L) of the lead-out electrode sections on both end faces 10B and 10C in the lamination direction also reduced the contact area with the external electrodes 40 and 41. Therefore, in the heat cycle test, poor conductivity occurred due to the reduced contact area, resulting in a failure (NG). For this reason, the evaluation results for samples No. 6 and 7 were deemed acceptable.

In the multilayer ceramic capacitors 1 of samples No. 3-5, the ends 200R, 200L, 210R, and 210L of the lead electrodes 200a and 210a were bent. However, no decrease in performance from the initial stage was observed in the seismic resistance test, and therefore, it was deemed OK.

Furthermore, the degree of bending at both ends 200R, 200L, 210R, and 210L of the lead electrode portions 200a and 210a of samples No. 3 to 5 was greater than that of sample No. 2 and less than that of sample No. 6. Therefore, the stress Fv was reduced compared to sample No. 2, and the contact area with the external electrodes 40 and 41 was increased compared to samples No. 6 and 7. As a result, no conductivity failures occurred in the heat cycle test, and the results were satisfactory. Therefore, the evaluation results for samples No. 3 to 5 were given as excellent.

Thus, in samples No. 3 to 5, the ratio of length b to length a is set within the range of 1.006 to 1.032. Furthermore, in samples No. 3 to 5, the ratio of size h to size v is set within the range of 3.0 to 5.0. This not only sufficiently reduces the stress Fv but also ensures sufficient contact area with the external electrodes 40 and 41.

Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the invention as described in the claims.

1, 1a Multilayer ceramic capacitor 7 Laminate 10 Multilayer chip 20, 21 Internal electrode layer 30, 32 Cover layer 31 Dielectric layer 50-53 Dielectric green sheet 60, 61 Internal electrode pattern 200a, 200b, 210a, 210b Lead-out electrode section 40, 41 External electrode 10A Bottom surface 10B, 10C End surface

Claims (9)

A laminate in a substantially rectangular parallelepiped shape comprising multiple internal electrode layers and multiple dielectric layers stacked alternately,
The laminate has a pair of external electrodes provided in a pair of substantially rectangular regions on one of the surfaces other than both end faces in the stacking direction,
Each of the aforementioned internal electrode layers has a plurality of lead-out electrode portions that are alternately connected to the pair of external electrodes along the stacking direction,
A ceramic electronic component characterized in that, in a front view of one of the aforementioned surfaces, the ends of two of the plurality of lead-out electrode portions , which are connected to one of the pair of external electrodes and are closest to each of the end faces, are curved convexly with respect to the end faces such that they move away from the four corners of the rectangular region on which one of the external electrodes is provided . The ceramic electronic component according to claim 1, characterized in that, in a front view of the end faces and adjacent faces adjacent to one of the aforementioned faces, the pair of ends of the lead electrode portion that is connected to one of the external electrodes and is closest to one of the end faces, on the external electrode side, is bent so as to be convex toward one of the end faces. In a front view of the adjacent surfaces, among the plurality of internal electrode layers, the internal electrode layer connected to the other of the external electrode does not have a curved end and extends substantially in a straight line.
The ceramic electronic component according to claim 2. The ceramic electronic component according to any one of claims 1 to 3, characterized in that, in a front view of one of the aforementioned surfaces, the ratio of the length of the lead electrode portion closest to one of the end faces to the length of the lead electrode portion that is not bent at both ends is within the range of 1.006 to 1.032. The ceramic electronic component according to any one of claims 1 to 3, characterized in that, in a front view of one of the aforementioned surfaces, the ratio of the length of the lead electrode portion closest to one of the end faces to the length of the lead electrode portion that is not bent at both ends is within the range of 1.012 to 1.022. The ceramic electronic component according to any one of claims 1 to 3, characterized in that, in a front view of one of the aforementioned surfaces, the ratio of the size of the bent portion of the lead-out electrode closest to one of the end faces to the size in the stacking direction to the size in the direction perpendicular to the stacking direction is within the range of 3.0 to 5.0 . A process of printing an internal electrode pattern, including an extraction electrode pattern, onto the surface of a dielectric green sheet using a metal conductive paste,
A step of forming a substantially rectangular parallelepiped laminate by stacking a plurality of dielectric green sheets on which the internal electrode pattern is printed,
A step of pressing the laminate to bond multiple dielectric green sheets together,
The process includes forming a pair of external electrodes in a pair of substantially rectangular regions on one face of the laminate other than both end faces in the stacking direction, wherein the extraction electrode patterns are alternately connected along the stacking direction.
A method for manufacturing ceramic electronic components, characterized in that, in a front view of one side, the steps for pressing together a plurality of dielectric green sheets are, in which the ends of two lead electrode patterns that are connected to one of the pair of external electrodes and are closest to each of the end faces are bent convexly with respect to the end faces so as to move away from the four corners of the rectangular region on which one of the external electrodes is provided . The method for manufacturing a ceramic electronic component according to claim 7, characterized in that, in the step of pressing together a plurality of dielectric green sheets, a plate-shaped rigid body is arranged along one surface of the end faces of the laminate. The method for manufacturing a ceramic electronic component according to claim 8, characterized in that, in the step of pressing together a plurality of dielectric green sheets, a plate-shaped elastic member is placed between one surface of the end faces of the laminate and the rigid body.