JP7847465B2 - Optical semiconductor equipment - Google Patents

Description

This invention relates to an optoelectronic device .

Conventionally, in optoelectronic devices equipped with heaters for heating waveguides, there are known optoelectronic devices that have a space and pillars supporting the mesa between the mesa and the substrate in order to improve the heating efficiency of the heater (Patent Document 1).

Japanese Patent Publication No. 2019-087714

As disclosed in Patent Document 1, in this type of optoelectronic device, the flatness of the semiconductor layer, including the waveguide, may be impaired due to the process of providing spaces and pillars.

The inventors, through diligent research into ensuring flatness, have discovered a configuration and manufacturing method for optoelectronic devices that facilitates flatness.

Therefore, one of the objectives of the present invention is to obtain a novel and improved optoelectronic semiconductor device and a method for manufacturing such a device, in which a space and pillars are provided between the mesa and the substrate, for example, flatness can be more easily or reliably ensured.

The optical semiconductor device of the present invention comprises, for example, a base having a substrate and a base surface intersecting a first direction which is the crystal orientation [100] direction; a mesa projecting from the base surface in the first direction and extending along the base surface; a waveguide layer extending along the base surface at an intermediate position of the mesa in the first direction; a heater layer provided on the mesa at a position away from the waveguide layer in the first direction and generating heat upon power supply; and a pillar provided between the substrate and the mesa such that it at least partially overlaps the section of the mesa heated by the heater layer in the first direction, and has a first side surface facing a direction intersecting the first direction and extending in a second direction which intersects the first direction and is non-parallel to the crystal orientation [0-11] direction, wherein a space adjacent to the pillar is provided between the substrate and the mesa.

In the aforementioned optoelectronic device, the semiconductor layers constituting the substrate, the pillar, and the mesa may have a zincblende-type structure.

In the aforementioned optoelectronic device, the substrate, the pillar, and the cladding layer of the mesa may be made of InP.

The optical semiconductor device may include a plurality of pillars separated by the space between them.

The optical semiconductor device may include a plurality of pillars, which are spaced apart from each other in the direction of the mesa's extension.

In the aforementioned optical semiconductor device, an opening may be provided on the base surface that is open in the first direction and connected to the space.

In the aforementioned optical semiconductor device, multiple apertures may be provided as the apertures.

In the aforementioned optical semiconductor device, the plurality of apertures may be arranged such that the mesa is positioned between the plurality of apertures when viewed in the direction opposite to the first direction.

The optical semiconductor device comprises a plurality of pillars separated by space, and has a plurality of DBR blocks of substantially the same length in the direction of extension, arranged at first intervals along the waveguide layer in the direction of extension of the mesa. The pillars may be arranged so as not to overlap the same relative positions of the DBR blocks in the direction of extension when viewed in the opposite direction to the first direction.

In the aforementioned optical semiconductor device, the plurality of pillars may be arranged in the extending direction at a second interval different from the first interval.

The optical semiconductor device may include a partition wall adjacent to the space and made of the same material as the pillar, and a residual layer extending in a direction intersecting the first direction, on the opposite side of the partition wall from the space, and made of a material that is etched by a predetermined etchant having a sufficiently low etching rate for the substrate, the pillar, and the mesa.

In the aforementioned optical semiconductor device, the partition wall may have a second surface that faces a direction intersecting the first direction in at least the section overlapping the mesa and the first direction, and that extends in the second direction.

In the aforementioned optical semiconductor device, the partition wall and the pillar may be connected.

In the aforementioned optical semiconductor device, the mesa may have a portion that extends linearly in the section overlapping the pillar and the space in the first direction.

In the aforementioned optical semiconductor device, the mesa may have a curved portion that extends in a section overlapping the pillar and the space in the first direction.

Furthermore, the present invention provides a method for manufacturing an optoelectronic semiconductor device, comprising: a first step of forming a first layer and a second layer adjacent to each other in a direction intersecting a first direction, which is the crystal orientation [100] direction, on a substrate whose main surface is the crystal orientation (100) plane, wherein the first layer is made of a material with a sufficiently low etching rate to a predetermined etching agent, and the second layer is made of a material that is etched by the etching agent; a second step of forming a mesa extending intersecting the first direction, on the side opposite to the substrate relative to the first and second layers in the first direction, including a waveguide layer and a layer made of a material with a sufficiently low etching rate to the predetermined etching agent; a third step of forming a heater layer for heating the waveguide layer on the mesa; and a fourth step of removing the second layer with the predetermined etching agent, wherein the side surface of the first layer faces a direction intersecting the first direction and extends in a second direction that intersects the first direction and is non-parallel to the crystal orientation [0-11] direction.

According to the present invention, a novel and improved optoelectronic device and a method for manufacturing an optoelectronic device can be obtained.

Figure 1 is an exemplary and schematic cross-sectional view of an optoelectronic device of the first embodiment. Figure 2 is an exemplary and schematic cross-sectional view of a product during the manufacturing process of the first embodiment of an optoelectronic semiconductor device. Figure 3 is an exemplary and schematic cross-sectional view of the product in the intermediate manufacturing process of the optical semiconductor device of the first embodiment, at a stage later than that shown in Figure 2. Figure 4 is an exemplary and schematic cross-sectional view of the product in the intermediate stages of the manufacturing process of the first embodiment of the optical semiconductor device, at a stage later than that shown in Figure 3. Figure 5 is an exemplary and schematic cross-sectional view of the product in the manufacturing process of the first embodiment of the optoelectronic device at a stage later than that shown in Figure 4. Figure 6 is an exemplary and schematic cross-sectional view of the product in the intermediate manufacturing process of the first embodiment of the optoelectronic device, at a stage later than that shown in Figure 5. Figure 7 is an exemplary and schematic cross-sectional view of the product in the manufacturing process of the first embodiment of the optoelectronic device at a stage later than that shown in Figure 6. Figure 8 is an exemplary and schematic plan view of the product at the same stage as Figure 4 in the manufacturing process of the optical semiconductor device of the first embodiment. Figure 9 is an exemplary and schematic plan view of a part of the optical semiconductor device of the first embodiment. Figure 10 is an exemplary and schematic cross-sectional view of a part of the optical semiconductor device of the second embodiment. Figure 11 is a schematic diagram illustrating the effects of the configuration of the optoelectronic semiconductor device according to the second embodiment. Figure 12 is an exemplary and schematic plan view of a part of the optical semiconductor device of the third embodiment. Figure 13 is an exemplary and schematic plan view of a part of the optical semiconductor device of the fourth embodiment. Figure 14 is an exemplary and schematic plan view of the optical semiconductor device of the fifth embodiment. Figure 15 is an exemplary and schematic plan view of a pillar included in the optical semiconductor device of the sixth embodiment. Figure 16 is an exemplary and schematic plan view of a pillar included in the optical semiconductor device of the seventh embodiment.

The following describes exemplary embodiments of the present invention. The configurations of the embodiments shown below, as well as the actions and results (effects) brought about by them, are examples only. The present invention can also be realized by configurations other than those disclosed in the following embodiments. Furthermore, according to the present invention, it is possible to obtain at least one of the various effects (including derived effects) that can be obtained by the configuration.

The following embodiments share similar configurations. Therefore, the configurations of each embodiment yield similar functions and effects based on those similar configurations. Furthermore, similar components are denoted by the same reference numerals, and redundant explanations may be omitted.

In this specification, ordinal numbers are assigned for convenience to distinguish directions, intervals, parts, etc., and do not indicate priority or order.

In each figure, the X direction is represented by arrow X, the Y direction by arrow Y, and the Z direction by arrow Z. The X, Y, and Z directions intersect and are also orthogonal to each other. Furthermore, below, the X direction will be referred to as the longitudinal direction or extension direction, the Y direction as the short direction or width direction, and the Z direction as the stacking direction or height direction.

Furthermore, each diagram is a schematic representation for explanatory purposes, and the vertical and horizontal scales and proportions may not necessarily match those of the actual objects.

[First Embodiment]
Figure 1 is a cross-sectional view of the optoelectronic device 100A (100) of the first embodiment. As shown in Figure 1, the optoelectronic device 100 comprises a substrate 10 and a laminated portion 20 made of semiconductor material or the like, which is laminated on the substrate 10.

The substrate 10 has a substantially constant thickness in the Z direction and extends intersecting the Z direction. The substrate 10 has two surfaces: surface 10a and surface 10b. Surface 10a faces and intersects the Z direction. Surface 10a is a (100) plane according to Miller indices. Surface 10b is located on the opposite side of surface 10a, faces the opposite direction of the Z direction, and intersects the Z direction. The substrate 10 is made of, for example, n-InP. The Z direction is the crystal orientation [100] direction and is an example of a first direction. Surface 10a is an example of a principal plane.

The laminated portion 20 includes pillars 21, a sacrificial layer 22, a first semiconductor layer 23, a second semiconductor layer 24, a third semiconductor layer 25, and pillars 26.

Figures 2-7 are cross-sectional views of the laminated material at each manufacturing step of the optoelectronic device 100.

As shown in Figure 2, first, a sacrificial layer 22 is laminated on the surface 10a of the substrate 10 in the Z direction with a substantially constant thickness. The sacrificial layer 22 is made of, for example, GaInAsP.

Next, a protective layer and a resist (neither shown) are applied to the sacrificial layer 22 of the laminate (product) shown in Figure 2 to form a pattern in the resist. Selective etching is then performed according to the resist pattern to selectively remove the sacrificial layer 22, as shown in Figure 3. At this time, the substrate 10 may be partially removed at position P1 to ensure that no sacrificial layer 22 remains.

Next, as shown in Figure 4, at position P1, where the sacrificial layer 22 has been removed, pillars 21 and 26 are formed by crystal growth. The pillars 21 and 26 are made of the same material as the substrate 10, i.e., in this embodiment, n-InP as an example. The pillars 21 and 26 and the sacrificial layer 22 are arranged adjacent to each other in a direction intersecting the Z direction. Note that the pillars 21 and 26 and the sacrificial layer 22 are made of materials with different etching rates for a predetermined etching agent. This will be described in detail later. Also, the pillars 21 and 26 may protrude from the sacrificial layer 22 in the Z direction. The pillars 21 and 26 are examples of the first layer, and the sacrificial layer 22 is an example of the second layer. Furthermore, the process shown in Figures 2-4 is an example of the first process.

Next, as shown in Figure 5, the first semiconductor layer 23, the second semiconductor layer 24, and the third semiconductor layer 25 are stacked in this order in the Z direction on the pillars 21, 26 and the sacrificial layer 22 shown in Figure 4. As is clear from Figure 5, the pillars 21, 26 and the sacrificial layer 22 support the stacked portion 20 provided on the substrate 10. The stacked portion 20 is located on the opposite side of the substrate 10 from the pillars 21, 26, and includes the first semiconductor layer 23, the second semiconductor layer 24, and the third semiconductor layer 25, etc. A laminate including the substrate 10 and the stacked portion 20 is an example of a base.

The first semiconductor layer 23 is made of the same material as the substrate 10, that is, in this embodiment, n-InP as an example.

The second semiconductor layer 24 is made from a material containing, for example, InGaAsP.

Furthermore, the third semiconductor layer 25 is made of, for example, p-InP.

Next, by selective etching of the laminate shown in Figure 5, that is, the laminate including the substrate 10 and the laminated portion 20, the first semiconductor layer 23, the second semiconductor layer 24, and the third semiconductor layer 25 are removed from the product of Figure 5 at position P2, from the end face 20a in the Z direction. This forms a trench T that opens in the Z direction at the end face 20a and has a bottom surface 20b.

In this embodiment, two trenches T are formed, creating a mesa 30 between them. The mesa 30 protrudes in the Z direction from the bottom surface 20b of the trenches T provided in the laminated portion 20. The bottom surface 20b intersects with the Z direction. Furthermore, the mesa 30 extends in the X direction, in other words, along the bottom surface 20b. The bottom surface 20b is an example of a base surface.

In the mesa 30, the first semiconductor layer 23 functions as the lower cladding layer 31, the second semiconductor layer 24 functions as the waveguide layer 32 (core layer), and the third semiconductor layer 25 functions as the upper cladding layer 33. The process shown in Figures 5 and 6 is an example of the second process.

Next, as shown in Figure 7, an insulating layer 101 is formed to cover the laminated portion 20, and a heater layer 102 for heating the waveguide layer 32 of the mesa 30, and a conductor 103 for conducting electricity through the heater layer 102 are formed. The heater layer 102 is located at a position away from the waveguide layer 32 in the Z direction. The heater layer 102 is, for example, an electric thermal resistor, which generates heat in response to the supply of power via the conductor 103, and heats the waveguide layer 32 of the mesa 30. The refractive index of the waveguide layer 32 changes according to its temperature. The conductor 103 is provided on the insulating layer 101 along the end face 20a, the side surface of the trench T, and the bottom surface 20b. The process of forming the heater layer 102 is an example of the third process.

Furthermore, as shown in Figure 7, the laminated portion 20 is provided with an opening 20c in the Z direction in the bottom surface 20b and the insulating layer 101 covering the bottom surface 20b, by selective etching. The opening 20c is provided so as to reach at least the sacrificial layer 22S (22) located between the substrate 10 and the mesa 30. The depth of the opening 20c only needs to be sufficient to reach at least the sacrificial layer 22S; its bottom may be located within the sacrificial layer 22S, or it may extend slightly beyond the sacrificial layer 22S in the opposite Z direction to reach the substrate 10.

Next, in the laminate shown in Figure 7, an etching agent is applied to the sacrificial layer 22S through the opening 20c to remove the sacrificial layer 22S. In this case, the etching is, for example, wet etching. This results in the optoelectronic device 100 shown in Figure 1, which has a space S provided where the sacrificial layer 22S has been removed. With this configuration and manufacturing method, in this embodiment, in the heating section of the mesa 30 including the waveguide layer 32, a pillar 21 and the space S adjacent to the pillar 21 are interposed between the substrate 10 and the mesa 30. In other words, the pillar 21 overlaps, at least partially, with the heating section of the mesa 30 including the heater layer 102 in the Z direction. Therefore, the pillar 21 supports the mesa 30 and serves as a heat transfer path from the heater layer 102 to the mesa 30 to the substrate 10. In other words, in this embodiment, the provision of space S limits the heat transfer path from the heater layer 102 to the substrate 10 to only the pillar 21, thereby increasing the heating efficiency of the heater layer 102. As shown in Figure 1, in the optoelectronic device 100 with the sacrificial layer 22S removed, the opening 20c and space S become connected. The step of removing the sacrificial layer 22S, shown in Figures 7 and 1, is an example of the fourth step.

As the etching agent used to remove the sacrificial layer 22S, an etching agent is used that has a sufficiently low etching rate for each material constituting the substrate 10, pillars 21 and 26, and mesa 30, and a sufficiently high etching rate for the sacrificial layer 22.

Furthermore, as is clear from Figures 1 and 7, the pillar 26 separates the sacrificial layer 22S (space S) where the etching agent acts, from the sacrificial layer 22R where the etching agent does not act, via the opening 20c. That is, in this embodiment, the presence of the pillar 26 ensures that the sacrificial layer 22R remains in the optoelectronic device 100, as shown in Figure 1. As is clear from the manufacturing process described above, the sacrificial layer 22R is made of the same material as the sacrificial layer 22S and extends in a direction intersecting the Z-direction on the opposite side of the pillar 26 from the sacrificial layer 22S. The pillar 26 is an example of a partition, and the sacrificial layer 22R is an example of a remaining layer.

However, in the optoelectronic device 100 manufactured through the above-described manufacturing process, depending on the conditions during crystal growth of pillars 21 and 26 (see Figure 4), it may become difficult to ensure the flatness of each semiconductor layer, including the waveguide of the optoelectronic device 100. For example, it may become difficult to obtain the required optical properties of the optoelectronic device 100.

Figure 8 is a plan view of a part of the laminate (product) of Figure 4. The inventors diligently studied the influence of the crystal growth of pillars 21 and 26 on the flatness, and found that, as shown in Figure 8, when the sides 21a and 26a of pillars 21 and 26 that face in a direction intersecting the Z direction extend in a direction that intersects the Z direction and is non-parallel to the crystal orientation [0-11] direction (Y direction), the required shape accuracy and flatness of pillars 21 and 26 can be obtained, and consequently, the required flatness can be ensured in each semiconductor layer including the waveguide of the optoelectronic device 100A. It is presumed that this phenomenon correlates with the crystal orientation direction when the wafer that becomes the substrate 10 and each semiconductor layer laminated on the substrate 10 have a zincblende type structure. In the example shown in Figure 8, when viewed in the opposite direction to the Z direction, the extension directions De of the sides 21a and 26a are both oriented in directions non-parallel to the [0-11] direction (Y direction), and the absolute value of the angular difference between the extension direction De and the [0-11] direction (provided that the smaller of the two is less than or equal to a right angle) is approximately 45° or approximately 90°. However, the absolute value of this angular difference is not limited to 45° or 90°, and any value greater than 0° is acceptable. According to the inventors' experimental research, it has been found that the absolute value of this angular difference is preferably 5° or more, and more preferably between 30° and 60°. Furthermore, in areas where the accuracy of the shape and flatness do not affect the optical properties, such as positions that do not overlap with the mesa 30 in the Z direction, the extension directions De of the sides 21a and 26a do not necessarily have to satisfy the above conditions. In other words, the sides 21a and 26a of pillars 21 and 26, which face a direction intersecting the Z direction, only need to extend in a direction intersecting the Z direction and non-parallel to the crystal orientation [0-11] direction, at least in the heated section of the mesa 30 by the heater layer 102. The extension direction De of sides 21a and 26a is an example of a second direction. Furthermore, side 21a is an example of a first side, and side 26a is an example of a second side.

Figure 9 is a plan view of the optoelectronic device 100A (100). As shown in Figure 9, the mesa 30 extends in the X direction. The optoelectronic device 100 comprises a plurality of conductors 103 spaced apart in the X direction, and the heater layer 102 extends in the X direction along the mesa 30 between the plurality of conductors 103.

Furthermore, the optoelectronic device 100 is equipped with a plurality of pillars 21. The plurality of pillars 21 are spaced apart from each other in the X direction, i.e., the direction in which the mesa 30 extends. A space S is formed between the plurality of pillars 21. Therefore, the mesa 30 extends linearly in the section overlapping with the plurality of pillars 21 and the space S in the Z direction. With this configuration, even when the heating section of the mesa 30 by the heater layer 102 is relatively long, the plurality of spaces S suppress the decrease in heating efficiency by the heater layer 102, while the plurality of pillars 21 make it easier to ensure the required rigidity and strength of the mesa 30.

Furthermore, as shown in Figure 9, the optoelectronic device 100A is provided with multiple apertures 20c. These multiple apertures 20c are positioned such that, when viewed in opposite directions in the Z-direction, the mesa 30 is located between them. This configuration allows the etching agent to act on the sacrificial layer 22S located between the mesa 30 and the substrate 10 from both sides of the mesa 30, resulting in the more rapid removal of the sacrificial layer 22S. Note that the size, position, shape, and other specifications of the apertures 20c are not limited to the example in Figure 9 and can be varied.

As described above, the structure and method of this embodiment provide the advantage of more easily or reliably ensuring the required flatness in, for example, the pillars 21 and 26, the laminated portion 20 stacked on the pillars 21 and 26, and the optoelectronic device 100 including the laminated portion 20.

[Second Embodiment]
Figure 10 is a cross-sectional view of the optical semiconductor device 100B (100) of the second embodiment. This embodiment also has the same configuration as the optical semiconductor device 100A of the first embodiment. Therefore, the same effects as the first embodiment can be obtained with this embodiment as well.

As shown in Figure 10, in this embodiment, a plurality of DBR blocks 41-44 (40) (DBR: distributed bragg reflector) are provided within the mesa 30 of the optoelectronic device 100B at positions opposite to the substrate 10 relative to the waveguide layer 32. Each DBR block 40 is made of a material including, for example, p-InGaAsP, and has a distributed reflection type diffraction grating. The plurality of DBR blocks 40 have the same length in the X direction, are aligned in the X direction along the waveguide layer 32, and are arranged at a constant interval I1 in the X direction. The X direction is the direction of extension of the mesa 30. The interval I1 is an example of a first interval.

Furthermore, pillars 21 and spaces S are alternately arranged between the substrate 10 and the mesa 30 along the X direction. Multiple pillars 21 are arranged at a constant interval I2 in the X direction. Interval I2 is different from interval I1. Interval I2 is an example of a second interval.

Figure 11 is an explanatory diagram showing the relative positions in the X direction where the pillars 21 are positioned with respect to each DBR block 40. As described above, the pillars 21 serve as paths through which heat is transferred from the mesa 30 to the substrate 10. Therefore, in each DBR block 40, the temperature is lowest at the position closest to the pillar 21, i.e., positions p1 to p5 (see Figure 10) that overlap with the pillar 21 in the Z direction, and the temperature increases as the distance in the X direction from these positions p1 to p5 increases. In such a situation, if a temperature distribution occurs in each DBR block 40 where the lowest temperature is at the same relative position in the X direction, it may become difficult to obtain the required optical characteristics at a specific wavelength. This corresponds to the case in Figure 11 where positions p1 to p5 overlap at the same position. Furthermore, the relative position in the X direction can be expressed as x/L, for example, if L is the distance in the X direction between end 40a and end 40b in the X direction, and x is the distance in the X direction between end 40b and each position p1 to p5.

Therefore, in this embodiment, by making the spacing I1 and spacing I2 different, in Figure 11, positions p1 to p5 do not overlap, that is, when viewed in the opposite direction of the Z direction, each pillar 21 does not overlap with the same relative position in the respective X direction of the DBR block 40. This makes it possible to suppress the loss of the required optical characteristics for a specific wavelength. Note that the arrangement in which each pillar 21 does not overlap with the same relative position in the respective X direction of the DBR block 40 when viewed in the opposite direction of the Z direction is not limited to the examples in Figures 10 and 11.

[Third Embodiment]
Figure 12 is a plan view of the optical semiconductor device 100C (100) of the third embodiment. This embodiment also has the same configuration as the optical semiconductor device 100A of the first embodiment. Therefore, the same effects as the first embodiment can be obtained with this embodiment as well.

As shown in Figure 12, in this embodiment, the end 21b of pillar 21C is connected to and integrated with pillar 26. This configuration offers the advantage of increasing the support rigidity of the mesa 30 and laminated section 20 by pillars 21 and 26. The specifications of pillar 21, such as length, thickness, position, and shape, can be modified as appropriate.

[Fourth Embodiment]
Figure 13 is a plan view of the optical semiconductor device 100D (100) of the fourth embodiment. This embodiment also has the same configuration as the optical semiconductor device 100A of the first embodiment. Therefore, the same effects as the first embodiment can be obtained with this embodiment as well.

As shown in Figure 13, in this embodiment, the conductor 103 has a connection portion 103a with respect to the heater layer 102, a pad portion 103b connected to the outer conductor, and a wiring portion 103c between the connection portion 103a and the pad portion 103b. Furthermore, the pillar 21D is exposed through the opening 20c and divides the opening 20c in the X direction.

Furthermore, the wiring section 103c is provided so as to cover the Z-direction end face of the pillar 21D. With this configuration, the wiring section 103c of the conductor 103 can be provided using the pillar 21D; in other words, the conductor 103 can be routed. This provides the effect of increasing the degree of freedom in the layout of the conductor 103 and, consequently, the heater layer 102.

[Fifth Embodiment]
Figure 14 is a plan view of the optical semiconductor device 100E (100) of the fifth embodiment.

As shown in Figure 14, the optoelectronic device 100E of this embodiment comprises an SG-DBR section 110 (SG-DBR: sampled-grating DBR), a phase adjustment section 120, a connection section 140, and a ring resonator 150. The optoelectronic device 100E is an example of a tunable laser device having a tunable laser resonator utilizing the Vernier effect.

The connection section 140 is branched by a branching section, such as a 1x2 MMI coupler, which is optically connected to the gain section 130, and each section comprises two bent mesas 30 in a plan view in opposite directions in the Z direction. The waveguide layer 32 (see Figure 1) of each mesa 30 is optically connected to the annular waveguide layer 32 of the ring resonator 150 at the coupling section C by a 2x2 MMI coupler or the like.

The SG-DBR section 110 has a waveguide layer 32 and a heater layer 102.

The phase adjustment unit 120 is provided in a part of the connection unit 140. The phase adjustment unit 120 has a heater layer 102.

The ring resonator 150 has a reflection spectral characteristic with a comb-shaped peak having a different period than the SG-DBR section 110, and constitutes the reflection section of the laser resonator.

Furthermore, the ring resonator 150 has a heater layer 102. Heating the heater layer 102 changes the refractive index of the waveguide layer 32, thereby shifting the comb-shaped reflection peak in the frequency axis direction.

Furthermore, in the heating sections of the SG-DBR section 110, the phase adjustment section 120, and the mesa 30 of the ring resonator 150, pillars 21 are provided between the mesa 30 and the substrate 10. Space S (not shown in Figure 14; see Figure 1, etc.) is provided adjacent to the pillars 21, around the pillars 21, or between multiple pillars 21. In this embodiment as well, the side surface 21a of each pillar 21 extends in a direction intersecting the Z direction and non-parallel to the crystal orientation [0-11] direction. Therefore, the same effects as in the first embodiment can be obtained with this embodiment.

In the ring resonator 150, pillars 21 are provided on the curved mesa 30. The effect of the pillars 21 described above is obtained not only on the straight-extending portion of the mesa 30 but also on the curved-extending portion.

[Sixth and seventh embodiments]
Figure 15 is a plan view of pillar 21F (21) provided in the optical semiconductor device of the sixth embodiment, and Figure 16 is a plan view of pillar 21G (21) provided in the optical semiconductor device of the seventh embodiment.

As shown in Figures 15 and 16, in these embodiments as well, the side surface 21a of the pillar 21 extends in a direction intersecting the Z direction and non-parallel to the crystal orientation [0-11] direction. Therefore, the same effects as in the first embodiment can be obtained in these embodiments as well. Thus, the pillar 21 is not limited to a linearly extending shape, but can be implemented in various shapes and configurations.

The above embodiments of the present invention have been illustrated, but these embodiments are merely examples and are not intended to limit the scope of the invention. The above embodiments can be implemented in various other forms, and various omissions, substitutions, combinations, and modifications can be made without departing from the spirit of the invention. Furthermore, each configuration, shape, and other specifications (structure, type, orientation, model, size, length, width, thickness, height, number, arrangement, position, material, etc.) can be modified as appropriate.

10... Circuit board (base)
10a...Surface 10b...Surface 20...Laminated section (base)
20a...End face 20b...Bottom face (base surface)
20c...Opening 21, 21C, 21D, 21F, 21G...Pillar (first layer)
21a... Side (first side)
21b...End section 22...Sacrificial layer (second layer)
22S... Sacrificial layer 22R... Sacrificial layer (surviving layer)
23...First semiconductor layer 24...Second semiconductor layer 25...Third semiconductor layer 26...Pillar (partition, first layer)
26a...Side (second side)
30...Mesa 31...Lower cladding layer 32...Waveguide layer 33...Upper cladding layer 40, 41-44...DBR block 40a...End 40b...End 100, 100A-100E...Optical equipment 101...Insulating layer 102...Heater layer 103...Conductor 103a...Connection part 103b...Pad part 103c...Wiring part 110...SG-DBR part 120...Phase adjustment part 130...Gain part 140...Connection part 150...Ring resonator C...Coupling part De...Extension direction (second direction)
I1...Interval (first interval)
I2...Interval (second interval)
P1-P2...Positions p1-p5...Positions S...Space T...Trench X...Direction (Mesa extension direction)
Y...direction Z...direction (first direction)

Claims (14)

A base having a substrate and a base plane intersecting a first direction which is the crystal orientation [100] direction,
A mesa projecting from the base surface in the first direction and extending along the base surface,
At the intermediate position of the mesa in the first direction, a waveguide layer extending along the base surface,
A heater layer is provided in the mesa at a position away from the waveguide layer in the first direction, and generates heat when power is supplied.
Between the substrate and the mesa, a pillar is provided such that it at least partially overlaps the section of the mesa heated by the heater layer in the first direction, and has a first surface that faces a direction intersecting the first direction and extends in a second direction that intersects the first direction and is non-parallel to the crystal orientation [0-11] direction,
A partition wall made of the same material as the pillar is adjacent to a space provided between the substrate and the mesa, and is adjacent to the space provided adjacent to the pillar.
A residual layer made of a material that extends in a direction intersecting the first direction on the opposite side of the space from the partition wall, and is etched with a predetermined etchant that has a sufficiently low etching rate for the substrate, the pillar, and the mesa;
Equipped with,
The partition wall has a second side surface that is oriented in a direction intersecting the first direction in at least the section overlapping the mesa and the first direction, and that extends in the second direction. A base having a substrate and a base plane intersecting a first direction which is the crystal orientation [100] direction,
A mesa projecting from the base surface in the first direction and extending along the base surface,
At the intermediate position of the mesa in the first direction, a waveguide layer extending along the base surface,
A heater layer is provided in the mesa at a position away from the waveguide layer in the first direction, and generates heat when power is supplied.
Between the substrate and the mesa, a pillar is provided such that it at least partially overlaps the section of the mesa heated by the heater layer in the first direction, and has a first surface that faces a direction intersecting the first direction and extends in a second direction that intersects the first direction and is non-parallel to the crystal orientation [0-11] direction,
A space provided between the substrate and the mesa, adjacent to the space adjacent to the pillar, and comprising a partition wall made of the same material as the pillar,
A residual layer made of a material that extends in a direction intersecting the first direction on the opposite side of the space from the partition wall, and is etched with a predetermined etchant that has a sufficiently low etching rate for the substrate, the pillar, and the mesa;
Equipped with ,
The waveguide layer extends in the [011] direction ,
The partition wall has a second side surface that is oriented in a direction intersecting the first direction in at least the section overlapping the mesa and the first direction, and that extends in the second direction . The optical semiconductor device according to claim 1 or 2 , wherein the partition wall and the pillar are connected. The semiconductor layer constituting the substrate, the pillar, and the mesa has a zincblende-type structure, as described in any one of claims 1 to 3 . The optoelectronic device according to any one of claims 1 to 4 , wherein the cladding layer of the substrate, the pillar, and the mesa is made of InP. The optical semiconductor device according to any one of claims 1 to 5 , wherein the pillar comprises a plurality of pillars separated by the space. The optical semiconductor device according to claim 6 , wherein the plurality of pillars are a plurality of pillars that are separated from each other in the direction of extension of the mesa. The optical semiconductor device according to any one of claims 1 to 7 , wherein the base surface is provided with an opening that is open in the first direction and connected to the space. The optical semiconductor device according to claim 8 , wherein a plurality of openings are provided as the aforementioned openings. The optical semiconductor device according to claim 9 , wherein the plurality of apertures are provided such that the mesa is located between the plurality of apertures when viewed in the opposite direction to the first direction. The aforementioned pillar comprises a plurality of pillars separated by the space,
Along the waveguide layer, there are a plurality of DBR blocks of substantially the same length in the direction of extension, arranged at first intervals in the direction of extension of the mesa,
The optical semiconductor device according to any one of claims 1 to 10 , wherein the pillars are arranged so as not to overlap with the same relative positions in the respective extension directions of the DBR blocks when viewed in the opposite direction to the first direction. The optical semiconductor device according to claim 11 , wherein the plurality of pillars are arranged in the extending direction at a second interval different from the first interval. The optoelectronic semiconductor device according to any one of claims 1 to 12 , wherein the mesa has a portion that extends linearly in a section that overlaps with the pillar and the space in the first direction. The optoelectronic semiconductor device according to any one of claims 1 to 13 , wherein the mesa has a curved portion that extends in a section overlapping with the pillar and the space in the first direction.