JPS5810853B2 - Method for measuring deep impurity levels in semiconductors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on the temperature dependence of the transient phenomenon of semiconductor junction capacitance when a bias pulse is applied between the junctions of semiconductors such as a semiconductor having a PN junction and a MOS diode without a PN junction. This article relates to a method for measuring deep impurity levels in semiconductors.Deep impurity levels in semiconductors have a large impact on the characteristics, reliability, deterioration, etc. of semiconductors.

In recent years, with the increasing density of semiconductor integrated circuits, ion implantation,
It is necessary to easily and accurately measure the electrical properties of various defects that occur during the semiconductor manufacturing process due to doping with thermal neutrons, etc., or of defects that exist in the crystal itself, even down to the dynamic properties, with extremely high sensitivity and ease. It has arisen.

A method for measuring deep impurity levels in semiconductors (hereinafter referred to as DLT) proposed by Lang et al.
It is abbreviated as S measurement method.

). In this method, a bias pulse as shown in Figure 1a is applied to the semiconductor to fill the semiconductor with majority carriers, and as the bias pulse falls, a transient change in the semiconductor junction capacitance as shown in Figure 1A is output. is obtained by a capacitance meter, and the output has a pulse width t1. which is called a double boxcar as shown in FIG. 1C. The signal is multiplied by a weighting function signal with narrow pulse interval t2 and a deep impurity level signal, which is hereinafter abbreviated as DLTS signal.

).

In the figure, Vo is the voltage of the bias pulse, VR
is the reverse bias voltage, T1 is the bias pulse application time (pulse width), C1 is the junction capacitance when applying the bias pulse, Co is the steady state junction capacitance achieved after applying the reverse bias voltage, and Co is from Vo to vR. The junction capacitance immediately after applying the reverse bias, C84, is the lowest junction capacitance obtained by the response characteristics of the capacitance meter relay.

This Lang-based DLTS measurement method has advantages over other conventional methods, such as detection sensitivity, measurement speed, ease of analysis, and the ability to separate and measure two or more deep impurity levels. It is considered to be a method of measurement.

However, since Lang's DLTS measurement method uses a double boxcar, the device becomes extremely hot, and the S/N ratio of the DLTS signal is not sufficient.

In response to this, a DLTS measurement method using a lock-in amplifier was proposed by Kimerling.

This method uses a weighting function signal in the form of a rectangular wave that rises at the rising edge of the bias pulse, with one period of the bias pulse as shown in FIG. This is a method of multiplying the transient change output of the semiconductor junction capacitance as shown by this weighting function signal and obtaining the DLTS signal output by the product.

Such a measurement method using quinoling requires a relatively complex device, and the S/N ratio of the DLTS signal output is also improved.

However, this method requires procedures such as determining constants in order to obtain the data (trap level, etc.) required from the obtained DLTS signal, which complicates data analysis and affects the response of the capacitance meter. There are drawbacks such as errors being mixed in and separation of these errors not being easy.

As described above, all conventional measurement methods have advantages and disadvantages.

An object of the present invention is to provide a DLTS measurement method that combines the advantages of the conventional Lang and Chimering measurement methods.

The DLTS measurement method of the present invention uses a weighting function signal as shown in FIG. 1e, multiplies the transient change output of the semiconductor junction capacitance as shown in FIG. It is used to obtain signal output.

The weighting function signal used in the present invention is based on the application time T1 of the bias pulse and the expected response time T1 of the capacitance meter.
d continuously for the sum of time (T1 + Td), then rises after the scheduled response time of the capacitance meter and changes into a rectangular wave, and the period from after the scheduled response time of the capacitance meter until the rise of the next bias pulse is 1. The shape changes as a cycle.

As mentioned above, the DLTS signal output is represented by the product of the transient change output of the semiconductor junction capacitance shown in FIG. 1 and the weighting function signal, so the DLTS signal output signal output in FIG. c), DLTS signal output signal output by the chimering measurement method bXd in Figure 2), DLTS signal output signal output by the measurement method of the present invention b×e in Figure 3
) is calculated as follows.

Here, σn is the electron capture cross section, ■n is the thermal average velocity of electrons, No is the conduction band effective density of states, Eo is the energy in the conduction band, Et is the energy level of the trap, K is Boltzmann constant, H is the temperature expressed in absolute temperature, ΔC0 is (C∞−C0).

Here, the above-mentioned ■1. V2. Let's consider V3.

Vl shown in equation (1) is excellent in that the equation is simple and data analysis is easy, but as mentioned above, the equipment is extremely expensive and the S/N ratio of the V1 value is not sufficient.

V2 shown in formula (2) is defined by C1, T1. Including C∞, etc., making data analysis complicated.

Furthermore, due to the response characteristics of a capacitance meter, using the capacitance waveform C0 causes an error, which is not easy to remove.

On the other hand, V3 according to the method of the present invention shown in equation (3) uses a weighting function signal that is set to zero during the (T1+Td) time, so the equation is extremely simple and data analysis is easy. be.

Also, similar to lock-in up, improvements in the S/N ratio are taken advantage of.

From equation (3) showing V3, D with Td/T as a parameter
The function of LTS signal output V0 and T/τ is shown in FIG. 2.

As is clear from the figure, V0 takes a maximum value at a certain T/τ.

Also, as Td/T increases, T/ takes an extremely thick value.
τ becomes smaller and the extremely thick value decreases.

For example, if we change τ under the condition that Td/T is constant,
Correspondingly, V.

τ at which Vo becomes extremely thick changes, and the temperature at which Vo becomes extremely thick is determined for each τ, and the temperature dependence of τ is obtained.

The trap energy level Et can be evaluated based on the value of τ.

Furthermore, it is possible to distinguish between a majority carrier trap and a minority carrier trap depending on whether ΔC0=C∞−C0 is positive or negative.

FIG. 3 shows an example of a measuring device for carrying out the measuring method of the present invention.

In the figure, 1 is a semiconductor sample placed in a cryostat 2 that changes the temperature from liquid nitrogen temperature to room temperature; 3
4 is a capacitance meter that measures the junction capacitance of semiconductor 1;
5 is an amplifier that amplifies the output of the capacitance meter 3; 6 is a first circuit through which the output of the amplifier 5 directly passes;
7 is a second electric path through which the output of the amplifier 5 is inverted by an inverter 8, and 9 is an analog switch that selectively opens and closes both paths 6 and 7 to form a weighting function signal.
10 is a low-pass filter that forms a DLTS signal obtained by multiplying the output of the capacitance meter 3 by a weighting function signal;
11 is an XY recorder.

This XY recorder 11 receives the DLTS signal from the low-pass filter 10 and the temperature signal from the temperature sensor 12 in the cryostat 2 as input, and records changes in the DLTS signal with respect to temperature changes.

13 is a clock pulse generator, and 14 is a timing controller.

The timing controller 14 controls the timing at which the bias pulse generator 4 generates bias pulses based on the clock pulse, and also outputs a timing signal Ta for opening and closing the analog switch 9 as shown in FIGS. 4B and 4C. It is designed to produce Tb.

The output of the capacitance meter 3 is the timing signal Ta
Then, the inverted output of the capacitance meter 3 is applied to the low-pass filter 10 for 772 hours according to the timing signal Tb.

If the period of the clock pulse is Tc, then T=200Tc and Td=Tc (100-D) are selected in this embodiment.

Here, D is an integer varying from 1 to 99.

FIG. 4 shows another embodiment of a measuring device for carrying out the measuring method of the present invention.

In the figure, reference numeral 15 denotes a control logic that receives a clock pulse as an input and generates a control pulse for generating a bias pulse and a weighting function signal shown in FIG. 1e.

In this control logic 15, if the period of the clock pulse is Tc, the integration period T and the expected response time Td of the capacitance meter 3 are T=nTc, Td=Tc(
100-D).

Here, for example, n=200, and D is an integer varying in the range of 1 to 99.

Reference numeral 16 denotes a DC bias control circuit which receives control pulses from the control logic 15 and forms bias pulses, so that the bias voltage can be changed as appropriate.

17 is D by multiplying the output of the capacitance meter 3 by the weighting function signal given from the control logic 15.
A signal processor that forms LTS signals.

Note that 1 is a semiconductor as a sample, 2 is a low temperature bath, 3 is a capacitance meter, 11 is an XY recorder, and 12 is a temperature sensor.

A thermocouple is used as the temperature sensor 12, and its electromotive force is applied to the X axis of the XY recorder 11.

When actually performing measurements, it is desirable to keep Td/T constant so that the shape of the output does not change even if T is changed.

For this purpose, T and Td are designed to vary in proportion to Tc.

Td=5ms, Td/T=1/20. By setting the condition of D=90, it is possible to set τ of at least τ=46.1 ms or more, and Td/T=1/2. If D=0, the shortest τ=9
．． 5ms can be set.

FIG. 6 shows the results of an experiment in which the measurement principle of the present invention was applied to a silicon P+N diode irradiated with neutrons.

As is clear from the figure, E1°E2. Three distinct peak values of E3 were observed.

In this case, the reverse bias voltage was 16 sq. under the condition of Td/T=1/200.

Furthermore, by changing Td/T, E1. E2. By obtaining the temperature dependence characteristics of E3, a characteristic diagram of the temperature dependence of τ regarding the electron trap shown in FIG. 7 was obtained.

As a result, E1. E2. The trap energy levels of E3 were estimated to be 0.16 eV, 0.20 eV, and 0.44 eV.

As explained above, in the DLTS measurement method according to the present invention, the weighting function signal is set to zero for the sum of the bias pulse application time and the expected response time of the capacitance meter, and then rises after the expected response time of the capacitance meter. Since a signal that changes in the form of a rectangular wave is used, the S/N ratio of the DLTS signal is improved, measurement accuracy is improved, data analysis is facilitated, and there is an advantage that response errors of the capacitance meter are not mixed in.

Furthermore, according to the method of the present invention, a measuring device can be provided at a significantly lower cost than in the past, making it easier for users to purchase it, making it possible to popularize this type of measuring method, and improving the yield of semiconductor products. can be done.

[Brief explanation of drawings]

Figures 1 a to e are waveform diagrams for comparing the differences between the method of the present invention and the conventional method; Figure 2 is a diagram showing the relationship between the DLTS signal and T/τ using Td/T as a parameter; FIG. 3 is a block diagram showing an embodiment of an apparatus for carrying out the method of the present invention, and FIGS. 4A and 4B. C is a waveform diagram showing the output of the capacitance meter and the opening/closing timing of the analog switch in the device shown in FIG. 3, FIG. 5 is a block diagram showing another embodiment of the device implementing the method of the present invention, and FIG. FIG. 7, which is a diagram showing an example of a change in the DLTS signal with respect to a temperature change, is a characteristic diagram of temperature dependence on τ. T1: Application time of bias pulse, Td: Expected response time of capacitance meter, 1: Semiconductor, 2
...Cryogenic chamber, 3...Capacitance meter, 4...
- Bias pulse generator, 9...analog switch for weighting function signal formation, 10...low-pass filter for integration.

Claims (1)

[Claims] 1 Apply a bias pulse to the semiconductor, measure the transient change in semiconductor junction capacitance that occurs with the fall of this bias pulse with a capacitance meter, and multiply the transient change output obtained from the capacitance meter by a weighting function signal to calculate the deep In the method of measuring a deep impurity level of a semiconductor by obtaining an impurity level signal, the weighting function signal is set to zero for the sum of the application time of the bias pulse and the expected response time of the capacitance meter. A method for measuring deep impurity levels in semiconductors, characterized by using a signal that rises after a scheduled response time and changes in a rectangular waveform.