JPS5811632B2 - daily rhythm ensouchi - Google Patents

Description

Detailed Description of the Invention The present invention fixes the state of a counter circuit in an automatic rhythm performance device to one or more divided measures by adding a command signal when all playable measures are divided into a plurality of measures. The present invention provides an automatic rhythm playing device that can maintain the state until the command signal is released and repeatedly play only the -measure or a plurality of measures.

To explain further, for example, a final stage frequency divider in the counter circuit is equipped with a set and reset terminal, and by supplying a command signal to the set terminal or reset terminal, the final stage frequency divider is set to the current state. It is fixed to the performance state, and the currently played part of all the playable measures is fixed.

This invention relates to an automatic rhythm playing device that can change the rhythm by repeatedly playing only the first two measures or the second half.

The present invention will be explained below with reference to the drawings.

In FIG. 1, 1 is a clock pulse generator that generates a clock pulse corresponding to the beat of the smallest rhythm unit, and 2 is a counter circuit, which is a frequency divider C1 that sequentially divides the clock pulses of the clock pulse generator 1. , C2... are connected in series, and the final stage branching device C
A set terminal S and a reset terminal R are provided at n+1.

3 is each frequency divider C1, C2, . . . of the counter circuit 2.
A rhythm step signal is generated by a decoder made up of a group of AND circuits that take the output signal of the input signal as an input signal.

4 is a group of switches for selecting a predetermined rhythm; 5 is a rhythm pattern generation circuit that receives as input the rhythm step signal generated by the decoder 3 and the rhythm designation signal selected by the switch group 4 and generates a desired rhythm; Reference numeral 6 denotes an output signal inhibition gate circuit, which is composed of a group of AND circuits controlled by the start signal from the start switch 7 and the rhythm signal from the rhythm pattern generation circuit 6, and is configured to shape the rhythm signal at the start with a clock pulse and pass it through. When stopped, the passage is blocked.

3 is a sound source circuit that is triggered by the rhythm signal that has passed through the output signal inhibition gate circuit 6 and drives the speaker 9.

Reference numeral 10 is a command switch for counter control, which is the object of the present invention, and repeats the first half or the second half of all performance measures depending on when it is turned on.

Next, the operation of the present invention will be explained with reference to FIG.

At the beginning, when the start switch 7 is turned on, each frequency divider C in the counter circuit 2 is connected via the first inverter 11 in FIG.
The reset signals applied to the reset terminals R, R, . . . of the devices 1, C2, .

Further, the reset signal at the reset terminal of the clock pulse generator 1 is also released, causing the clock pulse generator 1 to operate and producing the signal shown at the opening in FIG.

The signal is frequency-divided by frequency dividers C1, C2... and each frequency divider C
1, C2 . . . generate the signals shown in FIG.

These signals are decoded by a decoder 3.

These decoded signals are applied to a rhythm pattern generation circuit 5, which generates a specified rhythm signal under the control of the rhythm designation signal selected by the switch group 4.

These signals are applied to the output signal inhibit gate circuit 6.

If the signals from the start switch 7 and decoder 3 are applied to the output signal prohibition gate circuit 6 via the first AND circuit 12, the selected rhythm designation signal passes through the output signal prohibition gate circuit 6 and is sent to the sound source circuit. 8 to drive a desired sound source.

The signal is amplified by an amplifier 13 and drives the speaker 9.

Such an operation is repeated, so that, for example, the entire performance from measure ■ to measure ■ is played in sequence.

By the way, ■■■ If you want to play a measure repeatedly, when the state of the final stage divider cn+t is "0" (stop,
■■Measure performance period) Turn on the command switch 10 (4th
(Fig. t, t).

Then, the second AND circuit 14 receives a signal "1" obtained by inverting the signal nIIt from the instruction switch 10 and the output signal of the final stage frequency dividing circuit Cn+1 by the second inverter 15.
51 will be added.

The signal "'1" passes through the first OR circuit 16 and is applied to the reset terminal R of the frequency divider Cn+1 at the final stage.
+1 is fixed in the “0” state■,■no measure is played■,
■Play a measure repeatedly.

Or, if you want to repeatedly play only measures ■ and ■, when the state of the final stage divider Cn-1-1 is "1" (■
(2) Measure performance period) When the command switch 10 is turned on, the signal "1" from the frequency divider Cn+1 and the signal +1111 from the command switch 10 are connected to the third AND circuit 16.

These signals 91 and 11 are applied to the set terminal of the final stage divider Cn+1, and the divider Cn+1 is fixed in the u111 state, so that at this time, the bars are played repeatedly.

In the above description, a case has been described in which only the state of the final stage of the counter is fixed, but it is clear that the state of any stage can be fixed.

Furthermore, in the above explanation, the final stage of the counter is fixed to ``0'' or 1'' depending on the timing when the instruction switch is turned on. ” or “1”, it is also possible to repeatedly play only the first half or the second half of all the playable bars.

Further, in the above description, a method of fixing a predetermined stage of the counter using an output signal from an instruction switch has been described, but it is obvious that an output signal from a flip-flop circuit or the like can be used instead of an output signal from an instruction switch.

As described above, in the automatic rhythm performance device of the present invention, the divider at a predetermined stage in the counter circuit that divides the frequency of the clock pulse from the oscillator is fixed in a predetermined state by a control signal, so that all the measures that can be played are fixed. When the main performance is divided into multiple parts, only one or several measures of the divided parts that are being played at that time can be played repeatedly.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an automatic rhythm performance apparatus according to the present invention, and FIG. 2 is a time chart of output signals from each part. 1...Clock pulse generator, 10...Instruction switch,
2...Power counter circuit, 3...Decoder, C1, C2
... Frequency divider, 5... Rhythm pattern generation circuit.

Claims (1)

[Claims] 1. A clock pulse generation circuit that generates a clock pulse corresponding to the beat of the smallest rhythm unit, a counter circuit that includes a divider that sequentially divides the clock pulse, and the divider output of each stage of the counter circuit as input. a rhythm pattern generation circuit that receives the rhythm step signal and rhythm designation signal generated by the decoder and generates a desired rhythm pattern, and a rhythm sound source circuit that is driven by the output of the rhythm pattern generation circuit. An automatic rhythm playing device comprising: a predetermined stage divider in the counter circuit is fixed in a predetermined state so that only a predetermined portion of the rhythm pattern is repeatedly played. performance equipment.