JPS5840758B2 - daily rhythm ensouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an automatic rhythm performance device having an intro performance function, in which when all playable measures are divided into several equal parts such as the first half and the second half, only any of the divided measures can be freely used as the intro performance measure. This invention relates to a selectable automatic rhythm performance device.

Furthermore, to explain the present invention, during the intro performance period, transmission of the frequency division signal to the division period after a predetermined stage constituting the counter circuit is prohibited, and the frequency division signal in the state of the frequency divider after the predetermined stage is controlled independently. By doing this, you can play the first half or second half of all measures, allowing you to play not only the first half of the intro performance and then the main performance, but also the intro performance. This invention relates to an automatic rhythm playing device that can play only the latter half of the measure and then proceed to the main performance, and will be described below with reference to the drawings.

In FIG. 1, 1 is a clock pulse generator that generates a clock pulse corresponding to the beat of the smallest rhythm unit, and 2 is a frequency divider C1, C2, and C2 that sequentially divides the frequency of the clock pulse.
A counter circuit having the clock pulse generator 1 and the frequency divider C1°C2...
Reset terminals R, R provided on...
is connected to the nutato isochi 4 via the third inverter 3, and the final stage frequency divider Cn+1 is connected to the previous stage frequency divider Cn via the first AND circuit 5.
The reset terminal R of n+t is connected to the first instruction switch 6, and the set terminal S of n+t is connected to the second instruction switch 7, respectively.

8 is an intro flip-flop whose output terminal layer is connected to one input terminal of the first AND circuit 5, and whose output terminal layer is connected to one input terminal of the first AND circuit 5;
is connected to the intro switch 10 via the second differentiating circuit 9.

Further, the reset terminal R is connected to the output terminal of the first OR circuit 11.

One input terminal of the first OR circuit 11 is connected to the intro switch 10 via a second inverter 12, and the other input terminal is connected to the output terminal of the divided period Cn via a first differentiating circuit 13 and a first inverter 14. It is connected to the.

Reference numeral 15 denotes each frequency divider C, Cn, . . . of the counter circuit 2.
This is a decoder composed of, for example, a group of AND circuits, which inputs the output signals of .

16 is a rhythm pattern generation circuit that manually generates a desired rhythm pattern using the step signal decoded by the decoder 15 and the rhythm designation signal selected by the switch group 11; 18 is an output signal prohibition gate circuit that is connected to the start switch 4; It has a group of AND circuits controlled by a start signal from the clock pulse generator 1 and a signal from the clock pulse generator 1, and passes a rhythm signal shaped by a clock pulse at a start time, and prevents the rhythm signal from passing at a stop time.

Reference numeral 19 denotes a sound source circuit that is triggered by the rhythm signal that has passed through the output signal prohibition gate circuit 18, and the output is sent to the amplifier 20.
and is connected to the Nubee car 21.

Next, the operation of the present invention will be explained with reference to the time chart shown in FIG.

First, when the intro switch 10 is turned on, the second differentiation circuit 9
After that, the signal IIl" is applied to the set terminal S of the intro flip-flop 8, and the output terminal Q of the intro flip 70 knob 8 is set to the signal "0".

(Fig. 2H) When the start switch 4 is turned on in this state, the signal "'1" is inverted by the third inverter 3, and the clock pulse generator 1 and each frequency divider C1, C2...
The reset voltages of the reset terminals R, R, . C2・
...... (Fig. 2 C-F), and due to the fall of the output of the frequency divider Cn (Fig. 2 F), the first
A signal is applied to the reset terminal R of the intro flip-flop 8 via the inverter 14, the first differentiating circuit 13, and the first OR circuit 11 (FIG. 2G).

That first pulse causes the intro flip-flop 8 to
is reset and the output terminal Q changes from signal “O” to signal “1”
(Figure 2H).

The output signal n l" is applied to one end input of the first AND circuit 5.

Since the output of the frequency divider Cn (FIG. 2F) is applied to the other end input, the first AND circuit 5 generates an output signal (FIG. 2).

Here, since the state of the final stage frequency divider Cn+t differs depending on the states of the first instruction switch 6 and the second instruction switch 7, three cases will be explained below.

(1) When both the first instruction switch 6 and the second instruction switch 7 are off.

First, as described above, by turning on the intro switch 10, the output terminal Q of the intro flip-flop 8 is turned on.
is set to the state of the signal ``O''.

Even if a signal "1" is received from the frequency divider Cn, it cannot pass through the first AND circuit 5, so the signal is not applied to the input of the final stage frequency divider Cn+1.

Next, when the output signal of the frequency divider Cn is inverted from 1" to "O", the output terminal Q of the intro flip-flop 8 is "
1”.

However, at this time, the output signal of the frequency divider Cn is "0", so the output signal of the frequency divider Cn+1 is still "0".

Next, the output signal of the frequency divider Cn becomes P1''.

Also, the output terminal Q of the intro flip-flop 8 is the signal +
1, “, so the frequency divider cn+,
Signal "1" is added to human power.

Next, when the output signal of the frequency divider Cn becomes IT Off, the signal ++O" is applied to the input of the frequency divider Cn+1, and the output signal of the frequency divider Cn+1 becomes "■".

(FIG. 2J) These signals are decoded by the decoder 15 and applied to the rhythm pattern generation circuit 16.

The rhythm pattern generation circuit 16 selects a predetermined rhythm under the control of the rhythm designation signal and applies it to the output prohibition gate circuit 18 .

When the output terminal layer of the input flip-flop 8 is in the state of the signal 110'', the output inhibit gate circuit 18
Only the intro signal is passed through, and when the signal is in the state of "■", only the main performance signal is passed through.

Therefore, the first two verses in which the output terminal Q of the intro flip 70 knob 8 is a signal "0" are played as an intro.

Moreover, at that time, the output signal of the frequency divider Cn+1 is "0", so the measures of ■■ of in)o are played.

The main performance starts when the output terminal 4 of the intro Noritsubu flop 8 is inverted to 1. At this time, the frequency divider Cn+
Since the output signal of 1 is still 0", the Φ卆" section of the main performance is played.

At the next moment, the output terminal Q of the frequency divider cn +t becomes 1, so measure ■■ of the main performance is played.

(2) First instruction switch 6 is on, second instruction switch 7
is off.

Since the signal ``1'' is applied to the reset terminal R of the frequency divider Cn+ through the first command switch 6, the output signal of the frequency divider Cn+1 is always 0'' (FIG. 2).

Therefore, the output terminal Q of the intro flip-flop 8 is 0.
When it is “,” the intro measure ■■ is played, and when it is “1”, only the main performance measure ■■ is played.

(3J First instruction switch 6 is off, second instruction switch 1 is on.

At this time, a signal of 1'' is applied to the cent terminal S of the frequency divider cn+t via the second command switch 7.

As a result, the signal at the output terminal of the frequency divider Cn+1 is always 1.
4, n (Figure 2C)).

This means that the signal applied to the decoder 15 from the frequency divider c1j C2'''''' is only the ■■ measure performance.

Therefore, the signal generated by the rhythm pattern generation circuit 16 is the signal "0" at the output terminal Q of the intro Noritub flop 8.
While the output signal is ``,'', the output signal prohibition circuit 19 allows only the intro signal to pass through and plays the intro C2 measure.

Next, the output terminal Q of the intro Noritsubu flop 8 becomes the signal n,'', so the output signal inhibition gate circuit 19 passes the main performance signal and repeatedly plays the main performance's measures.

(4) When the intro switch 10 is turned off, the signal 741N inverted by the second inverter 12 is connected to the reset terminal R of the intro flip-flop 8, and outputs the output terminal Q of the intro flip-flop R as a signal. Set it to the “1” state.

Therefore, since the signal pulse is always connected to one end of the input terminal of the first AND circuit 50, if there is a signal "1" from the frequency divider Cn, that signal IT IN will all pass through the first AND circuit 5. It is added to frequency divider Cn+1 (not shown).

Also, the signal + of the output terminal Q of the intro flip-flop 8
111'l is added to the output signal prohibition gate circuit 18 and passes the main performance signal, so that the main performance is directly performed without performing an intro performance.

The above explanation has been made regarding the case where the final stage is controlled using the first and second command switches. It is also clear that the number of stages can be controlled.

The automatic rhythm performance device of the present invention uses an output signal of a storage circuit for performance control, which is set by a signal generated by an intro switch and reset in response to a change in the output of a frequency divider at a predetermined stage. The transmission of the frequency division signal to a predetermined stage and subsequent stages of the counter circuit is prohibited, and when the memory circuit is reset, the state of the frequency divider after the predetermined stage is controlled by the signal from the command switch. By operating the switch, you can play the intro performance from the beginning and play all the measures of the main performance, or repeat some measures of the main performance, or you can play the intro performance from the middle and the main performance will continue. Corresponding measures can be played repeatedly, allowing for a variety of rhythmic performances.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an automatic rhythm playing device of the present invention, and FIG. 2 is a time chart of output signals of each part. 1... Clock pulse generator, 2...
Counter circuit, C1, C2... Frequency divider, 4.
...Start switch, 6, 7...1st
, second instruction switch, 8...° (intro flip-flop, 10...intro switch.

Claims (1)

[Claims] 1. A clock pulse generator that generates a clock pulse corresponding to the beat of the smallest rhythm unit, a counter circuit consisting of a plurality of frequency dividers connected in multiple stages to divide the clock pulse, and each membrane of the counter circuit. A decoder receives the output of the external circuit, a rhythm pattern generation circuit receives the rhythm step signal decoded by the decoder and the rhythm designation signal as input, and generates a desired rhythm pattern. a memory circuit for controlling an intro performance which is inverted in response to a change in the output of a frequency divider of a predetermined stage; a gate circuit is controlled by the output signal of the memory circuit for controlling the intro performance; The circuit selectively prohibits the application of a frequency division pulse to the frequency divider after a predetermined stage of the counter circuit, and also commands the set terminal or reset terminal or the set terminal and reset terminal of the frequency divider after the predetermined stage. An automatic rhythm performance device that makes it possible to obtain a desired rhythm pattern by adding a cent signal or a reset signal from a switch to control the frequency divider to different states.