JPS5811655B2 - Buffer storage device address control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address control method for a buffer storage device in a multi-processor system consisting of a plurality of central processing units each having a buffer storage device and one main storage device.

In a multi-processor system where multiple central processing units (CPUs) share one main memory, prefix conversion is performed on each CPU so that the area (prefix area) unique to each CPU does not overlap. I am doing it.

The prefix area is for each CPU from the program's perspective.
Both are given the same fixed address, but the contents are different for each CP.
Since it is U-specific information, is it physical? These must be allocated to different main memory addresses.

Therefore, each CPU maps the prefix area to its own main memory address and swaps addresses between the prefix area and the mapped area.

This is called prefix conversion. This prefix conversion will be explained in more detail with reference to FIG.

This is also disclosed, for example, on pages 38-1 to 38-4 of "rHITACM-180/170/160 II Processing Apparatus" (3rd edition) published by Hitachi, Ltd. in October 1975.

Referring to Figure 3, the programs on CPU0 and CPU1 have their own real addresses, which are converted into prefixes? From this, the absolute address is converted by one and the main storage device is accessed.

The prefix area of each CPU is address 0 to 4095, and area A at the real address of CPU0 is area A' at the absolute address, and area C at the real address of CPU1.
is addressed to area C' with an absolute address.

Area B of CPU0, which overlaps area A' of the absolute address addressed by the prefix area of CPU0, is area B', which is the absolute address 0 to 4095, and area B' of the absolute address addressed by the prefix area of CPU0. CP that overlaps with area C'
Area D of the UI is addressed at absolute addresses 0-4095, area D/ (which is equal to area B').

For areas other than this area, the real address is treated as an absolute address.

In the case where the above-mentioned CPU has a buffer storage device, in the conventional technology, the address after prefix conversion (absolute address) is used to refer to the buffer storage device.

FIG. 1 shows an example of the configuration of such a conventional technology, in which 1 is an address calculator, 2 is an address converter, 3 is a prefix converter, 5 is an index array, 6 is a buffer storage device, and 7 is a comparison device. When the buffer storage device 6 is read by its own CPU, the logical address obtained by the address calculator 1 is converted to a real address by the address converter 2, and the obtained real address is sent to the prefix converter 3. The prefix is converted by , and reading from the buffer storage device 6 is performed by referring to the index array 5 using a part of the converted address.

When accessing the main storage device, this prefix conversion address (absolute address) is used.

Therefore, reading from the buffer storage device is delayed by the time required for prefix conversion, leading to a decrease in the performance of the buffer storage device.

An object of the present invention is to speed up reading from a buffer storage device by using an address before prefix conversion as a read address from the buffer storage device.

In the present invention, the read address of the buffer storage device uses the address before prefix conversion to speed up the read time of the buffer storage device, and the block cancellation interface with other CPUs uses the address after prefix conversion, and the read address of the buffer storage device is When canceling a block in a CPU's buffer storage device, the block cancel address sent from another CPU is prefix-inverse converted and then given to the buffer storage device.

Hereinafter, the content of the present invention will be explained in detail with reference to Examples.

FIG. 2 shows an example of the configuration of the address control method according to the present invention.
In the figure, 1 is an address calculator, 2 is an address converter, 5 is an index array, 6 is a buffer storage device, γ
is a comparator, 9 is a read data register, and 10 is a prefix converter.

Reading of the buffer storage device 6 by its own CPU is as follows:
The logical address obtained from the address calculator 1 is converted into a real address by the address converter 2, and a part of the obtained real address is immediately referred to the Indylus array 5, and the read data is compared with the remaining address. Judgment with instrument 7,
If they match, the data in the buffer storage device 6 is read and set in the data register 9.

If they do not match, the data read from the main memory is set in the read data register 9 through the main memory data bus 8.

As is clear from this, the buffer storage device is accessed under the real address of each CPU that is not prefix-converted.

Access to the main storage device is performed using prefix conversion and absolute addresses as in the prior art.

This prefix conversion is performed using prefix converter 3, and in the example of FIG.
', B is converted to B' in the same way as before.

On the other hand, when writing to the main unit, the real address obtained from address converter 2 is converted to prefix converter 1.
0 (same as prefix converter 3), and then sent to other CPUs via block cancel address bus 11.

If Figure 2 is CPUQ, then in the example of Figure 3, real address area A is converted to absolute address area A', real address area B is converted to absolute address area B', and the CPU
Send to 7.

When a block cancellation request is received from another CPU, the address (absolute address) sent from the block cancellation address bus 4 is converted to a prefix converter 10.
The block is then converted and sent to the buffer storage device to perform block cancellation.

For example, if Figure 2 is CPU0, then in the example of Figure 3, absolute address area B'(=D') is set to CPU0's real address area B, and absolute address areas A,' are set to CPU0's real address area A. The reverse conversion is performed to access the buffer storage managed under each CPU's real address.

Even though it is an inverse transformation, it is clear from Figure 3 that A and B
'1A' and B have the same address value, so converting A to A' and converting B/ back to B are exactly the same operation, so prefix inversion uses the same prefix as prefix converter 3. This can be realized using the converter 10.

As a result, for example, when CPU0 rewrites the real address area B of CPU0, the absolute address on the main memory is rewritten to area B/ (which is the same as D'), and CPU1 has the absolute address of area D' and C
In PU1, this is reversely converted to area D, and the block in the buffer storage device of CPU1 corresponding to area D, which is the source of the real address, can be block-cancelled.

As described above, according to the present invention, the long reading time of the buffer storage device can be reduced by the time required for prefix conversion, so that a high-speed buffer storage device can be obtained.

[Brief explanation of drawings]

FIG. 1 shows an example of an address control method for a buffer storage device according to the prior art. FIG. 2 shows an embodiment of an address control scheme for a buffer storage device according to the present invention. FIG. 3 is a diagram explaining prefix conversion. 1... Address calculator, 2... Address converter, 3... Prefix converter, 5...
...Indices array, 6...Buffer storage device, 7...Comparator, 9...
Read data register, 10... Prefix converter.

Claims (1)

[Claims] 1. In a multi-processor system consisting of a plurality of central processing units each having a buffer storage device and one main memory device, each central processing unit is required to perform bidirectional conversion to and from a given area, which is a prefix area. A prefix converter is provided to perform the prefix conversion, and the readout of the buffer storage device by its own central processing unit is performed using the address before prefix conversion, and the block cancellation request to another central processing unit is performed using the address after prefix conversion. When a block cancellation request is received from another central processing unit, the prefix inverse conversion is performed on the address sent from the other central processing unit, and block cancellation is performed using the converted address. Address control method.