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JPS5811736B2 - Hand tie souchi - Google Patents
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JPS5811736B2 - Hand tie souchi - Google Patents

Hand tie souchi

Info

Publication number
JPS5811736B2
JPS5811736B2 JP49119025A JP11902574A JPS5811736B2 JP S5811736 B2 JPS5811736 B2 JP S5811736B2 JP 49119025 A JP49119025 A JP 49119025A JP 11902574 A JP11902574 A JP 11902574A JP S5811736 B2 JPS5811736 B2 JP S5811736B2
Authority
JP
Japan
Prior art keywords
semiconductor element
island
semiconductor
hole
souchi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP49119025A
Other languages
Japanese (ja)
Other versions
JPS5144871A (en
Inventor
萩本英二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP49119025A priority Critical patent/JPS5811736B2/en
Publication of JPS5144871A publication Critical patent/JPS5144871A/ja
Publication of JPS5811736B2 publication Critical patent/JPS5811736B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置用基体への半導体素子の取付は構造
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of attaching a semiconductor element to a substrate for a semiconductor device.

従来の半導体装置用基体への半導体素子の取付は構造を
樹脂封止型半導体装置用リードフレームを用いる場合に
ついて説明する。
The structure of attaching a semiconductor element to a conventional substrate for a semiconductor device will be described using a resin-sealed lead frame for a semiconductor device.

まずコバールのような金属材料で構成されているリード
フレームの半導体素子を載置する部分(以下アイランド
と称する)にAuメッキを施しておく。
First, a portion of a lead frame made of a metal material such as Kovar on which a semiconductor element is placed (hereinafter referred to as an island) is plated with Au.

このリードフレームなAu−Si合金片が溶融可能な温
度(約380℃以上)まで上げ、AuSi合金片をのせ
たアイランドに半導体素子を持って来て前後左右にこす
る(以下スクラブすると称する)と、半導体素子材料で
あるSiとAu−Si合金片とAuメッキ部分とで合金
化反応が起る。
The temperature is raised to a temperature at which this lead frame Au-Si alloy piece can be melted (approximately 380°C or higher), and the semiconductor element is brought to the island on which the AuSi alloy piece is placed and rubbed from front to back and from side to side (hereinafter referred to as scrubbing). An alloying reaction occurs between Si, which is a semiconductor element material, the Au-Si alloy piece, and the Au plating part.

その結果半導体素子はアイランドに強固に接着すること
ができる。
As a result, the semiconductor element can be firmly adhered to the island.

Au−Si合金片を用いず直接コバール上に施したAu
メッキ上で半導体素子をスクラブしてもAu−Si合金
化反応は起υ、上記と同様の結果となる。
Au applied directly on Kovar without using Au-Si alloy pieces
Even if the semiconductor element is scrubbed on the plating, the Au-Si alloying reaction will occur, resulting in the same result as above.

以上のAu−Si合金化反応を用いた接着方法は基体が
セラミック材料や金属材料で構成されている気密封止型
半導体装置の製造においても有効であシ、広く一般に行
なわれている。
The bonding method using the Au--Si alloying reaction described above is also effective in manufacturing hermetically sealed semiconductor devices whose substrates are made of ceramic or metal materials, and is widely used.

樹脂封止型半導体装置は広く民需用に大量生産されてい
るが、使用する樹脂材料の価格がセラミック材料のそれ
よシも安価であるため、半導体装置組立工程忙おける経
費は製品の原価構成に大きな部分を占める。
Resin-encapsulated semiconductor devices are widely mass-produced for civilian use, but because the resin materials used are cheaper than ceramic materials, the costs associated with the semiconductor device assembly process are not included in the product cost structure. occupies a large portion.

当然組立工程の自動化、省力化が要求される。Naturally, there is a need for automation and labor saving in the assembly process.

接着作業工程も自動化が要求されるのであるが、この工
程の自動化は単にこの工程ばかシでなく後工程である金
属細線を用いた接続工程(ワイヤボンディング工程)の
生産性に大きく影響するのである。
Automation of the bonding work process is also required, but automation of this process is not only a simple process, but also has a significant impact on the productivity of the subsequent process, the connection process using thin metal wires (wire bonding process). .

すなわち接着工程での半導体素子の取付は位置が一定と
なシにくいため、後工程のワイヤボンデング工程におけ
る半導体素子の電極とリードフレーム先端部分との位置
合せに時間がかかシ、ワイヤボンデング工程の生産性を
少なからず低いものとしてきた。
In other words, it is difficult to maintain a constant position when mounting the semiconductor element in the bonding process, so it takes time to align the electrodes of the semiconductor element and the tip of the lead frame in the wire bonding process, which is a later process. This has caused the productivity of the process to be quite low.

この傾向はワイヤボンデング作業を自動機械を用いて行
った時には、よシ一層顕著になシ機械の能力を十分に生
かしきれないのが現状である。
This tendency is even more noticeable when wire bonding work is performed using automatic machines, and the current situation is that the capabilities of the machines cannot be fully utilized.

一方基体がセラミック材料で構成されている気密封止型
半導体装置においては次のことが言える。
On the other hand, the following can be said about a hermetically sealed semiconductor device whose base is made of a ceramic material.

半導体素子載置部分空間の気密保持のため封止にはシー
ル幅として一定値以上の幅を必要とする。
In order to maintain airtightness of the partial space in which the semiconductor element is placed, sealing requires a seal width of a certain value or more.

しかるに半導体素子の方はその機能の増大にともないそ
の規模が大きくなる傾向にあシ、よシ大きなアイランド
が要求されている。
However, as the functions of semiconductor devices increase, their scale tends to increase, and even larger islands are required.

通常スクラブする時に半導体素子をピンセットその他の
治具でつまむため、良好な接着性を得るためには、半導
体素子とアイランドとには少くとも前後ないし左右に1
.0mm、等分して0.5mm以上の隙間を必要とする
Normally, when scrubbing, semiconductor elements are pinched with tweezers or other tools, so in order to obtain good adhesion, it is necessary to attach at least one area between the semiconductor element and the island in the front and back or left and right sides.
.. 0mm, and a gap of 0.5mm or more is required when divided into equal parts.

半導体素子の中には上記の隙間もとれない程大きなもの
もあシ、十分なスクラブ作業ができない。
Some semiconductor devices are so large that even the above-mentioned gap cannot be removed, making it impossible to perform sufficient scrubbing.

その結集合金化反応が十分に進まなければ半導体素子は
僅かの外力によってアイランドから剥離してしまう。
If the cohesive aggregation reaction does not proceed sufficiently, the semiconductor element will peel off from the island due to a slight external force.

また合金化反応が不均一に進めば不均一な熱応力の発生
を促し、半導体素子に亀裂を生じさせてしまうという不
良を多発させるに至っている。
Furthermore, if the alloying reaction proceeds non-uniformly, it promotes the generation of non-uniform thermal stress, leading to frequent failures such as cracks in semiconductor devices.

本発明は上記欠点を除去した改良された基体への半導体
素子の取付は構造を提供するものである。
The present invention provides an improved structure for mounting semiconductor devices on a substrate that eliminates the above drawbacks.

かかる目的を達成するだめの本発明の要旨は、アイラン
ドに貫通孔を設け、この貫通孔に半導体素子の側壁の少
くとも一部が挿入接着されて半導体素子を基体に固着す
ることにある。
To achieve this object, the gist of the present invention is to provide a through hole in the island, and at least a part of the side wall of the semiconductor element is inserted into the through hole and bonded, thereby fixing the semiconductor element to the base.

本発明によれば貫通孔と半導体素子との隙間を。According to the present invention, the gap between the through hole and the semiconductor element is reduced.

0.5mg以内としているため、接着工程におけるアイ
ランド内での半導体素子取付は位置を一定に保つことが
できる。
Since the amount is within 0.5 mg, the mounting position of the semiconductor element within the island during the bonding process can be kept constant.

このため現在広く行なわれているワイヤボンディング工
程での位置合せ時間を短縮することができる。
Therefore, the alignment time in the currently widely used wire bonding process can be shortened.

この時間短縮の効果は自動機械を用いた場合に著しい。This time saving effect is remarkable when an automatic machine is used.

一つのアイランド上に2つ以上の半導体素子を設けた半
導体装置の組立においても、半導体素子相互間の位置を
一定に保つことができるため、組立の確実なことと合わ
せて組立の自由化を容易にすることができる。
Even when assembling a semiconductor device with two or more semiconductor elements on one island, the positions of the semiconductor elements can be kept constant, which not only ensures reliable assembly but also facilitates freedom of assembly. It can be done.

以下に本発明の実施例について図面を参照しながら詳細
に説明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は樹脂封止型半導体装置に適用した本発明の第1
の実施例を示す。
FIG. 1 shows a first embodiment of the present invention applied to a resin-sealed semiconductor device.
An example is shown below.

コバールで構成されているベースリボンのアイランド1
には貫通孔があり、この貫通孔の側壁部を含むアイラン
ド部分はAuメッキが施されている。
Island 1 of the base ribbon made of Kovar
has a through hole, and the island portion including the side wall of this through hole is plated with Au.

ベースリボンは表面処理したステンレス鋼板(図示せず
)で支持し、半導体素子を貫通孔に挿入する。
The base ribbon is supported by a surface-treated stainless steel plate (not shown), and the semiconductor element is inserted into the through hole.

さらに貫通孔と半導体素子との隙間にAu−8i共晶コ
ウ材を帯状にして挿入した後、上記ステンレス鋼板とと
ヒータブロック上にのせる。
Further, a strip of Au-8i eutectic material is inserted into the gap between the through hole and the semiconductor element, and then placed on the stainless steel plate and the heater block.

ヒータプロツはAu−8i共晶ロウ材3が溶融する温度
(約380’C以上)にすると、半導体素子とアイラン
ドとはAu−Si合金化反応を起こして接着する。
When the heater plate is heated to a temperature at which the Au-8i eutectic brazing material 3 melts (approximately 380'C or higher), the semiconductor element and the island undergo an Au-Si alloying reaction and are bonded to each other.

合金化反応が起きにくい場合には、微小振幅の機械振動
をリードフレームないしアイランドに加えるとよい。
If the alloying reaction is difficult to occur, it is advisable to apply minute amplitude mechanical vibration to the lead frame or island.

ベースリボンをのせたステンレス鋼板なヒータブロック
からおろせば、Au−8i共晶ロウ材は凝固し接着は完
了する。
When the base ribbon is removed from the stainless steel plate heater block, the Au-8i eutectic brazing material solidifies and the adhesion is completed.

半動体素子の能動域を含む面は、この面上に接着材3が
流れ込まないように、アイランド表面よシ低くないこと
が望ましい。
The surface containing the active area of the semi-moving element should preferably not be lower than the island surface, so that the adhesive 3 does not flow onto this surface.

第2図にはその素子を示すためにアイランド部分の切断
面を示す。
FIG. 2 shows a cut section of the island portion to show the element.

使用する接着材としては上記のAuSi共晶ロウ材の他
にAc−8uロウ材、熱硬化性樹脂たとえばエポキシ樹
脂にAu。
In addition to the AuSi eutectic brazing material mentioned above, the adhesive used is Ac-8u brazing material, thermosetting resin such as epoxy resin, and Au.

Ag等の粉末を含有させた接着材を用いることができる
An adhesive containing powder such as Ag can be used.

また接着工程における加熱の手段として、従来からのヒ
ータブロック等による加熱方法以外にも、たとえばレー
ザ光線のような強力な熱線をアイランドの貫通孔の側壁
部と半導体素子との隙間にある接着材3に照射すること
によっても加熱することができる。
In addition, as a means of heating in the bonding process, in addition to the conventional heating method using a heater block, for example, a strong heat ray such as a laser beam can be used to heat the adhesive material 3 in the gap between the side wall of the through hole of the island and the semiconductor element. It can also be heated by irradiating it with water.

第2図では基体下方または上方からレーザ光線4を照射
する様子を示す。
FIG. 2 shows how the laser beam 4 is irradiated from below or above the substrate.

レーザ光線4による加熱は局部的であるため、半導体素
子の機能を損うことなく接着を行うことができる。
Since the heating by the laser beam 4 is localized, bonding can be performed without impairing the function of the semiconductor element.

以上のような組立方法を用いれば半導体素子に亀裂を生
じさせたり、また半導体素子がアイランドから僅かな外
力によって剥離するという不良が防げるばかりでなく、
アイランドに0.5mm以内の隙間を残しただけの規模
の半導体素子を載置することができる。
Using the above assembly method not only prevents defects such as cracks in the semiconductor element or separation of the semiconductor element from the island due to a slight external force, but also
It is possible to mount a semiconductor element of such a scale that only a gap of 0.5 mm or less is left on the island.

第3図は1つのアイランドに2つ以上の半導体素子を設
けた半導体装置に適用した本発明の第2の実施例を示す
FIG. 3 shows a second embodiment of the present invention applied to a semiconductor device in which two or more semiconductor elements are provided on one island.

以上に第1.第2の実施例を挙げて説明してきたが上記
実施例は本発明の実施例の一部にすぎず、本発明の請求
範囲を制限するものではないことは当然である。
Above is the first point. Although the second embodiment has been described, the above embodiment is only a part of the embodiments of the present invention, and it goes without saying that it does not limit the scope of the claims of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

図面はすべて本発明の実施例を示すもので、第1図は第
1の実施例の要部斜視図、第2図は第1図の切断正面図
、第3図は第2の実施例の要部斜視図を示す。 なお図面において、1は基体アイランド、2は半導体素
子、3は接着材、4はレーザ光線である。
The drawings all show embodiments of the present invention; Fig. 1 is a perspective view of essential parts of the first embodiment, Fig. 2 is a cutaway front view of Fig. 1, and Fig. 3 is a cross-sectional view of the second embodiment. A perspective view of the main parts is shown. In the drawings, 1 is a base island, 2 is a semiconductor element, 3 is an adhesive, and 4 is a laser beam.

Claims (1)

【特許請求の範囲】[Claims] 1 ベースリボンのアイランドに貫通孔が設けられてお
シ、該貫通孔内に半導体素子が挿入され、該半導体素子
の能動域を含まない面は該ベースリボンの一方の面とほ
ぼ一致しておシ、該半導体素子の能動域を含む面は該ベ
ースリボンの他方の面よシ突出しておシ、かつ該貫通孔
の側壁と該半導体素子の側壁との間の0.5ty以下に
設けられた間隙に接着材を設けることによって該半導体
素子を該ベースリボンに固着していることを特徴とする
半導体装置。
1 A through-hole is provided in the island of the base ribbon, a semiconductor element is inserted into the through-hole, and a surface of the semiconductor element that does not include an active area substantially coincides with one surface of the base ribbon. C. The surface including the active area of the semiconductor element protrudes from the other surface of the base ribbon, and is provided at a distance of 0.5ty or less between the side wall of the through hole and the side wall of the semiconductor element. 1. A semiconductor device, wherein the semiconductor element is fixed to the base ribbon by providing an adhesive in the gap.
JP49119025A 1974-10-15 1974-10-15 Hand tie souchi Expired JPS5811736B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP49119025A JPS5811736B2 (en) 1974-10-15 1974-10-15 Hand tie souchi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49119025A JPS5811736B2 (en) 1974-10-15 1974-10-15 Hand tie souchi

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP57070139A Division JPS606090B2 (en) 1982-04-26 1982-04-26 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5144871A JPS5144871A (en) 1976-04-16
JPS5811736B2 true JPS5811736B2 (en) 1983-03-04

Family

ID=14751110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP49119025A Expired JPS5811736B2 (en) 1974-10-15 1974-10-15 Hand tie souchi

Country Status (1)

Country Link
JP (1) JPS5811736B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5776848A (en) * 1980-10-30 1982-05-14 Seiko Epson Corp Mounting method for integrated circuit chip
JPS606090B2 (en) * 1982-04-26 1985-02-15 日本電気株式会社 Manufacturing method of semiconductor device
JPS5982746A (en) * 1982-11-04 1984-05-12 Toshiba Corp Electrode wiring method of semiconductor device
JPS59141292A (en) * 1983-02-01 1984-08-13 イビデン株式会社 Method of producing laminated board for printed circuit
US4528216A (en) * 1983-02-24 1985-07-09 Oki Electric Industry Co., Ltd. Process for forming heat-resistant resin films of polyimide and organosilicic reactants
CN100585220C (en) 2004-06-22 2010-01-27 杉谷伸 Gear mechanism, planetary gear device, rotary bearing device, and singular planetary gear reduction device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4918590U (en) * 1972-05-19 1974-02-16

Also Published As

Publication number Publication date
JPS5144871A (en) 1976-04-16

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