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JPS606090B2 - Manufacturing method of semiconductor device - Google Patents
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JPS606090B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS606090B2
JPS606090B2 JP57070139A JP7013982A JPS606090B2 JP S606090 B2 JPS606090 B2 JP S606090B2 JP 57070139 A JP57070139 A JP 57070139A JP 7013982 A JP7013982 A JP 7013982A JP S606090 B2 JPS606090 B2 JP S606090B2
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor device
semiconductor
island
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57070139A
Other languages
Japanese (ja)
Other versions
JPS57184225A (en
Inventor
英二 萩本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57070139A priority Critical patent/JPS606090B2/en
Publication of JPS57184225A publication Critical patent/JPS57184225A/en
Publication of JPS606090B2 publication Critical patent/JPS606090B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/685Shapes or dispositions thereof comprising multiple insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07336Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07337Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/352Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置用基体への半導体素子の取付け方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for attaching a semiconductor element to a substrate for a semiconductor device.

従来の半導体装置用基体への半導体素子の取付け構造を
樹脂封止型半導体装置用リードフレームを用いる場合に
ついて説明する。
A conventional structure for attaching a semiconductor element to a semiconductor device substrate will be described using a resin-sealed semiconductor device lead frame.

まずコバールのような金属材料で構成されているリード
フレームの半導体素子を戦層する部分(以下アイランド
と称する)にAuメッキを施しておく。このリードフレ
ームをAu−Sj合金片が溶融可能な温度(約3800
0以上)まで上げ、Au−Si合金片をのせたアィラン
日こ半導体素子を持って来て前後左右にこする(以下ス
クラブすると称する)と、半導体素子材料であるSiと
Au−Si合金片とAuメッキ部分とで合金化反応が起
る。その結果半導体素子はアィランド‘こ強固に接着す
ることができる。Au−Si合金片を用いず直接コバー
ル上に施したAuメッキ上で半導体素子をスクラブして
もAu−Si合金化反応は起り、上記同様の結果となる
。以上のAu−Si合金化反応を用いた接着方法は基体
がセラミック材料や金属材料で構成されている気密封止
型半導体装置の製造においても有効であり「広く一般に
行なわれている。
First, Au plating is applied to a portion (hereinafter referred to as an island) on which a semiconductor element of a lead frame made of a metal material such as Kovar is placed. This lead frame is heated to a temperature at which the Au-Sj alloy piece can be melted (approximately 3800°C).
0 or more), then bring the Airan-Japanese semiconductor device with the Au-Si alloy piece on it and rub it back and forth and left and right (hereinafter referred to as scrubbing). An alloying reaction occurs with the Au plated portion. As a result, the semiconductor element can be firmly bonded to the island. Even if a semiconductor element is scrubbed on the Au plating directly applied to Kovar without using an Au-Si alloy piece, the Au-Si alloying reaction occurs, resulting in the same result as described above. The bonding method using the Au--Si alloying reaction described above is also effective in manufacturing hermetically sealed semiconductor devices whose substrates are made of ceramic or metal materials, and is widely used.

しかしながらこのリードフレームにスクラブする場合は
リードフレーム自体をその作業場所に用意しなければな
らず面倒な場合が多く「 この分製造が容易とならない
こととなる。
However, when scrubbing a lead frame, the lead frame itself must be prepared at the work site, which is often troublesome and does not make manufacturing easier.

このことは基体がセラミック材料や金属材料で構成され
る気密封止型半導体装置でも同様のことがいえる。又、
従来技術では熱放散はリードフレームの材質、厚さある
いは容器全体を形成するセラミックの材質等で定められ
るから、熱放散を重要視した設計ができにくい欠点があ
る。
The same holds true for hermetically sealed semiconductor devices whose base bodies are made of ceramic or metal materials. or,
In the conventional technology, heat dissipation is determined by the material and thickness of the lead frame or the ceramic material forming the entire container, so it is difficult to design with heat dissipation as important.

したがって本願の目的は、製造が容易でかつ熱放散の良
好となる半導体装置の製造方法を提供することである。
Therefore, an object of the present application is to provide a method for manufacturing a semiconductor device that is easy to manufacture and has good heat dissipation.

本発明の特徴は、支持体の上面に半導体素子を接着材に
て固着させる工程と、しかる後に半導体装置用基体に設
けられた貫通孔内に該半導体素子を挿入し該基体の底面
と該支持体の上面の該半導体素子が設けられていない部
分とを接着材にて固着させる工程とを有し、該貫通孔の
側壁と該半導体素子の側壁とが0.5側以下になるよう
設定されていることによって該基体の所定個所に該半導
体素子を位置せしめた半導体装置の製造方法にある。従
来技術において基体に凹部を設けこの凹部の底面に半導
体素子を接着する構造がある。
The features of the present invention include the step of fixing the semiconductor element to the upper surface of the support with an adhesive, and then inserting the semiconductor element into a through hole provided in the base for a semiconductor device, and then attaching the semiconductor element to the bottom of the base and the support. fixing a portion of the upper surface of the body where the semiconductor element is not provided with an adhesive, and the side wall of the through hole and the side wall of the semiconductor element are set to be 0.5 side or less. The present invention provides a method for manufacturing a semiconductor device, in which the semiconductor element is positioned at a predetermined location on the base by using a method of manufacturing the semiconductor device. In the prior art, there is a structure in which a recess is provided in a base and a semiconductor element is adhered to the bottom surface of the recess.

しかしこの様な構造でスクラブする時に半導体素子をピ
ンセットその他の治具でつまむため、良好な接着性を得
るためには、半導体素子とアイランドとには少くとも前
後ないし左右に1.仇肋,等分して0.5肋以上の隙間
を必要とする。半導体素子の中には上記の隙間もとれな
い程大きなものもあり、十分なスクラブ作業ができない
。その結果合金化反応が十分に進まなければ半導体素子
は僅かの外力によってアイランドから剥離してしまう。
また合金化反応が不均一に進めば不均一な熱応力の発生
を促し、半導体素子に亀裂を生じさせてしまうという不
良を多発させるに至っている。又、上記従来技術で十分
のスクラブを行うためには大きな凹部が必要となり、こ
のために容器全体が大のものとなってしまう。これに対
して本発明の構造では半導体素子は支持体に自由にスク
ラブして信頼性よく固着させることができる。
However, when scrubbing with this structure, the semiconductor element is pinched with tweezers or other tools, so in order to obtain good adhesion, the semiconductor element and the island must be spaced at least 1. Requires a gap of 0.5 ribs or more when divided into equal parts. Some semiconductor devices are so large that even the above-mentioned gap cannot be removed, making it impossible to perform sufficient scrubbing. As a result, if the alloying reaction does not proceed sufficiently, the semiconductor element will peel off from the island due to a slight external force.
Furthermore, if the alloying reaction proceeds non-uniformly, it promotes the generation of non-uniform thermal stress, leading to frequent failures such as cracks in semiconductor devices. Further, in order to perform sufficient scrubbing with the above-mentioned conventional technique, a large recess is required, which results in a large container as a whole. In contrast, with the structure of the present invention, the semiconductor element can be freely scrubbed and reliably fixed to the support.

又、本発明において「貫通孔と半導体素子との隙間を0
.5脚以内とすることが好ましい。これにより接着工程
におけるアイランド内でのすなわち半導体装置用基体で
の半導体素子取付け位置を実用上の一定に保つことがで
きるからであり、このため現在広く行なわれているワイ
ヤボンディング工程での位置合せ時間を短縮することが
できるからである。この時間短縮の効果は自動機械を用
いた場合に著しい。一つのアイランド上に2つ以上の半
導体素子を設けた半導体装置の組立においても、半導体
素子相互間の位置を一定に保つことができるため、組立
の確実なことと合わせて組立の自動化を容易にすること
ができる。以下に本発明の実施例について図面を参照し
ながら詳細に説明する。
In addition, in the present invention, "the gap between the through hole and the semiconductor element is reduced to 0".
.. Preferably, there are no more than five legs. This is because the mounting position of the semiconductor element within the island in the bonding process, that is, on the substrate for semiconductor devices, can be kept constant for practical purposes, and this reduces the alignment time in the currently widely used wire bonding process. This is because it is possible to shorten. This time saving effect is remarkable when automatic machines are used. Even when assembling a semiconductor device with two or more semiconductor elements on one island, the positions of the semiconductor elements can be kept constant, making assembly reliable and easy to automate assembly. can do. Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は樹脂封止型半導体装置に適用した本発明の第1
の実施例を示す。すなわち第1図には半導体素子2の能
動城を含まぬ面にアイランドの一部分となるべき支持体
5を設けた本発明の第1の実施例を示す。コバールのよ
うな金属材料ないしアルミナ,ベリリア等にメタライズ
処理したセラミック材料から成り表面をAuメッキした
支持体5上に半導体素子2を接着しておく。接着材とし
てはAu−Si,Au−Snロウ材等を用いることがで
きる。半導体素子2を戦層した支持体5をベースリボン
のアイランドの貫通孔に半導体素子2が挿入される様に
設置し、アイランド亀と支持体5とを接着する。コバー
ルで構成されているベースリボンのアイランド部分はA
uメッキされている。接着材はAu−Si,Au−Sn
ロウ材が有効である。支持体5を設けることによりアイ
ランドへの接着を強固にできるばかりでなく「半導体装
置の熱抵抗を大幅に減少させるこをか可能である。次に
セラミック材料によって構成された気密封止型半導体装
置に適用した本発明の第2の実施例を第2図に示す。
FIG. 1 shows a first embodiment of the present invention applied to a resin-sealed semiconductor device.
An example is shown below. That is, FIG. 1 shows a first embodiment of the present invention in which a support 5, which is to become a part of an island, is provided on a surface of a semiconductor element 2 that does not include an active castle. The semiconductor element 2 is bonded onto a support 5 made of a metal material such as Kovar or a ceramic material metallized with alumina, beryllia, etc. and whose surface is plated with Au. As the adhesive material, Au--Si, Au--Sn brazing material, etc. can be used. A support 5 on which a semiconductor element 2 is layered is installed so that the semiconductor element 2 is inserted into a through hole of an island of a base ribbon, and the island shell and support 5 are bonded. The island part of the base ribbon made of Kovar is A
U-plated. Adhesive material is Au-Si, Au-Sn
Brazing wood is effective. By providing the support 5, it is possible not only to strengthen the adhesion to the island, but also to significantly reduce the thermal resistance of the semiconductor device.Next, it is possible to significantly reduce the thermal resistance of the semiconductor device. A second embodiment of the present invention applied to is shown in FIG.

セラミック材料をメタラィズ処理しAuメッキを施して
ある支持体5に半導体素子2を接着する。接着材にはA
u−Si合金ロウ材を用いる。基体アイランドの貫通孔
の外側緑6はメタラィズ処理しAuメッキを施しておく
。半導体素子2を敷遣した支持体5をAu−Snロウ材
のりング3bを介して貫通孔に半導体素子2が挿入され
るように設置し「押しつけ加熱して接着する。すなわち
接着材3は半導体素子直下部3aはAu−Si合金から
、貫通孔周囲部はAu−Sn合金から構成されており、
Au−Si合金の融点はAu−Sn合金のそれに〈らべ
て約100q0も高いため、接着材3bを形成する時の
加熱で接着材3aの部分が融けることはない。以上のよ
うに半導体素子2を半導体装置用基体に固着した後は、
従来の組立工程に従って所定のワイヤボンディングを行
った後、Au−Snロウ材によってセラミックキャップ
を用いて封止する。
A semiconductor element 2 is bonded to a support 5 made of a ceramic material that has been metallized and plated with Au. A for adhesive
U-Si alloy brazing material is used. The outer green 6 of the through hole of the base island is metallized and Au plated. The support 5 on which the semiconductor element 2 is spread is installed so that the semiconductor element 2 is inserted into the through hole through the Au-Sn brazing material ring 3b, and is bonded by pressing and heating. The part 3a directly below the element is made of an Au-Si alloy, and the area around the through hole is made of an Au-Sn alloy.
Since the melting point of the Au-Si alloy is about 100q0 higher than that of the Au-Sn alloy, the adhesive 3a will not melt when heated during the formation of the adhesive 3b. After the semiconductor element 2 is fixed to the semiconductor device substrate as described above,
After predetermined wire bonding is performed according to a conventional assembly process, a ceramic cap is used for sealing with Au-Sn brazing material.

以上のような組立方法を用いれば半導体素子に亀裂を生
じさせたり、また半導体素子がアイランドから僅かな外
力によって剥離するという不良が防げる。以上に第1,
第2の実施例を挙げて説明してきたが上記実施例は本発
明の実施例の一部にすぎず、本発明の請求範囲を制限す
るものでないことは当然である。
By using the above assembly method, it is possible to prevent defects such as cracks occurring in the semiconductor element or peeling of the semiconductor element from the island due to a slight external force. First of all,
Although the second embodiment has been described, the above embodiment is only a part of the embodiments of the present invention, and it is a matter of course that it does not limit the scope of the claims of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

図面はすべて本発明の実施例を示すもので、第1図は第
1の実施例の要部切断正面図、第2図は第2の実施例の
装置全体の切断正面図を示す。 なお図面について、1は基体アイランド「 2は半導体
素子、3は接着材、5は支持体、6は基体の貫通孔の外
側緑である。界’図 第2図
The drawings all show embodiments of the present invention; FIG. 1 is a cutaway front view of essential parts of the first embodiment, and FIG. 2 is a cutaway front view of the entire device of the second embodiment. Regarding the drawings, 1 is the base island, 2 is the semiconductor element, 3 is the adhesive, 5 is the support, and 6 is the green outside of the through hole of the base.

Claims (1)

【特許請求の範囲】[Claims] 1 支持体の上面に半導体素子を接着材にて固着させる
工程と、しかる後に半導体装置用基体に設けられた貫通
孔内に該半導体素子を挿入し該基体の底面と該支持体の
上面の該半導体素子が設けられていない部分とを接着材
にて固着させる工程とを有し、該貫通孔の側壁と該半導
体素子の側壁とが0.5mm以下になるよう設定されて
いることによって該基体の所定個所に該半導体素子を位
置せしめたことを特徴とする半導体装置の製造方法。
1. A step of fixing the semiconductor element to the upper surface of the support with an adhesive, and then inserting the semiconductor element into a through hole provided in the base for semiconductor device, and aligning the bottom surface of the base with the upper surface of the support. and fixing the part where the semiconductor element is not provided with an adhesive, and the side wall of the through hole and the side wall of the semiconductor element are set to be 0.5 mm or less, so that the substrate 1. A method for manufacturing a semiconductor device, characterized in that the semiconductor element is positioned at a predetermined location.
JP57070139A 1982-04-26 1982-04-26 Manufacturing method of semiconductor device Expired JPS606090B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57070139A JPS606090B2 (en) 1982-04-26 1982-04-26 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57070139A JPS606090B2 (en) 1982-04-26 1982-04-26 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP49119025A Division JPS5811736B2 (en) 1974-10-15 1974-10-15 Hand tie souchi

Publications (2)

Publication Number Publication Date
JPS57184225A JPS57184225A (en) 1982-11-12
JPS606090B2 true JPS606090B2 (en) 1985-02-15

Family

ID=13422936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57070139A Expired JPS606090B2 (en) 1982-04-26 1982-04-26 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS606090B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5811736B2 (en) * 1974-10-15 1983-03-04 日本電気株式会社 Hand tie souchi

Also Published As

Publication number Publication date
JPS57184225A (en) 1982-11-12

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