JPS5812614B2 - Multiprocessor connection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor connection method, and more particularly, to a multiprocessor connection method having a mask processor and a plurality of subprocessors.

Hierarchical control type processors are known in which a mask processor and a sub-processor are provided, relatively simple control of a controlled circuit is performed by the sub-processor, and complex control is performed by a master processor.

Usually, a plurality of sub-processors are provided for one mask processor.

It is necessary to exchange data such as information and instructions between the mask processor and the sub-processors.

Conventionally, for example, a special control circuit was provided in addition to the above-mentioned processor, and the operation of the mask processor and sub-processor was controlled by the control of this control circuit, and the data was exchanged.

For this reason, a relatively large-scale control circuit is required, and it is difficult to say that the data transfer is carried out efficiently and reliably. The present invention eliminates the above-mentioned drawbacks of the conventional method, which had drawbacks such as time wasted in processing and reduced processing capacity for the original processing, and instead consists of one mask processor and several sub-processors horizontally. In a multiprocessor system that uses multiple processors, it is possible to reliably transfer data between the master processor and each sub-processor, and to efficiently transfer data between processors in an orderly and efficient manner. The purpose is to shorten the time required and improve the processing efficiency of each processor.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a connection diagram of an embodiment of the present invention.

In the figure, MPU is a mask processor, MM is a main memory that operates together with the master processor MPU, MB is a main bus, MG MG SG, SG2 are gate circuits, RAM is a random access memory, INV is an inverter, SB is a sub bus, SPU#o, SPU#1・
...SPU#n is each subprocessor, So, 81
~Sl are controlled devices each monitored and controlled by one subprocessor SPU#o.

Note that each of the sub-processors SPU#1 to SPU#n is a controlled device S in the sub-processor SPU-#o.

, 81 to 81 are monitored and controlled.

A relatively small number of controlled devices S.

, S1 to S1 and a subprocessor S that monitors and controls these.
The PU#o is connected to the subprocessor SPU#o by a monitoring line for sending information about the controlled device, such as status information, to the subprocessor SPU#o and a control line for sending a control signal from the subprocessor SPU#o.

Here, the subprocessor SPU#o is the controlled device S described above.

, 81 to Sl, and if a change occurs in the state of the device, the information is received via the monitoring line, analyzed and processed, and based on this information, the sub processor SPU#o individually performs a predetermined process. When it is determined that the control is to be performed, without sending this information to the mask processor MPU,
A control signal is sent to the control line and the corresponding controlled device (So, 81~
The above-mentioned control is performed for S1).

After analyzing and processing the above information, the subprocessor S
PU #o does not control it, but processes it as common information in the mask processor MPU, and when it is determined that control is to be performed, this information data is passed to the master processor MPU.

The mask processor MPU performs processing using the main memory MM and creates control information.

This control information is sent from the mask processor MPU to the sub-processor SPU#o, and is sent as a control signal to the controlled device that sent the information to perform predetermined control.

Alternatively, as a control signal for another controlled device specified by the above information, it is sent to the specified controlled device via the sub-processors SPU#1 to SPU#n that accommodate the specified controlled device. It will be done.

Note that this control information is transmitted to the subprocessor S PU #o-
It is also possible to directly send it to a predetermined device without going through S PU#n.

Mask processor MPU and sub-processors SPU #1 to SPU #n for the above information data or control data
The data is transferred to and from the data via the random access memory RAM as described below.

Random access memory RAM includes each subprocessor S.
A fixed area is allocated to each PU #o-S PU # n, and each sub-processor S PU #
o=S PU# The data passed from n to the mask processor MPU and the data passed from the mask processor MPU to each sub-processor are written to and read from the area corresponding to the sub-processor.

FIG. 2 is an operation time chart of the embodiment shown in FIG.

A clock signal shown as CL in FIG. 2 is input to the clock signal input terminal CL in FIG.

As shown in FIG. 2, this clock signal CL has a first period T1 and a second period T2, and its output is "1" in the first period T1 and "0" in the second period T2. And this is repeated.

At the beginning of period T1, clock signal CL is ゜“1”.
If so, this is first given to the mask processor MPU as an interrupt signal IRQ, and also to the gates MG1,
It is given to MG2, which becomes open.

However, "1" of this clock signal CL is the inverter IN.
Since it is inverted by V and becomes "0", no interrupt (IRQ) is performed to subprocessor SPU#o.
Further, gates SG1 and SG2 are closed, and the sub-processor S PU #o-S PU # n is connected to the sub-bus S
Access to the random memory RAM via B is prohibited.

At the beginning of the period T1 of the clock signal CL, the mask processor MPU is interrupted as described above, so that the mask processor MPU accesses the random access memory RAM via the main bus MB and gates MG1 and MG2, and accesses the random access memory RAM. reads the data written from the sub-processor S PU #=o to the area allocated to the sub-processor S PU #o, thereby receiving the data from the sub-processor S PU =#=o, and further reading the data written from the sub-processor S PU #=o, The data to be passed from to the subprocessor SPU#o is written into the area.

The above processing is performed on each sub-processor SPU#0 to SPU#n.
Perform all of the steps in sequence.

The period T1 of the clock signal CL is selected to be slightly longer than this so as to sufficiently cover the time tm required for the above processing for all subprocessors.

In this way, when the mask processor MPU finishes the above processing and the clock signal CL enters the period T2, and the clock signal CL becomes "0", the gates MG1 and MG2
, these gates are closed, and the mask processor M
Access from the PU to the random access memory RAM via the main bus MB is prohibited, and the above "0" is inverted by the inverter INV to become "1", which is applied to the gates SG1 and S02, and these gates are opened. , furthermore, this signal “1” is sent to the subprocessor SPU#o
is given as an interrupt signal IRQ to sub-processor SPU#o, which causes sub-bus SB and gate SG
18G2, the random access memory RAM is accessed, and the mask processor MPU
reads the data written from the sub-processor S PU #o, thereby receiving the data from the mask processor MPU, and further reads the data written from the sub-processor S PU #o to the mask processor MP
Write the data to be passed to U into the area.

When the sub-processor SPU#o completes the above processing, it sends an interrupt signal IRQ to the next sub-processor SPU#1.

Next sub-processor SPU that received the interrupt signal IRQ
#1 performs the same processing as described above for subprocessor SPU#o, reads data to be passed from mask processor MPU to subprocessor SPU#1 from random access memory RAM, and sends data to subprocessor SPU#1.
The data to be passed from to the mask processor MPU is written into the random access memory RAM.

When this processing is completed, an interrupt signal is further sent to the next sub-processor SPU#2.

As mentioned above, the sub-processor SPU#o first accesses the random access memory RAM, and after the access is completed, the next sub-processors SPU#1 to SPU#n sequentially access the random access memory RAM.
Each sub-processor receives data from the mask processor MPU via the random access memory RAM, and also passes data to the mask processor MPU.

In the operation time chart of Fig. 2, SPU #o, S
PU#1 to SPU#n are each sub-processor SPU
#o indicates the timing at which SPU#1 to SPU#n access the random access memory RAM, and t3 in the figure indicates the time during access.

Here, the time period T2 is the time for all subprocessors SPU#0S.
The length is long enough for PU#1 to SPU#n to complete one round of access to the random memory RAM.

FIG. 3 is a connection diagram of an example of an electronic exchange constructed by applying the present invention.

The electronic exchange shown in FIG. 3 uses a plurality of subprocessors and one mask processor to monitor and control subscriber circuits and trunks according to the present invention, and simple processing such as call detection is performed by the subprocessor. , processing of complex common information such as call processing is performed by a mask processor.

In the figure, LC1, ~LC1m; LC21 ~LC2m
; LCl1 to LClm are subscriber circuits, NW is a communication path network,
T R K -TRI(rn: T R K
-TRK2 rn: ~:TRKp1~TRKpm are trunks, SPU#1, SPU#2~SPU#l, SP
U#1', SPU2' to SPU#p are sub-processors,
SPC is a communication path control device, and the other parts are the same as in FIG.

Note that the sub-processors SPU#, etc. are the controlled circuits S in FIG.

-Sl respectively monitor and control a relatively small number of m, for example eight subscriber circuits (LC11 to LC1m, etc.) or trunks (TRK1, to TRK1rn, etc.).

FIG. 4 will be explained by taking as an example the case of monitoring and controlling a subscriber circuit.

The subscriber circuit includes line relays and cutoff relays, although the functions and configurations thereof vary depending on the exchange.

FIG. 4 is a connection diagram showing the relationship between subscriber circuit LC11 and sub-processor SPU#1 in the above case.

In a stationary state (telephone Tea is on-hook)? If so, line relay L and cutoff relay CO in subscriber circuit LC11 are in the recovery state.

Now, if you make a call on the phone Tel and it goes off-hook, the ground, line relay L winding ■, contact CO1,
Telephone Tel, contact CO2, line relay L winding I1
, H is constructed, line relay L operates, and its contact l closes.

Through the contact l, the earth air is connected to the monitoring line S1 of the subscriber circuit LC11.
It is given to sub-processor SPU#1 via.

Sub-processor SPU#1 processes this earth signal by itself, sends a drive signal (earth air) to control line C11, and operates cut-off relay CO.

As a result, contacts C01 and C02 switch, and the telephone line Tel
The communication line extends to the communication network NW of the exchange.

The line relay L is restored when its operating circuit is cut off at contacts CO1 and CO2.

The subprocessor SPU#1 detects the accommodation position information of the calling telephone with respect to the exchange from the position of the monitoring line S1 that received the ground signal, adds the calling information to this, and adds the calling information to the information as explained in FIG. As in, random access memory RA
M to the mask processor MPU.

Upon receiving this, the mask processor MPU learns that the telephone Tea has made a call and performs subsequent call processing.

As shown in FIG. 3, a control signal is sent from the mask processor MPU to the communication path control circuit SPC, and the communication path control device SP
Using this control signal, C controls the communication path network NW to set a desired communication path.

The trunk TRK11 and so on are similarly monitored and controlled.

Since the detailed control of the exchange has little relevance to the present invention, the explanation will be limited to the example shown in FIG. 4 and other explanations will be omitted.

In FIG. 3, the data exchange between sub-processors SPU#1 and so on and mask processor MPU is performed in exactly the same manner as described with respect to FIGS. 1 and 2.

Although the embodiments and application examples of the present invention have been described above, the present invention is not limited to the embodiments and application examples described above, and various modifications and applications can be made within the technical scope thereof.

Since the present invention is configured as described above, it has the advantage that data can be transferred reliably and efficiently between one mask processor and a plurality of subprocessors.

Further, there is no need for an external control device to control each processor for data reception, etc.

The excellent effects described above can be achieved by applying the present invention to a case where an electronic exchange is controlled in two layers by a plurality of sub-processors and one mask processor.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram of one embodiment of the present invention, Fig. 2 is an operation time chart of Fig. 1, Fig. 3 is a connection diagram when the present invention is applied to control of an electronic exchange, and Fig. 4 is a FIG. 4 is a connection diagram showing the relationship between the subscriber circuit of FIG. 3 and a sub-processor; MPU...Mask processor, MM...
・Main memory, MB... Main bus, MG,
MG, MG2SG, SG1, SG2...Gate circuit, RAM...Random access memory,
■N■...Inverter, SB...Sub bus, SPU#o, SPU#1 to SPU#n...
・Sub-processor, So-Sl...controlled? Device, CL...Clock signal input terminal, LC1, ~
LClm...Subscriber circuit, TRK1 to TRKp
m...Trunk, NW...Call route network.

Claims (1)

[Claims] 1 A plurality of sub-processors each controlling a plurality of devices, a master processor processing the common information of the plurality of sub-processors, and a master processor controlling each of the sub-processors; a random access memory that can be accessed even in the event of a processor failure, and further has a repeating signal indicating a first period T1 and a second period T2, and in the first period of the signal, the mask processor By making the random access memory accessible, information passed from the master processor to each intermediate processor and information received from each subprocessor are written to and read from the random access memory, respectively, and in the second period of the signal, the Enables multiple subprocessors to access the random access memory,
Note that during the second period, at the beginning of the period, one sub-processor receives an interrupt signal from the above-mentioned signal, starts accessing the random access memory, and transfers the information and sub-processor from the mask processor to the sub-processor. The information to be passed from the processor to the mask processor is written to and read from the random access memory, respectively, and when the access of the subprocessor is completed, an interrupt signal is sent to the next subprocessor, so that the next subprocessor accesses the random access memory. A multiprocessor connection method characterized in that this process is repeated so that all subprocessors sequentially and continuously access the random access memory.