JPS5814107B2 - Received data detection method in data transmission - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a received data detection method for correctly detecting received data in data transmission.

In order to perform transmission and reception correctly in a serial transmission system, it is necessary to match the data sampling operation on the receiving side and the data transmission timing on the transmitting side.

If these operations are performed independently, there will be a very small error between transmission and reception, no matter how high the accuracy.

This error accumulates over time, and the initially consistent data sampling operation on the receiving side begins to deviate from time to time.

If the timing of this data sampling operation is shifted, information cannot be received correctly.

To prevent this lag between transmission and reception, it is necessary to match the timing of the data sampling operation on the receiving side and the data transmission operation on the transmitting side.

In other words, it is necessary to synchronize the receiving side and the sending side.

This synchronization method includes a partial synchronization method and a continuous synchronization method.

The most commonly used partial synchronization method is the start-stop synchronization method.

In the asynchronous type, the stop polarity is continuous in a non-communication state, and when data transmission is started, the start polarity precedes it, indicating that the transmission has started.

Therefore, the receiving side detects the change from stop polarity to start polarity, starts the data sampling timing function, and stops the timing function when the stop polarity is reached.

Since this method adds a start polarity and a stop polarity to each character, it has the disadvantage that the transmission efficiency is lower than that of the continuous synchronous transmission method.

On the other hand, the continuous synchronization method is a method in which data from the transmitting side and a timing clock indicating the bit boundaries of this data are transmitted together, and it is necessary to provide a timing line separately from the data line.

In addition, the device (MODEM) is more expensive and complicated than the partial synchronization method.
etc.) have to be used.

Therefore, the present invention is intended to improve the above-mentioned drawbacks of the prior art, and its purpose is to eliminate the need for timing lines and expensive equipment as described above in continuous synchronization reception with good transmission efficiency, and to provide It is an object of the present invention to provide a simple method for detecting received data in data transmission, which is not easily affected by mixed noise and generates a clock for correctly sampling the received data by detecting a change in the polarity of the received data.

A feature of the present invention for achieving this object is that, in a method for detecting binary received data in data transmission, an N-ary counter is provided that is incremented by a clock that is N times the communication speed (N is a natural number), and A constant Ak corresponding to the contents of the counter at the moment when the polarity of data changes is stored, and when the contents of the counter are incremented to N0Ak, the counter is cleared and the increment operation for the next data is performed. The method is to sample the received data pit at the moment the counter is cleared.

Examples will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a block diagram of a received data detection device according to the present invention, where 1 is a received data input, 2 is a clock input 32 times the communication speed, and 3 is a clock input 2.
4, 5, 6, 7, 8.9 are J-K type flip-flops forming counter 3; 10, 11, 12, 13;
is an AND gate that constitutes counter 3, 14, 15, 1
6, 17, 18, and 19 are clock input 2, respectively.
2, 1/4, 1/8, 1/16, 1/
3 2, 1/64 divided output, 20 is counter 3
The circuit decoding the outputs 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25 are the counters 3
The count values of ``30'', ``31'' and ``32'' are respectively
26 is a negative gate that inverts the polarity of clock input 2, 27 is a D-type flip-flop for detecting the polarity change of received data input 1, and 28 is a receiving circuit. Exclusive OR gate for detecting polarity changes in data input
, 29 is an output that becomes "1" when a change in polarity of received data input 1 is detected, and 30.31 is a D type that stores the state of outputs 18 and 17 of counter 3 when the polarity of received data input 1 changes. A flip-flop 32 is a D-type flip-flop that stores the change in polarity of the received data input 1, and 33 is an arithmetic circuit that realizes the functions shown in the table below.
34 is an AND gate that outputs "1" when the count value of counter 3 changes from "0" to "7" and the count value of counter 3 reaches "30" when the polarity of received data input 1 changes; 35 is an AND gate of reception data input 1, which outputs "1" when the count value of counter 3 changes from "8" to "15" and becomes "31" when the polarity changes, 36 is an AND gate that outputs ゜'1'' when the polarity of received data input 1 does not change and the count value of counter 3 becomes "32", and 37 is an AND gate that outputs ゜'1'' when the polarity of received data input 1 changes. An AND gate that outputs "1" when the count value of counter 3 becomes "33" from "16" to "24", and 38 is the count of counter 3 when the polarity of received data input 1 changes. The AND gate outputs "1" when the count value of Count 3 reaches "34" from "24" to "31", 39 is the AND gate output 34, 35
, 36, 37, and 38; 40 is the output of the OR gate 39; 41 is an OR gate that outputs "1" when the count value of the counter 3 is 16'' or more;
2 is a clock output for sampling received data.

Next, the operation of this embodiment will be explained.

The table below shows the relationship between the count value (CNT) of the counter 3 at the moment when the polarity of the received data input 1 changes, the constant (Ak) corresponding to this count value, and one cycle time of the received data sampling clock.

Now, when the polarity of received data input 1 changes at the time when received data input 1 is 43 in FIG. 2A (the content of counter 3 is 4), the content of counter 3 and the sample output 42
is as shown in Figure B.

At this time, when the clock input 2 falls, the output 29 becomes "1" and the flip-flops 30, 31, and 32 are set to "0".
”, “0”, and “1” are stored, and when the count value of counter 3 reaches “30”, the output 40 becomes “1” (A
k=-2), all flip-flops of the counter 3 are cleared and the received data sampling clock output 42 becomes "0" (see 44 in FIG. 2).

Therefore, the clock output 42 for sampling received data is 1.
The period becomes a pulse 30 times that of clock input 2.

At this time, the flip-flops 30, 31, and 32 are also cleared, so the output 40 becomes "0" and the circuit of FIG. 1 returns to its initial state and starts operating again.

The width of one pulse of the received data is approximately equal to 32 clocks of the counter 3, so the content of the counter 3 at the moment when the polarity of the received data changes in the next cycle is approximately 6, and in the next cycle it is 8. becomes.

Furthermore, in each subsequent cycle, the contents of the counter at the moment of polarity change will be 9-15.

When the number of squares becomes 16, Ak=+1, so the value of counter 3 becomes 15 in the next cycle.

That is, in a steady state, the content of the counter 3 at the moment of polarity change is around 15-16.

Therefore, by sampling at the moment when the counter 3 is cleared (timing 44 in FIG. 2), the median value of the pulses of the received data can be correctly received.

Further, when the received data input changes at time 45 in FIG. 2A, the contents of the counter 3 and the sample output 42 become as shown in FIG. 2C.

At this time, "1", "0", and "1" are stored in the flip-flops 30, 31, and 32, respectively, and when the count value of the counter 3 reaches "33", the output 40 is stored in all the flip-flops of the counter 3 and the flip-flops 30 and 32. ,31
．． 32 is cleared, and the received data sampling clock output 42 outputs a pulse whose period is 33 times that of the clock input 2 (Ak=+1).

At this time as well, the contents of the counter 3 at the moment when the polarity of the received data changes will vary from 15 to 1 as the cycle progresses.
6.

Therefore, if the received data is sampled at the moment when the counter 3 is cleared, the center of the received pulse can be sampled.

Also, if received data input 1 does not change (4 in Figure 2)
FIG. 2D shows the counter 3 and sample output of the counter 3 (see 6).

When the count value of counter 3 is “32” (Ak=0)
The output 40 clears all the flip-flops of the counter 3, and the received data sampling clock output 42 outputs a pulse whose period is 32 times that of the clock input 2.

At this time as well, the median value of the received data is sampled at the moment when the counter 3 is cleared.

Therefore, if the reception data input 1 is sampled at the falling edge of the reception data sampling clock output 42 (at the moment when the count 3 is cleared), the reception data can be correctly received in any case.

As explained above, the received data detection method in data transmission of the present invention detects a change in the polarity of received data and samples the received data correctly based on the counter value at this time, so the continuous synchronization method is more efficient in transmission. can be applied, and there is no need to provide a timing line separate from the data line, and no expensive equipment is required.

It also has the advantage of being less susceptible to noise mixed in received data and can be realized with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a received data detection device according to the present invention, and FIG. 2 is an explanatory diagram of the operation of the device shown in FIG. 1...Receive data input, 2...Clock input, 3...6
Bit count, 4, 5, 6, 7, 8, 9...J-K type flip-flop, 10, 11, 12, 13...AND gate, 20...Decoder, 26...Negation gate, 27
, 30, 31, 32...D type flip flip, 28...
...Exclusive OR gate, 33... Arithmetic circuit, 3
4, 35, 36, 37, 38...and gate, 39,
41...OR gate, 42...Clock output for sampling received data.

Claims (1)

[Claims] 1. In a method of detecting binary received data in data transmission, an N-ary counter is provided that is incremented by a clock that is N times the communication speed (N is a natural number), and when the polarity of the received data changes, the value of the counter at that moment is A constant Ak corresponding to the content is memorized, and when the content of the counter is incremented to N+Ak, the counter is cleared and the increment operation for the next data is started, and the moment the counter is cleared, the received data is A method for detecting received data in data transmission, characterized by sampling pits.