JPS6255745B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an NRZ code receiving device, and an object of the present invention is to extract a timing component from a received NRZ encoded signal and perform identification and reproduction of the NRZ signal.

Conventionally, data highways use two positive and negative pulses as transmission path codes, as shown in Figure 1, and to send a logic "1", the pulses are sent in order from positive to negative, and the logic "0" is sent. To send ", a dipulse code (a type of biphasic code) is used, which sends out signals in reverse order from negative to positive.

One of the reasons why the dipulse code is used is that it is easy to extract timing components. Figure 2 is a diagram for explaining this, where a is a signal sequence, b
is the signal waveform when using the dipulse code, c
is the differential output of the signal waveform of b, and d is a repetitive pulse sequence with a period equal to the transmission period among the differential outputs of c. As shown in Figure 2c, there is one or more pulses per bit in the differential output of the dipulse encoded signal, and as shown in Figure 2d, the transmission period is There exists a synchronous pulse sequence equal to . That is, since it contains many of the same spectral components as those at a transmission rate of ₀ Hz, the timing component can be easily extracted by passing it through _a high Q filter (for example, realized by a PLL) having a center frequency of 0 Hz. However, as mentioned above, the dipulse code uses two pulses to transmit one bit of information, so the occupied bandwidth becomes large.
This is undesirable due to the bandwidth of the transmission path.

Incidentally, the NRZ code is an example of a transmission line code whose occupied bandwidth is about half that of the dipulse code. However, the power spectrum of the NRZ-encoded signal has fewer frequency components equal to the transmission speed, and it is difficult to extract the timing component from the NRZ-encoded signal, making it more reliable than the NRZ-encoded received signal. The disadvantage of this method is that it requires a complicated circuit for accurate identification and reproduction.

The present invention aims to eliminate the above-mentioned drawbacks, and embodiments of the present invention will be described below with reference to the drawings.

In FIG. 3, 1 is a differentiating circuit, 2 is a latch circuit, 3 is a delay circuit that delays the received NRZ encoded signal in order to have the received NRZ encoded signal in the correct phase and latched by the latch circuit 2, and 4 is a received NRZ encoded signal.
Set the transmission rate of the NRZ encoded signal to ₀ bps (T(S) =
When _1/0 (bps) (2N ₁ ) Hz { ₁
and ₀ are approximately equal, and N is a positive integer}. 5 is a counter that counts the number of clock signals 1 and CK1. The counter 5 is cleared. When 3N clock signals 1 and CK1 are counted from the state (counter value is 0), a carry pulse is output. The carry signal becomes logic "1" for one clock. Due to the carry pulse, counter 5 has
A value N is preset. After this, when 2N clock signals 1 and CK1 are further counted, the value of the counter 5 becomes 3N, and a carry pulse is output. Unless cleared, counter 5 operates as a 2N-base counter.

6 is when the value of the counter 5 reaches N,
Logic gate with logic “1”, 7 is OR gate,
8 and 12 are flip-flops. The JK terminal of the flip-flop is pulled up. 9
is a phase comparison circuit, 10 is a filter, and 11 is a phase comparison circuit.
A VCO (voltage controlled oscillator) supplies clock signals 2 and CK2 with a frequency of ₂ and a transmission rate close to ₀ . In reality, ₀ = ₂ since clock signal 2 is synchronized with the received NRZ encoded signal.
The phase comparison circuit 9, filter 10, VCO 11, and flip-flop 12 constitute a PLL.

The output of the differentiating circuit 1 is input to the clear terminal of the counter 5, the carry signal of the counter 5 is input to the load terminal of the counter 5 and the OR gate 7, and the oscillation circuit 4
The clock signals 1 and CK1 are input to the clock terminal of the counter 5.

Next, the operation of the receiving circuit shown in FIG. 3 will be explained together with the timing chart shown in FIG. 4.

The differentiating circuit 1 differentiates the received NRZ encoded signal shown in FIG. 4a, and outputs a differentiated pulse at a change point of the received NRZ encoded signal, as shown in FIG. 4b.

When the counter 5 is cleared by the pulse from the differentiating circuit 1, the counter 5 counts the clock signals 1 and CK1 shown in FIG. 4i from 0.
For example, when the counter 5 is cleared by the differential pulse _S1 of FIG. 4b, the counter 5 starts counting from zero. After about T/2 seconds, the value of the counter becomes N and the pulse shown at _S2 in FIG. 4c is passed from the logic gate 6. The counter 5 continues to count, but after T seconds from being cleared by the differential pulse S ₁ , the counter value becomes approximately 2N, and at that time, the differential pulse
The counter 5 is cleared again by _S3 and counts the clock signals 1 and CK1. Approximately T/2 seconds after clearing by the differential pulse _S3 , the value of the counter 5 becomes N again, and the pulse shown at _S4 in FIG. 4c is output from the logic gate 6. but,
This time, T/2 seconds after the _S4 pulse is output, there is no differential pulse, and the counter 5 continues counting. Approximately T seconds after the pulse _S4 , the value of the counter becomes 3N, and due to the carry, the carry pulse _S5 shown in FIG. 4d is output. This pulse presets the counter 5 to the value N.
Clock signals 1 and CK1 are counted using the value N as an initial value. However, about T/2 from the carry pulse S ₅
After seconds, it is cleared by the differential pulse S ₆ of FIG. 4b.

In this way, the output of the logic gate 6 as shown in FIG. 4c and the carry signal of the counter 5 as shown in FIG. 4d are obtained.

From OR Gate 7, as shown in Figure 4e,
The output of the logic gate 6 and the carry signal are logically summed and output.

The output of the OR gate 7 serves as a clock for the flip-flop 8, and the flip-flop 8 provides the frequency-divided output shown in FIG. 4f.

As shown in _FIG .
is outputting. The output is frequency-divided by the flip-flop 12 to produce an output as shown in FIG. 4g.

The output signal of the flip-flop 12 and the output signal of the flip-flop 8 are input to a phase comparator circuit 9 to obtain a signal output proportional to the phase difference, which is input via a filter 10 as a control voltage of the VCO 11.

The output of the OR gate 7 is synchronized with the received NRZ encoded signal, but contains a lot of jitter. This jitter is removed by the phase comparator circuit 9, filter 10, VCO 1
1. A stable clock signal 2, CK2 is obtained from the output of the VCO 11 by suppressing it by a PLL consisting of a flip-flop 12.

The delay circuit 3 adjusts the phase of the received NRZ code signal, inputs it to the latch circuit 2, and latches it with the clock signals 2 and CK2 with less jitter, thereby identifying and reproducing the NRZ signal.

As described above, according to the present invention, a repetitive pulse sequence synchronized with the received NRZ encoded signal can be obtained using a simple logic circuit, and by passing this pulse sequence through the PLL, a stable clock signal with less jitter is regenerated. By using this clock signal as the latch signal of the latch circuit, it is highly reliable.
It is possible to perform identification and reproduction of NRZ encoded signals.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams for explaining the conventional example. Figure 1 is a waveform diagram of a dipulse code signal;
The figure is a diagram for explaining a method of extracting a timing component from a dipulse encoded signal, FIG. 3 is a block diagram of an NRZ code receiving apparatus in an embodiment of the present invention, and FIG. FIG. 3 is a signal waveform diagram of each part of the embodiment. DESCRIPTION OF SYMBOLS 1...Differential circuit, 2...Latch circuit, 3...Delay circuit, 4...Oscillation circuit, 5...Counter, 6...Logic gate, 7...OR gate, 8, 12...Flip-flop, 9...Phase comparison circuit, 10...Filter, 11 …
VCO (voltage controlled oscillator).

Claims (1)

[Claims] 1. A means for outputting a differential pulse corresponding to a change point in the level of the signal from a received signal of the NRZ code transmitted at a transmission rate _{of 0} bps, and a means for outputting a differential pulse corresponding to the change point of the signal level, and
₁ ( ₁ ≒ ₀ , N is a positive integer), the clock signal is counted as the first input, and if the value becomes 3N, a carry pulse is output, and this carry The pulse presets the value N and counts until it is cleared.
It operates as a 2N-based counter, and is cleared by this pulse using the differential pulse as the second input, and inputs the counting means again from the value 0 and the output of this counting means to confirm that the number of counted pulses is the N value. A means for detecting N to detect, an OR means receiving as input the output of the detecting means and the carry pulse of the counting means, a jitter suppressing means receiving as input the output of the logical sum means, and the jitter suppressing means 1. An NRZ code receiving apparatus comprising a latch means receiving an output of the NRZ code and a received signal of the NRZ code as input, and performs identification and reproduction of a received NRZ encoded signal.