JPS581434B2 - Raster Scanning Dotsto Character Display Souch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rask-scan type dot character display device in which the display storage area of an external memory and the screen display format can be specified. The present invention proposes a character display device that is capable of continuously reading out a display storage area of 1 and displaying it in accordance with a specified format.

Conventional character display devices usually have memory for the maximum number of digits that can be displayed as a display buffer.
Formatting, that is, manipulating the position occupied by display data on the screen, was performed using a cursor that moved column by column or line by line.

However, in such a case, the trouble of having to perform a cursor operation every time data is inserted cannot be avoided.

Furthermore, it is preferable to prepare display buffers for the maximum number of digits that can be displayed, but when trying to use them for other purposes, the display capacity (number of display digits and lines) This causes an excess or deficiency in the number of

Further, as a display buffer, a shift register is often used from the viewpoint of cost, but in this case, as the display capacity increases, the access time also increases, which is disadvantageous in terms of use.

Therefore, it is an object of the display device of the present invention to overcome the drawbacks of the conventional device by improving operability and saving display buffer memory.

That is, the display device of the present invention has only a shift register called a line buffer, which has the maximum possible number of digits for one line, as a display buffer, and uses DMA (direct memory) to store display data. access)
Assuming the use of a functional external memory, the display device must have a storage area for display in the external memory, as well as its display capacity (display digits and number of lines) and format (display data occupied on the screen). It has the only function that allows you to specify the location).

With this configuration, editing operations for data display are facilitated, and the capacity of external memory for accommodating display data is reduced to the minimum necessary.
A further feature is that external memory addresses can be accessed using consecutive addresses regardless of the format on the screen.

Next, the display device of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of the apparatus of the present invention.

In the drawing, 1 is a display start address register, which is a register for specifying the first address of an external memory used as a buffer for display data.

2 is a cursor address register, which is used to display a cursor mark on the display screen, and when the external memory is within the address range specified as the display data buffer, the cursor is moved to the corresponding position on the screen. Display mark.

Reference numeral 3 designates an address counter which starts from the address specified by the display start address register 1 and increments by the specified display capacity to scan the external memory for display data.

Numeral 4 is a digit counter, which operates together with the address counter 3 in clock cycles of the external memory when writing display data from the external memory to the line buffer 8. During display, it operates in accordance with the scanning cycle of the display device and controls the circulation of the line buffer 8. Synchronize.

The base number (M digits) of this digit counter 4 is the line buffer 8
be equal to the number of digits in

A line counter 5 indicates the number of lines displayed on the screen, and has a base number (N lines) corresponding to the maximum number of lines displayed on the screen.

6(a, b) are digit format registers and display start and end registers, which are shift registers with a number of bits equal to the number of digits of the line buffer 8, and each bit is made to correspond to each digit of the corresponding line buffer 8. There is.

This digit format register 6a moves data from external memory to line buffer 8 when the corresponding bit is "1", and inserts a space (Sf) or black (BL) into line buffer 8 when it is "0". .

In addition, the display start and end register 6b has a bit “1” corresponding to the digit that starts and ends the display on the screen.
", and the others are "0".

Reference numerals 7(a, b) are row format registers and display start and end registers, which perform the same operations with respect to rows as the digit format register and display start and end registers 6(a, b) described above.

Reference numeral 8 denotes a line bus sofa, which can accommodate one line of display data (M digits) and operates with different clock pulses for data write cycles and display cycles.

That is, in the write cycle, it is operated by a clock pulse of the external memory, and one line of display data is written under the control of the digit format register 6a and the display start and end registers 6b.

In addition, in the display cycle, the display device operates in the scanning cycle of the display device, and cycles as many times as necessary for display.

A format control register 9 compares the cursor address register 2 and the address counter 3 with a comparator 10, and uses the detected timing to control the digit and row format register 6a.
, 7a are registers for setting the display start and end registers 6b and 7b.

A comparator 10 compares the cursor address register 2 and the address counter 3, sets digit and line format registers 6a, 7a, display start and end registers 6b, 7b in the write cycle, and sets the display start and end registers 6b, 7b. Now, detect the timing of displaying the cursor mark.

Reference numeral 11 denotes a timing control section, which generates timing pulses necessary for the device.

Further, 12 is a DMA channel, and 13 is a condition set bus.

The basic operation of the Rusk scan type dot character display device of the present invention will be explained as follows.

In this device, the period during which the lines on the screen are scanned is called a writing cycle, and the period during which characters are displayed on the screen is called a display cycle.

The reference (starting point) of each cycle is the horizontal synchronization pulse, and in the write cycle, the clock pulse of the external memory is used as the clock pulse, and in the display cycle, the effective period of horizontal scanning is determined by the number of digits and the number of dots in the horizontal direction. It operates with a divided clock.

When the device is powered on, all registers are cleared, and the maximum number of digits in the line buffer 8 is set by the digit counter 4 as the number of displayable digits.

Column and line format registers 6a and 7a and display start and end registers 6b, which are the main parts of the device of this invention.
Setting 7b is performed by the following operation.

(1) First, set display start address register 1.

Next, set cursor address register 2.

The addresses of both registers 1 and 2 determine the position of the cursor on the screen.

For example, if display start address register 1 is set to 500 and cursor address register 2 is set to 502, the cursor position will be three digits from the leftmost digit on the screen.
It is expressed as the difference between both addresses, such as the th address (however, it goes without saying that the condition of display start address≦cursor address must be satisfied).

(2) Next, set format control register 9.

This register 9 consists of 4 bits for one digit, and the data
Specify columns and rows for buffer control.

The first bit corresponds to the digit format register 6a, and the second bit corresponds to the digit display start and end register 6a.
Corresponds to b.

Also, the third bit is the row format register 7a.
The fourth bit corresponds to the line display start and end register 7b.

When these four bits are "1", they set their corresponding registers 6a, 6b, 7a, and 7b, respectively.

(3) Clear format control register 9.

In order to explain the operations (1) to (3) in more detail, their relationship is shown in FIGS. 2A and 2B.

That is, in FIG. 2A, digit format register 6
a, the display start and end registers 6b, the line format register 7a, and the display start and end registers 7b are shown in relation to the display screen, and FIG. 2B shows the main memory address in that case. are shown correspondingly.

14 in FIG. 2A is a displayable area of the display screen, and when displaying data such as a1 to a88 in the format shown in the figure, the digit format register 6
A and line formant register 7a set the corresponding columns and rows to "1", and digit display start and end registers 6b and line display start and end registers 7b set the start and end, respectively. Set the corresponding column and row to "1".

This specifies the display column, display line, and format of the display screen.

That is, the displayable area 14 is represented by two coordinates: a digit format register 6a and a line format register 7a, and these two registers 6a and 7a are both "1".
” The data will be displayed at the position set.

Also, from the relationship between the digit display start and end registers 6b and the line display start and end registers 7b, these four registers 5a
, 6b, 7a, and 7b are all set to "1" a1
Writing of data to the line buffer 8 is controlled by the format control register 9 shown in FIG. 1 so that the display starts from the position .

Writing to line buffer 8 in the read cycle is as follows:
All four registers 6a, 6b, 7a, 7b are "1"
After being set and started, two registers 6a,
This is performed only for addresses corresponding to locations where both 7a are set to "1".

Then, writing for one line ends at the digit position where all four registers are set to "1".

In this case, data written from consecutive addresses in the memory 15 is transferred to the line buffer 8 only at locations where both the digit format register 6a and the row format register 7a are set to "1"; At the position, the line buffer 8 becomes a space (SP).

In the next display cycle, the data in the line buffer 8 written in this read cycle is displayed on the display screen using a character generator.

By such read cycle and display cycle, 1
Once a line has been displayed, a cycle for reading and displaying the next line is started.

Then, display up to the preset line is performed.

The relationship between these operations and the main parts of the device will be explained in more detail with reference to FIG. 1 as follows.

Access to the external memory is made through the DMA channel 12, starting from the address set in the display start address register 1 and being accessed successively by the address counter 3 up to the address where the data required for display is stored. be exposed.

The data is then written to the line buffer 8.

On the other hand, the display position on the display screen is determined by a digit counter 4 that can count the maximum number of display digits (M digits) on the display screen, and a line counter that can count the maximum number of display lines (N lines). It is determined by the combination with 5.

That is, the two counters 4 and 5 start from "1", and when the digit counter 4 advances to the maximum value "M", the first row ends, then the digit counter 4 returns to "1", and the row continues. Counter 5 advances to "2".

Then, when the digit counter 4 advances to "M", the second row ends, the digit counter 4 returns to "1" again, and the row counter 5 advances to "3".

Such repetition is performed until the line counter 5 reaches 1N'', and all display positions on one display screen are designated.

In the display device of the present invention, four registers 6a, 6b,
7a and 7b are provided.

Digit format register 6 corresponds to digit counter 4
A and digit display start and end registers 6b are provided.
The digit set to "1" in FIG. 1 is the position where data is actually displayed within the display capacity of the display screen.

In this case, digit format register 6a is "1".
The second to Kth digits set to "O" are displayed, and digits set to "O", such as the sixth digit, are not displayed.

Similarly, a row format register 7a and a row display start/end register 7b are provided corresponding to the row counter 5, and among the second to Nth rows, the row format register 7a is " Data is displayed only for the rows set to "1".

As already explained with reference to FIG.
Writing is performed to the line buffer 8 having the number of digits for one line so that only the digits set to "1" can be displayed.

This writing is performed to the line buffer 8 at a timing corresponding to a display position on the display screen that is sequentially designated by a combination of the digit counter 4 and the line counter 5.

That is, writing to line buffer 8 is performed using column and row format registers 6a, ? Both a are “1”
The gate is opened as per the timing set to , otherwise the gate remains closed.

Therefore, from DMA channel 12 to line buffer 8
The data that is continuously sent to the line buffer 8 is sequentially written only at the timing when the gate of the line buffer 8 is opened, and is displayed in a desired format.

In addition, in the case of cursor display, if the address is set in cursor address register 2, comparator 1
A cursor mark can be displayed by comparing the address counter 3 with 0 and detecting the timing.

As described above, the display device of the present invention uses four registers 6a, 7a, 6b, and 7b to specify the display capacity and format of the display screen, and by setting these in advance, The data at consecutive addresses a1 to a88 of the main memory 15 shown in FIG. 2B can be displayed in a format as shown in FIG. 2A.

Although the addresses a3 and a4, a8 and a9, a11 and a12, etc. in FIG. 2A are consecutive in the main memory 15, they are displayed at separate positions on the screen.

Therefore, there is a space (S) for formatting.
P) Code packing can be kept to the minimum necessary, and the number of digits in the external memory can also be reduced compared to the conventional method.

With such a relatively simple configuration, it is possible to obtain a display device that is easy to operate and suitable for various uses, thereby achieving the excellent effect of significantly expanding its range of use.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of the display device of the present invention, and FIG. 2A shows the digit format register 6a, display start and end registers 6b, line format register 7a, display start and end registers 7b, and display. The relationship with the screen is shown, and FIG. 2B also shows the addresses of the main memory in the case of FIG. 2A correspondingly. In the drawing, 1 is a display start address register, 2 is a cursor address register, 3 is an address counter, 4 is a digit counter, 5 is a line counter, 6a and 6b are a digit format register and a digit display start and end register. 7
a and 7b are line format registers and line display start and end registers, 8 is a line buffer, 9 is a format control register, 10 is a comparator, 11 is a timing control section, 12 is a DMA channel, and 13 is a condition center. 14 is a displayable area of the display screen, and 15 is a main memory.

Claims (1)

[Claims] 1 Column and line display start and end registers for arbitrarily specifying and setting the display capacity determined by the number of display digits and lines of the display screen, and the display screen set in these display start and end registers. A column and line format register for arbitrarily specifying and setting the position occupied by each display data within the screen, a line buffer sofa with a capacity for the maximum number of digits that can be displayed on the screen, and an external memory address. An address counter that is continuously accessed and a format control register that selects only the display position set in the column and row format register and writes data from an external memory to the line buffer sofa. Rusk scan dot character display device featuring: