JPS5815969B2 - FET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rush current prevention circuit for an FET (field effect transistor) amplifier used, for example, in an audio output amplification stage of an audio device.

Figure 1 shows an example of an audio output stage in which FET II and 12 are connected in a single-ended push-pull manner.
When the FETs 11 and 12 are each of the N-channel type, they are configured such that a negative bias voltage is supplied to each gate electrode with respect to each corresponding source electrode in a steady state of operation.

That is, for example, FET 11 in class B push-pull operation.
The bias voltage of 12 is close to the cutoff, but this bias voltage is FETI 1 .

When the gate of 12 and the excitation stage and bias circuit 13 are directly connected, the voltage is obtained by the operation of the bias circuit 13 described above, and when they are not directly connected, an appropriate voltage dividing circuit etc. Not shown.

). In addition, 15 in the figure is a power transformer,
16 is a positive and negative voltage supply power source, and 17 is an output load circuit.

Incidentally, in the FET amplifier as described above, the rise of the bias voltage is delayed compared to the rise of the power supply voltage when the power is turned on.

Therefore, when the power is turned on, the bias voltage becomes shallow temporarily.

Therefore, if FETs 11 and 12 are used that exhibit low resistance at zero bias and allow a large current to flow, a large transient current, so-called rush current, will flow when the power is turned on.

In particular, in the case of FETs that have current unsaturated triode characteristics with low internal resistance, the rush current is extremely large, which causes the power supply voltage to rise more slowly and the rush current to flow for a longer time. There was a risk of damage to the FBT.

The present invention has been made to eliminate the above-mentioned drawbacks. Rush current is prevented by pulling the gate voltage of the FET in the cutoff direction until the bias voltage of the FET reaches a steady value after the power is turned on. The present invention provides a rush current prevention circuit for an FET amplifier that can prevent damage to the FET.

An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 2 shows the present invention in a complementary type push-pull F.
This is applied to an ET amplifier, and 51 is a rush current prevention circuit.

Further, a predetermined positive voltage is applied to the first current terminal 52, and a predetermined negative voltage is applied to the second power supply terminal 53.

Then, an N-channel type FET 54 is connected to the first power supply terminal 52.
The source electrode of the P-channel FET 55 is connected to the second power supply terminal 53.

The source electrode of the FET 55 and the source electrode of the FET 55 are respectively connected to an output terminal 58 via resistors 56 and 57.

This output terminal 58 is grounded via an output load circuit 59.

The gate electrodes of the FETs 54 and 55 are connected to an excitation stage and bias circuit 62 via resistors 60 and 61, respectively.
It is connected to the.

Note that the bias voltage of the FETs 54 and 55 is given by the bias circuit 62 a value close to the cutoff during steady operation.

In the rush current prevention circuit 51, resistors 63 and 64 are connected between the first power terminal 52 and the second power terminal 53.
, a capacitor 65, and a resistor 66 are connected in series in this order.

The connection point between the resistor 64 and the capacitor 65 is connected to the first power supply terminal 52 via a resistor 6γ, a diode 68 in the forward direction, and a Zener diode 69 in the reverse direction.
It is connected to the.

Further, the connection point of the resistors 63 and 64 is connected to the base of the PNP type transistor 10.

The collector of this transistor 70 is connected in the forward direction to the gate electrode of the FE'r 55 via a diode 71 and to the second power supply terminal 53 via a resistor 72.

On the other hand, the connection point between the capacitor 65 and the resistor 66 is connected in the opposite direction to the second power supply terminal 53 via a diode 73 and directly to the base of an NPN transistor 74.

The emitter of this transistor 74 is connected to the second power supply terminal 53
The collector is connected to the first power supply terminal 52 via a resistor 75, and in the opposite direction to the gate electrode of the FET 54 via a diode 76.

In the rush current prevention circuit 51, when the power is turned on, the first power supply terminal 52 is connected to the emitter terminal of the transistor 70.
Between bases → resistor 64 → capacitor 65 → transistor γ
A charging current flows through the path between the base and emic of the battery 4→the second power supply terminal 53.

As a result, transistors 70 and 74 are both turned on, and diodes 71 and 76 are forward biased and turned on.

As a result, each gate of FETs 55 and 54 is pulled in the direction of the cutoff voltage, thereby preventing rush current.

In this case, the time period during which the transistors 70 and 74 are in the on state can be appropriately selected depending on the time constants of the resistor 64 and capacitor 65.

In the steady state of operation, charging of the capacitor 65 is completed and the transistors 70 and 74 are not supplied with base current and are turned off.

Therefore, the diodes 71 and 76 are biased in the opposite direction and turned off, and the rush current prevention circuit 51
is completely isolated from the signal path of the FET amplifier and does not affect the amplification operation.

Note that resistor 67, diode 68, Zener diode 6
The series circuit 9 and the diode 73 are for quickly discharging the charge in the capacitor 65 when the power is turned off, so that the rush current prevention circuit 51 operates normally even if the power is repeatedly turned on and off.

In addition, in the Zener diode 69, the capacitor 65 performs charging and discharging operations due to ripples and fluctuations in the power supply voltage in a steady state of operation, and as a result, the transistor 70. This is to prevent malfunctions such as instantaneous ON operation of γ4.

According to the above configuration, transistors 70 and 74 are simultaneously controlled by the charging current of one capacitor 65.

Therefore, rush current in the FETs 54 and 55 can be simultaneously prevented stably and reliably.

Furthermore, since the capacitor 65 is shared by the transistors 70 and 74, the number of parts can be reduced.

As described in detail above, the present invention can prevent rush current and damage to the FET by pulling the gate voltage of the FBT in the cutoff direction until the bias voltage of the FET reaches a steady value after power is turned on. A rush current prevention circuit for FET amplifiers can be provided.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a conventional FET amplifier, and FIG. 2 is a configuration explanatory diagram showing an embodiment of a rush current prevention circuit for an FET amplifier according to the present invention. 51... Rush current prevention circuit, 52, 53.
...First and second power supply terminals, 54, 55...
...FET. 70.74...Transistor, 64...
・Resistance, 65...Capacitor, 71.76.6
8, 73, 69... Diode.

Claims (1)

[Claims] 1 N-channel, P connected between the first and second power supply terminals and forming a complementary push-pull amplifier
A channel FBT, a PNP transistor whose emitter and collector are connected between the first and second power supply terminals, an NPN transistor whose collector and emitter are connected respectively, and a resistor between the bases of both transistors. The first and second power supply terminals are connected in series between the first and second power supply terminals via resistors that flow bias currents to the bases of both transistors.
A capacitor through which a charging current flows until the bias voltage of the ET reaches a steady-state value; diodes are connected between the gates of the first and second FETs and conductive according to the charging current to pull the gate voltages of both FETs in the cutoff direction; 1. A rush current prevention circuit for an FET amplifier, comprising a power supply terminal and a discharge diode connected between the other end and the second power supply terminal.