JPS5816544B2 - magnetic recording and reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording/reproducing device with a plurality of N channels.

As is well known, this type of device is used in the following manner.

1) A method in which signals from a large number of microphones or signal sources are distributed into N-channel signals using a control console, etc., and recorded on an N-channel magnetic recording/reproducing device (tape recorder).

2) Record a rhythm or timing signal on one channel and then record other signals on other channels while playing back that signal.

This recording method is repeated many times until the recording of N channels is finally completed.

Play back the N-channel recorded tape created by methods 1) and 2) above, and adjust the playback signal to a console (mixer).
etc., to mix down to two channels (stereo), and the resulting signal is used to cut records or record on tape, and commercially available records, music tapes, etc. are created.

However, this process requires the following operations.

That is, with a tape created using method 1) above, there are many cases where the sound in a certain channel is strange, or where it would be better to change the sound.

In this case, while playing back the tape, only the parts to be changed are re-recorded to create the desired sound.

(The start of this recording is usually called the pan-nine, and the end is called the punch-out.

) There is not only one part in the same channel that requires such a change, but there are also several parts in other channels.In other words, the timing at which punch-in and punch-out is required on the tape differs depending on the channel. Looking at the whole, it becomes necessary to perform pan-nine and punch-out individually at many timings. When the tape created using the method 2) above is finally played back, there are parts that require re-recording as described above. occurs, requiring punch-in/punch-out.

An object of the present invention is to provide a magnetic recording/reproducing apparatus that can easily control pan-nine punch-out of N channels at a desired timing.

First, a magnetic recording/reproducing device (tape recorder) with multiple N channels will be explained using FIGS. 1 to 3.
The figure shows the tape running system of an N-channel tape recorder. The tape 3 is given an appropriate back tension by the torque of the supply reel motor 2 to which a voltage is applied to rotate the supply reel 1 in the direction of arrow A. B.
The pinch roller 5 is pressed at one end in the direction of arrow C by the pinch roller solenoid 4 with the point as a fulcrum, and the capstan 7 rotates at a constant speed in the direction of the arrow by a capstan motor 6. direction at a constant speed, and is wound onto the take-up reel 8 by the torque of the take-up reel motor 9 to which a voltage is applied to rotate the take-up reel 8 in the direction of arrow F.

As is well known, since the tape 3 runs in the direction of arrow E, 1
0 is an erasing head, 11 is a recording head, and 12 is a reproducing head.

FIG. 2 shows each of the erasing, recording, and reproducing heads 10.1.
1.12 as viewed from the tape contact surface (front surface of the head).

As shown in the figure, the tracks are 1st channel (1ch), 2nd channel (2ch), 3rd channel (3ch), and 4th channel (4ch) from the top, and the bottom end forms an N channel (Nch) track.

On the other hand, FIG. 3 shows the magnetization pattern of the magnetic tape recorded by these heads, viewed from the magnetic surface of the tape.
Versus tape running direction arrow E.

The recording tracks are 1 channel (lch) and 2 from the top.
Channel (2ch), 3rd channel (3ch), 4th channel (4ch), and the bottom end is N channel (Nc
h) has a magnetization track.

Next, using FIGS. 4 and 5, we will explain the conventional method of this type.

A recording/playback circuit and a control circuit for the recording/playback circuit used in a tape recorder will be explained.

A bias signal 13 for erasure and bias is amplified by an erase amplifier 14 and supplied to the erase head 10, and amplified by a bias amplifier 15 and supplied to the recording disk 11, respectively.

The recording signal 16 is supplied to the recording head 11 by the recording amplifier 17, and the relay contacts r11-1 to r11-3 turn the recording on/off, and the solid line indicates the recording OFF state and the dotted line indicates the recording ON state.

Signal 5 reproduced by the reproduction head 12 is equalized and amplified by the reproduction equalizer amplifier 18, and then sent to the output terminal 19.
Output to.

Reference numeral 20 denotes a sync reproduction equalizer amplifier for sync reproduction (described later), which equalizes and amplifies the signal reproduced by the recording head 11 and outputs it to the output terminal 19.

The relay contact r12 is a switching contact for sync playback/normal playback, and the solid line indicates normal playback, and the dotted line indicates sync playback.

Since the recording head 11 is performing reproduction, naturally the recording on/off relay contact r11-3 is in a solid line state.

Relay contacts r11-1 to r11-3 are contacts of the same relay, so relay contacts r11-1 and rll-2 are also rl 1
-3, it becomes a solid line state.

The control circuit 21 for the recording and reproducing circuit has the above-mentioned relay contact r11.
-1 to r11-3. Controls rl2.

When recording, rll-1 to r11-3 are set to dotted lines, rl1
2 as a solid line, and during sync playback, rll 1-1~
Even if the configuration is configured to control rll 1-3 to the solid line state and rl2 to the dotted line state, the manual switch 81.82
is a switch necessary to perform these controls, and the control is performed by connecting the input to ground.

Switch S1 is a recording on/off switch and is turned on in the infusion state.

The switch S2 is a sync playback/normal playback switch, and the solid line state indicates normal playback.

Also, since the common terminal of switch S1 is connected to the contact of switch S2, when switch S2 is switched to the sync playback side (dotted line state), the input signal remains at the ground voltage even if switch S1 is switched to the dotted line state. Not.

In other words, it is possible to prevent the recording on and synchronized playback states from occurring at the same time.

The recording/reproducing circuit described above is a circuit for one channel, so N
In the case of a channel tape recorder, N circuits are required.

In addition, the control circuit 21 for the recording/reproducing circuit shown in FIG. 4 has N channels as one block, but internally N circuits for one channel are built-in, and this switch is also used as an input signal, as shown in the figure. 2XN pieces are required.

Instead of these switches S1, S2, etc., they may be constructed as shown in FIG.

In FIG. 5, switch S9 is a recording/sync reproduction switch, and switch S10 is an overall recording on/off switch.

Reference numeral 22 denotes a control circuit for the recording/reproducing circuit which controls the relay contacts based on these switch inputs.

As mentioned above, sync playback means playback using a recording head, which will be explained below.

When performing pan-nine or punch-out while listening to the sound of another channel or the sound of the same channel, if you record to the other channel along with the sound played by the playback head 12 in FIG. 4, the recording head 11 and the playback head 12, so if the tape speed is KcrrL/sec, there will be a recording time difference of L/second.

In order to avoid this time delay, pan-nine etc. are performed while listening to the sound reproduced by the recording head 11.

When performing punch-out, pan-nine, etc. in the conventional example, the timing of punch-in, etc. is often different between channels, so switches 81 to S8 (actually 2
XN switches) must be operated many times, and if the timing interval that requires changes such as span-in is very short, it may not be possible. There was a strong need for a device that could perform out operations.

Next, an embodiment of the present invention that solves the conventional problems will be described with reference to FIGS. 6 to 10.

, the tape running system, the head, and the magnetization pattern of the tape are the same as those shown in FIGS. 1 to 3, so their explanation will be omitted.

First, the recording and reproducing circuit will be explained using FIG.

The bias signal 13 for erasing and bias is the erasing amplifier 1
4 and supplied to the erasing head 10, and amplified by the bias amplifier 15 and supplied to the recording head 11.

The recording signal 16 is amplified by a recording amplifier 17 and supplied to the recording head 11.

Relay contacts rA'3-1 and r13-2 are on/off contacts for this recording, and the solid line indicates on and the dotted line indicates off.

The signal reproduced by the reproduction head 12 is equalized and amplified by a reproduction equalizer amplifier 18 and output to an output terminal 19.

Reference numeral 20 denotes a sync reproduction equalizer amplifier for sync reproduction, which equalizes and amplifies the signal reproduced by the recording head 11 and outputs it to the output terminal 19.

relay. Contacts r14-1 and r14-2 turn on/off sync reproduction, and the dotted line state indicates sync reproduction.

Since it is an N-channel magnetic recording/reproducing device, it is natural that N
A channel recording/reproducing circuit, N recording signals, and N output terminals are required.

Next, the control circuit for the recording/reproducing circuit will be explained with reference to FIG.

SR1 to SRM constitute a shift register with N pits and XM columns, recording entry switches SW1 to SWN are input signals to the shift register, and switch S11 is a clock signal switch for shifting the shift register.

The numbers of the recording entry switches SW1 to SWN correspond to each channel, and the solid lines (logic level is H)
Recording is turned on at the dotted line (logic level is L), and a sync reproduction signal is input to the shift register SR1.

Therefore, since there are M shift registers, recording on/off information for channels 1 to N can be reserved in M stages.

The output signal of the shift register SRM• at the final stage controls the current recording on/sync reproduction of each channel.

This control is possible only when the recording switch 812 that controls on/off of the entire recording is open (logic level is H) as shown by the solid line.

When the recording switch S12 is short-circuited (logic level is L) as shown by the dotted line, neither recording nor sync reproduction can be performed.

For example, when the output Q1 of the shift register SRM is H1 and the recording switch S12 is H, the output of the AND circuit 23 becomes H, and the switching transistor Tr connected by the resistor R1
1 turns on and relay RL3 operates.

Also, since the output of the inverter 24 becomes L, the AND circuit 2
5 becomes L, the switching transistor Tr2 connected through the resistor R2 is turned off, and the relay RL4 does not operate.

Relay RL3. RL4 are relay contacts r13-1, r#3-2, and r1 of the recording/reproducing circuit shown in FIG. 6, respectively.
4-1 and r14-2, so r13-
1 r13-2 and ri! 4-1, r14-2
Since each of these will look like the actual one, recording will be on and normal playback will occur.

Furthermore, when the output Q1 of the shift register SRM is high and the recording switch S12 is high, the output of the AND circuit 23 is
Since the ND circuit 25 becomes H, relay RL3 is turned off and relay RL4 is turned on.

That is, in Fig. 6, relay contact r13-1゜r13-
2, r14-1, and r14-2 all become like dotted lines, and the recording/reproducing circuit is in a state of recording off and sync reproduction.

When the recording switch S12 is L, the shift register SR
Regardless of the output of M, the outputs of both AND circuits 23 and 25 are both L.

Therefore, in this case, RL3 and RL4 are turned off, and r
13-1, r13-2 are dotted line states, r114-1, r
Since the line 114-2 is in a solid line state, recording is turned off and sync playback is turned off, resulting in a normal playback state.

As described above, each channel is
It is controlled in three states: recording on, sync playback off, normal playback, ■recording off, sync playback off, and ■recording off, sync playback off, normal playback.

Next, in FIG. 8, which shows an example of pan-nine and punch-out and explains how to use the shift register, the upper half shows the time table of each channel, and the lower half shows the output of the shift register SRM at each time. Indicates the information required.

For example, in 1 channel (1ch), as time t passes, it changes from sync playback 5YNC to recording on REC at tl, and then to sync playback 5YNC at t3, so the output Q of the shift register SRM changes from L to H at tl, and at t3
It is sufficient if it becomes L.

Other channels may also be controlled in this manner.

Therefore, in order to control each channel using the timetable shown in FIG. 8, it is sufficient to perform the control as shown in FIG. 9.

, t in FIG.

Previously, it was necessary to start the tape run by PLAY, but in this explanation, we will explain the control method from to.

That is, t in FIG. From t1, from the 1st bit, L
, L, H...L (1st bit is QIIN bit is Q
N) Therefore, turn on SWl, turn on SW2, turn on SW3, turn off SW4... turn on SWN, and turn on the clock signal switch S11.

(Assuming that the clock signal of the shift register is L when data is read and latched), the outputs Q1 to QN of the shift register SR1 are L.

It becomes L, H,...L.

Next, at time t1, from the 1st bit, H, L, L, H...
Since L signal is required, SWl, SW2...S
When WN is turned off, on, on, off, etc. and the clock signal switch S11 is turned on, the output signal of the shift register SRI (sequentially from Q to QN, L,
L, H...L) are shifted to shift register SR2 and shift register.

The output of register SR1 is H and L from Q to QN.

L, H...L.

When such an operation is performed M times, a time t is stored in the shift register SRM as shown in FIG.

The necessary data (sequentially from Q to QN, L, L.

R2...L), and shift register SR (M-1).
is the data required at time t (H2L sequentially from Q to QN,
L, H...L), and the shift register SR (M-2) is filled with the necessary data at time t2 (H, L, H sequentially from Q to QN).
, H...L), and the shift register SR (M-3) stores the necessary data at time t3 (sequentially from Q to QN, L, H,
H,...L)... are registered.

Since the information is being input in this way, time t.

Then, the output of the shift register SRM is sequentially from Ql to QN, L, L, H...L. Therefore, as shown in Figure 8, channels 1 to 3 (1ch) to (3ch) are sync reproduction. , 4 channels (4ch) are set to record on, and N channel (Nch) is set to sync playback.

At time t, the clock signal switch S11 is operated.

By this operation, the information (
From Ql to QN, H, L, L, H...L) are shifted to the shift register SRM, so one channel (
1ch) is recording on, 2nd and 3rd channels (2ch) (3
channel) is sync playback, 4 channels (4ch) is recording on, and N channel (Nch) is sync playback.

Furthermore, when the flock signal switch S11 is operated at time t2, time t is reached.

The information registered in the shift register SR (M-2) (from Ql to QN sequentially H, L, H, H...L)
) is output from the shift register SRM, so 1st channel (1ch) is recording on, 2nd channel (2ch)
Hashi/replay, 3°4 channels (3ch) (4ch)
is recording on, and N channel (Nch) is in sync playback.

In this way, each channel can be controlled to a desired state by sequentially inputting necessary information to the shift register as time passes and operating the clock signal switch S11 as time passes.

Although shift registers are used as storage elements in FIGS. 7 and 9, switches can also be used as shown in FIG. 10.

As shown in the figure, signals obtained by inverting the outputs of N-bit AND gates 26 to 29 by inverters 30 to 33 may be connected in correspondence to the outputs of the shift register SRM in FIG. 7.

Also, since inverters 30 to 33 are included, it is sufficient to use switches to create a signal whose logic level is inverted as shown in the time table of FIG.

That is, time t. The necessary signals (R2H, H, . . . H from the 1st bit by inverting the level in Fig. 8) are created using switches S20-1 to 820-N, so 520
1 to S 20-N are turned off, off, off, etc. in sequence.

Similarly, the signals required at time t+ are L,
H, H...H, so switches 821-1 to S21-
Turn N on, off, off, etc. in sequence.

Similarly, the information at time t2 starts from the 1st bit, H, L...
- Since it is H, the switches 822-1 to S22-N are turned on, off, and then turned off in sequence.

In a similar manner, information after time t3 is transmitted to the switch 523-1.
~S 25-4.

Next, time t increases as time passes. Selector switch 826
to the I terminal, to the ■ terminal at time t1, to the ■ terminal at time t2,
The same method as that for the ■ terminal at time t1 may be used thereafter.

Therefore, time t.

Now, the output beams of inverters 30 to 33, L, L,...
However, at time t, H and L.

L...L2 At time t2, H, L, H...L, time t
3, the signals become L, H, . . . , and the same control as the method explained in FIGS. 7 and 9 can be performed.

As described above, in the present invention, since the magnetic recording/reproducing device is equipped with the memory elements of N bits/XM columns, it is possible to control the recording, reproduction, etc. of the N-channel recording/reproducing circuit in M stages.

Therefore, in the past, many channel switches (recording switches, sync playback devices, etc.) had to be operated in a short time, and such switching was impossible due to the short time. Since the switching information can be entered in advance, switching can be easily performed, and more usage methods can be provided for use in recording studios and the like.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing the tape running system of a magnetic recording/reproducing device; Fig. 2 is a front view of an N-channel recording, reproducing, and erasing head; Fig. 3 is a diagram showing an N-channel magnetic track pattern; The figure shows a conventional recording/reproducing circuit and control circuit diagram.
Fig. 5 is another conventional control circuit diagram, Fig. 6 is a magnetic recording/reproducing circuit diagram of the present invention, Fig. 7 is a control circuit diagram of the first embodiment of the present invention, and Fig. 8 is a control circuit diagram of each channel. An illustrative diagram of a timetable, FIG.
FIG. 10 is an explanatory diagram of a control example based on the time table shown in FIG. 8, and FIG. 10 is an explanatory diagram of a control example based on the time table of FIG. 8, which shows a second embodiment of the memory element. , 3...tape, 5
...Pinch roller, 6...Capstan motor, 7...Capstan, 8...
・Take-up reel, 10... Erasing head, 11...
... Recording head, 12 ... Playback head, 1
3... Bias signal for erasure and bias, 1
4... Erasing amplifier, 15... Bias amplifier, 16... Recording signal, 17...
Recording amplifier, 18... Playback equalizer amplifier,
19... Output terminal, 20... Sink reproduction equalizer amplifier, 21° 22... Recording and reproduction control circuit, 23, 25... AND circuit, 24
...Inverter, 26-29..., AND gate, 30-33...Inverter, RL3
, RL4------ Relay, r13-1, r13
-2, rll 4-2-...Relay contact, SR1~
SRM...Shift register, SW1 to SWN recording entry switch, S11...Clock signal switch, S12...Recording switch, R1
, R2...Resistance, Trl, Tr2...
・Switching transistor, S20-1 to S25
-N... switch, S26... changeover switch.

Claims (1)

[Claims] 1 comprising an N-channel erasing head, an N-channel recording head, an N-channel reproducing head, an N-channel magnetic recording/reproducing circuit, an N-channel recording/reproducing circuit control circuit, and an N-pitch hXM array of storage elements, A magnetic recording/reproducing device characterized in that a circuit control circuit is configured to perform control based on the contents of the storage element.