JPS5816765B2 - Tuning control circuit for synthesizer receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection control circuit for an AM/FM receiver, and more specifically, to a frequency division ratio that constitutes a part of a PLL circuit of a PLL (phase-locked loop) synthesizer receiver. The present invention relates to a tuning control circuit for a synthesizer receiver having both automatic tuning and preset tuning functions, which operates in conjunction with a variable programmable divider.

Conventional tuning systems for AM/FM receivers, such as car radios, generally include a mechanical preset device (
The complicated structure of the microtuner (μ tuner) has been a major obstacle to reducing the size and weight of AM/FM receivers.

Furthermore, in the conventional tuning method, taking the tuning button as an example, after receiving an AM signal by pressing the tuning button, if you operate the AM/FM switching lever to switch to FM, the FM signal cannot be received. This has the disadvantage that complicated operations such as having to press the same channel selection button again are required.

Furthermore, the conventional so-called 5-10 tuning system, which allows presetting of up to 10 stations using 5 selection buttons and an AM/FM switching lever, can only preset up to 5 AM stations and 5 FM stations each.

stomach.

Therefore, if there are many FM stations (for example, in the United States), 5
Being able to preset only up to the station does not fully satisfy listeners.

Therefore, the present invention solves the above-mentioned drawbacks.
A tuning control circuit for a synthesizer receiver having both automatic tuning and preset tuning functions that can be integrated into an IC and can be made to cooperate with a PLL synthesizer, especially when n tuning switches are used. It is an object of the present invention to provide a channel selection control circuit in which a total of 2n stations can be freely preset regardless of the types of AM stations and FM stations.

The invention will be explained in detail below with reference to illustrated embodiments.

The figure is a specific logic circuit diagram of the channel selection control circuit of the present invention, and is illustrated so that a total of 10 broadcast stations can be selected regardless of the types of AM stations and FM stations.

1 The preset tuning switches SW1 to SW5 are, for example, automatic return type switches, and are turned on when pressed upward or downward, respectively, and the corresponding preset tuning holding flip-flops FF1 to FF5. FF1/
~Increase the set input to FF5' by 4.

OR gates 01-G5. Gl' to G5' are, for example, OR
Gate G1 is a flip for preset synchronization holding, and 70 knobs FF2 to FF5. FF1' to FF5' and an automatic tuning holding flip-flop FF6, which will be described later. Just as it receives the output signal from FF6/, it also receives output signals from a preset tuning holding flip-flop and an automatic tuning holding flip-flop shown in parentheses, respectively.

OR Goo) Gl~G5. Gl' to G5' have their outputs connected to the reset inputs of the corresponding preset tuning holding flip-flops in order to reset all the preset tuning holding flip-flops in the non-tuning state.

Clip-flop FF1 to FF for maintaining precent synchronization
5, each output of FFI'-FF5' is connected to a random access memory RAM via an address encoder AE.
connected to.

The address encoder AE is a random tuner tuned by operating precent tuning switches SW1 to SW5.
Functions to specify the address of the access memory RAM.

In the illustrated embodiment, the random access memory RAM has n, each of which determines the tuning frequency for a total of 10 broadcast stations, regardless of the type of AM or FM station, that is, the frequency division ratio for the synthesizer receiver. It has a structure of 10 words x (n+1) bits so as to store bit data (for example, n-8) and 1-bit data for AM/FM identification.

the data selector DS outputs a data signal indicative of the tuned tuned frequency from the data output of the random access memory RAM in a normal preset tuning mode;
On the other hand, as described later, automatic tuning switch SW6
In the automatic tuning mode in which the FM presettable counter PC1 is activated, the counter output 0UT1 or AM
Counter output 0 of presettable counter PC2 for
This is a gate circuit that outputs the output signal from UT2.

The automatic tuning switch SW6 is an automatic return type switch that turns ON when pressed upward or downward. When pressed upward, the automatic tuning switch SW6 gives a set input to the FMM dynamic tuning holding flip-flop FF6; AMM dynamic tuning holding flip-flop F
Give a set input to F6'.

The OR gate G6 receives the output signals from the preset tuning holding flip-flops FF1 to FF5, FF1' to FF5 and the AMM dynamic tuning flip-flop FF6', and the output of the OR gate G6 is In order to reset the FMM dynamic tuning holding flip-flop FF5 in the tuning mode and the AM automatic tuning mode, it is connected to its reset input.

The OR gate 06' also connects preset tuning holding flip-flops FF1 to FF5. FF1/~FF5 and the output signal from the FMM dynamic tuning holding flip-flop FF13, and the output of the OR gate)
In order to put the dynamic tuning holding flip-flop FF5/ into a reset state, it is connected to its reset input.

The output of the FMM dynamic tuning holding flip-flop FF6 is the first input of the AND gate GGI, the set input of the flip-flop FF7 that makes the FM presettable counter PC1 countable in the FMM dynamic tuning mode, and the OR gate. They are respectively connected to the second human power of gate G7.

On the other hand, AMM dynamic tuning holding flip-flop FF5'
The output of the AND gate GG2 is the first input from the flip-flop F F7 that enables the AM presettable counter PC2 to count in the AM automatic tuning mode.
' set input, and OR game) are connected to the first human power of G7, respectively.

The output of flip-flop FF7 is presettable.
Clearing counter PC1 manually C1, AND gate GG1
The output of the flip-flop FF7' is connected to the second power of the presettable counter PC2, the second power of the AND gate GG2, and the first power of the OR gate G8. Each is connected to a second human power source.

The output of the AND gate GG1 is connected to the launch power L1 of the presettable counter PC1, and the output of the AND gate GG1
The output of 2 is connected to the latch input L2 of the presettable counter PC2.

Preset human power P- of presettable counter PC1
■N1 and preset manual counter P-IN2 of presettable counter PC2 are each random access memo 'J
Connected to the data output OUT of the RAM.

Flip 70-tube FF8 is in automatic tuning mode, and its set input is connected to OR gate G so that it is in the set state.
The output of the flip clock FF8 is connected to the second output of an AND gate GG3 whose first input is connected to the clock source CL, and the output of the flip clock FF8 is connected to the output of the AND gate GG3.
When flip-flop FF8 is in the set state, a clock signal for performing automatic tuning is sent to each counter input IN of presettable counter PC1 or PC2.
1 and IN2.

The counter outputs 0UTI and 0UT2 of the presettable counters PC1 and PC2 are connected to the first and second input terminals of the OR gate G9, and the output of the OR gate G9 is input to the data selector DS and the counter output 0UT1 and 0UT2 are input to the data input IN of the memory RAM so that they can be written to the random access memory RAM by the write switch SW7.

The output of OR gate G9 is output from data selector DS when OR gate G8 outputs an output due to the set state of flip-flop FF7 or FF7'.

OR gates GIO, G11, and G12 are a group of gates that act to reset flip-flop FF7 or FF7', and the inputs of OR gate G10 are connected to flip-flops FF1 to F for preset tuning retention, respectively.
It is connected to the outputs of F5 and FFI' to FF5'.

The first input of OR gate G11 is connected to the output of OR gate G10, the second input is connected to the output of AM automatic tuning holding flip-frog FF6', and the output of OR gate G11 is connected to the output of flip-frog FF6' for AM automatic tuning maintenance. Connected to the reset input of FF7.

Therefore, in the preset tuning mode and the AM automatic tuning mode, flip-flop FF7 is in the reset state.

On the other hand, the first human power of OR gate G12 is
Similarly to the first power of 1, the second power is connected to the output of the OR gate G10, and the second power is connected to the output of the FM automatic tuning holding flip-flop FF5, and the OR gate) Gl
The output of 2 is connected to the reset input of flip-frog F F 7'.

Therefore, in the preset tuning mode and the FM automatic tuning mode, flip-flop FF7' is in the reset state.

The data selector DS selects the data signal in the automatic tuning mode obtained via the OR gate G9 or the random access memo! signal in the preset tuning mode, depending on the presence or absence of the output from the OR gate G8. Select one of the data signals from JRAM and use the FM-AM separator S
Supply to P.

The data signal output by the data selector DS includes data for determining the frequency division ratio for the selected synthesizer receiver as well as data for AM/FM identification, and the FM-AM separator SP , according to the data for AM/FM identification, the data for determining the frequency division ratio is sent to the FM tuning circuit (
FM programmable divider PD1 incorporated in the FM tuning circuit (indicated by the broken line) or AM programmable divider PD2 incorporated in the AM tuning circuit (indicated by the broken line)
supply to.

The FM-AM branch supervisor SP also selects AM or F according to the channel selection.
The output signal of the data selector DS is supplied to the input of a display decoder/driver DD that energizes a display ITR that displays M, )G(z or MHz, etc.).

Finally, OR game) G13, in automatic tuning mode,
When tuned, the FM reception signal from the FM tuning circuit or the AM reception signal from the AM tuning circuit is received via the FM differentiation circuit DFC1 or the AM differentiation circuit DFC2, respectively, and a tuning signal is output.

This tuning signal is applied to the reset input of flip-flop FF8, which puts the flip-flop into a reset state.

Therefore, AND gate GG3 is deenergized.

In addition, the output signal of the differentiating circuit DFC1 is supplied to the input of the OR game G6 in order to reset the FM automatic tuning holding flip-flop FF5, while the output signal of the differentiating circuit DFC2 is clip for
In order to reset the flop FF6', it is supplied to the input of the OR gate G6'.

Although not shown in the figure, the FM and AM programmable dividers PD1 and PD2 are connected to a local oscillator (
VCO) together with a low-pass filter and a phase comparator form a PLL circuit, the oscillation frequency of which is controlled by the data signal supplied to the FM or AM programmable dividers PD1 and PD2, and can be set to any desired frequency. becomes available for reception.

Furthermore, although the data lines are shown as single lines in the figure for convenience, it is needless to point out that they may be composed of a plurality of lines depending on the data transfer method.

Next, the specific operation of the channel selection control circuit of the present invention will be explained.

First, the operation in preset tuning mode will be explained.

As mentioned above, the random access memory RAM includes flip-flops FFI to FF5 for holding preset tuning.
, FF1' to FF5', data for determining the frequency division ratio for the synthesizer receiver and data for AM/FM identification are stored in advance in designated addresses.

In this case, the preset tuning holding flip-flop F
The broadcast stations that can be selected corresponding to FI to FF5 and FF1' to FF5' are, regardless of the type of AM station or FM station, for example, 8 FM stations, 2 AM stations, or 3 FM stations, A
A total of 10 stations can be arbitrarily selected, such as 7 M stations.

Flip-flop FFI for preset tuning retention is FM
Assuming that it corresponds to station X among the broadcast stations in
1 upward to set the preset tuning holding flip-flop FF1.

The output signal of the preset tuning holding flip-flop FFI is given to OR gates G2 to G6 and Gl' to G5/, and the preset tuning holding flip flop FFI
F2-FF5 and FF1'-FF5', FM and AM
Frisoge for automatic synchronization maintenance / 70 knobs FF6. FF6' is put into a reset state.

At the same time, a flip-flop FF for maintaining preset synchronization
The output signal of address encoder AEK4 is
The l-17' address encoder AE specifies the address corresponding to the flip-flop FF1 of the random access memory RAM.

Memo' The designated address in the JRAM stores data for determining the frequency division ratio corresponding to the X station and FM identification data.

The data signal read from the memory IJRAM is processed by an OR gate.
Since there is no output signal in 4G8, it is selected by the data selector DS and is supplied as is to the FM-AM separator sp.

The FM-AM separator SP, according to the FM identification data,
Data for determining the frequency division ratio is input to the FM programmable divider PD1, and at the same time, a data signal is input to the display decoder driver DDK4.

On the other hand, a flip-flop for maintaining preset tuning F F
Assuming that 5' corresponds to station Y among the AM broadcasting stations, the specified address in the memory RAM contains data for determining the frequency division ratio corresponding to station Y, and AM identification data. is stored, and almost the same operation as in the above case is performed, but the FM-AM separator SP gives data for determining the frequency division ratio to the AM programmable divider PD2 according to the AM identification data, and at the same time , provides the data signal to the display decoder/driver DD.

In the preset tuning mode, the flip-flops FF1 to FF5 . FFI'～
The output signal from either FF5' is sent to OR gate group G.
10 , G11 , G12 to the reset inputs of flip-flops FF7 and FF7';
The operation of presettable counters PC1 and PC2 is inhibited.

Next, the operation in automatic tuning mode will be explained.

Assuming that an FM broadcasting station is to be searched, the upward ON state of the automatic tuning switch SW6 puts the -FM automatic tuning holding flip-flop FF5 into the set state, and the output signal from the flip-flop FF5 is set. teeth,
OR gates G1 to G5. G1'~G5', G6
At the same time, all the preset tuning holding flip-flops FF1 to FF5゜FF1/ to FF5' and the AM automatic tuning holding flip-flop FF6' are set to the reset state via - It is supplied to the cent input of flop FF7 and the set input of flip-flop FF8 via OR gate G7.

Furthermore, the output signal of flip-flop FF6 is supplied to the reset input of flip-flop FF7' via OR gate G12.

The output signal generated by flip-flop FF70 set state is supplied to the second input of AND gate GG1 to energize AND gate GG1 and also to the clear input C.
1, presettable counter PC for FM
1 is cleared and further supplied to the data selector DS via the OR gate G8 to enable selection of the output signal of the OR gate G9.

At the same time, the output signal generated by the set state of flip-flop FF8 causes the clock signal of clock source CL to be applied via AND gate GG3 to counter input IN1 of presettable counter PC1.

Therefore, the presettable counter PC1 for FM is
The data signal from the random access memory RAM is latched to the present manual P-IN1 and counting is started so that the search is started from the point preset in the preset tuning mode before switching to the automatic tuning mode.

Counter output 0UT of presettable counter PC1
The output signal from 1 is input to the display decoder/driver DD and the FM programmable divider PD1 via the OR gate G9, data selector DS, and FM-AM separator SP in this order.

The count result of presettable counter PC1, F
When the frequency signal is tuned in the M tuning circuit,
The FM received signal is sent to the differentiating circuit DFC1 and the OR gate G1.
3 to the reset input of flip-flop FF8.

Therefore, by deenergizing the AND gate GG30, the clock signal is no longer supplied to the counter input N1 of the presettable counter PCI, and the output signal from the counter output 0UT1 is stopped.

At the same time, the output signal of the differentiating circuit DFCI is
6, the FM automatic tuning holding flip-flop FF6 is reset, and the receiving state is finally fixed.

On the other hand, assuming that an AM broadcasting station is to be searched, the operation is similar to that described above, but first, the automatic tuning switch SW6 is turned ON in the downward direction, and the AMM dynamic tuning holding frisogage flop FF5 is turned on. ' becomes a cent state.

The output signal from the flip-flop F F 5' is O
R gates G1 to G5. All preset synchronization holding flip-flops FF1 through G1' to G5' and G6
FF5゜FF1'-FF5' and FMM dynamic tuning holding flip-flop FF5 are reset, and at the same time, the first manual input of AND game) GG2, the set input of flip 70-tube FF7', and OR gate G7 are respectively supplied to the set inputs of flip-flop FF8.

Furthermore, the output signal of clip-frog FF5' is supplied to the reset input of flip-flop FF7 via OR gate G11.

The output signal of flip-flop FF7/ is supplied to the second input of AND gate GG2.
is energized, and also supplied to the clear human power C2 to clear the presettable counter PC2 for AM, and furthermore, the OR
It is supplied via gate G8 to data selector DS to enable selection of the output signal of OR gate G9.

At the same time, the output signal of flip-flop FF9 causes the clock signal from clock source CL to be applied via AND gate GG3 to counter input IN2 of presettable counter PC2.

Therefore, the AM presettable counter PC2 is
The data signal from the random access memory IJRAM is latched into the preset manual P-IN2 and counting is started so that the search is started from the point preset in the preset tuning mode before switching to the automatic tuning mode.

Counter output 0UT of presettable counter PC2
The output signal from 2 is an OR gate G9, a data selector DS, and an FM-AM separator.

Valve SP sequentially to display decoder/driver DD and A.
Input to MM programmable divider PD2.

The count result of presettable counter PC2 is A
When the frequency signal is tuned in the M-tuned circuit,
The AM received signal is passed through the differentiating circuit DFC2 and the OR gate G1.
3 to the reset input of flip-flop FF8.

Therefore, due to the deenergization of the AND gate GG3, the clock signal is no longer supplied to the counter input IN2 of the presettable counter PC2, and the output signal from the counter output 0UT2 is stopped.

At the same time, the output signal of the differentiating circuit DFC2 is
G6', the AMM dynamic tuning holding flip-flop FF6' is reset, and the receiving state is finally fixed.

Note that the counter output 0UT1 or 0UT2 of the presettable counter PC1 or PC2 is connected to the OR gate G.
9 is connected to the data input IN of the random access memo' JRAM, and when the reception state is fixed as described above, when the write switch SW7 is turned on, the automatic tuning mode is entered. to the random access memory RAM address that was specified just before
The output signal from counter output 0UT1 or 0UT2 is written as new data.

At this time, the data signal from the random access memory RAM is sent to the FMM programmable divider PD1 or A.
It is supplied to the double shim pull divider PD2 for M,
This data signal is sent to the counter output 0 of the presettable counter PC1 by operating the write switch SW7.
Since the content has been changed to be the same as the output signal from UT1 or the counter output 0UT2 of the presettable counter PC2, the reception state is maintained as it is.

According to the present invention, by integrating the selection control circuit into an IC, it is possible to provide a receiver that is extremely small and lightweight compared to conventional A M/FM receivers, and furthermore, it is possible to provide a receiver that is extremely small and lightweight compared to conventional A M/FM receivers. Simple preset tuning and automatic tuning functions can be easily incorporated.

Furthermore, according to the present invention, regardless of the types of FM stations and AM stations, it is possible to preset any number of stations that can be selected within a certain range (10 stations in the embodiment), thereby increasing the degree of freedom in channel selection. can be significantly increased.

Furthermore, even when the power is turned off, the preset tuning holding flip-flop maintains the state before the off state, and by configuring the random access memory to be non-volatile, it can be set simultaneously when the power is turned on. It is possible to automatically tune into the broadcast station that was previously received.

[Brief explanation of the drawing]

The figure is a specific logic circuit diagram of the channel selection control circuit of the present invention. (Description of symbols), SW1 to SWS Switch for nib reset tuning, SW5: Switch for automatic tuning, SW7: Switch for writing, FF1 to FF5° FF1 to FF 5th generation preset tuning holding flip-frog, FF7, F
F7', FF8: Flip-flop, FF5:
FMM dynamic tuning holding flip-flop, FF6':A
MM dynamic tuning holding flip-flop, G1 to G13
, G1'-G6': OR gate, GGI-GG3
: AND gate, AE near address encoder, R
AM: Random access memory, DS: Take selector, CL: Clock source, PCI: FMM presettable counter, PC2: AMM presettable counter, SP: FM-AM minute discriminator DFCI, DFC2
: Differential circuit, DD: Display decoder/driver, ITR
: Display, PDI: Programmable °apida for FM,
PD2: Programmable ° divider for AM.

Claims (1)

[Scope of Claims] 1. In a channel selection control circuit for a synthesizer receiver that operates in conjunction with an AM programmable divider and an FM programmable divider that constitute a part of a PLL circuit of the synthesizer receiver, ) a plurality of preset tuning switches, each of which has two output terminals that can be selectively turned on to instruct tuning; (b) two of the preset tuning switches; A pair of first flip 70-tubes connected to two output terminals, respectively. In the preset tuning mode, when a station is selected, the set state is set and the first output signal is generated, and when the station is not selected, the first output signal is reset. the first flip-flop being in the ON state to prevent generation of the first output signal; an automatic tuning switch having two output terminals; (to) one output terminal of the automatic tuning switch; a second flip-flop which generates a second output signal and is reset by the preset tuning mode and the AM automatic tuning mode to prevent generation of the second output signal; is connected to a terminal, and in the automatic tuning mode, is set in the AM automatic tuning mode to generate a third output signal;
(f) a third flip-flop that is put into a reset state and prevented from generating the third output signal in the preset tuning mode and the FM automatic tuning mode; and (f) corresponding to the output terminal of the preset tuning switch. In order to make it possible to select a plurality of stations regardless of the types of AM stations and FM stations, a first flip-flop that determines a frequency division ratio for the synthesizer receiver corresponds to each of the first flip-flops. (g) a memory that stores data and second data for AM/FM identification and is accessed in response to the first output signal; latches the data signal consisting of the first and second data, starts counting, performs a search for FM automatic tuning, and continues counting until the FM tuning state is reached. a first counter generating a counter output signal of 1; The count is continued until the AM synchronization state is reached, and the second
a second counter that generates a counter output signal; (v) when in the preset tuning mode, selects and outputs the data signal read from the memory, and when in the automatic tuning mode, selects and outputs the data signal; or a data selector that selects and outputs the first counter output signal or the twentieth counter output signal according to a second output signal; an FM-AM separator that selectively supplies first data for determining the frequency division ratio to either the AM programmable divider or the FM programmable divider according to second data for identification; , A channel selection control circuit for the synthesizer receiver.