JPS5828963B2 - electronic tuning receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic tuning receiver, and in particular, detects a band select switch and a channel select switch that are in different standby states using a logic circuit.

In recent years, with the rapid development of electronic technology, various devices have come to be digitally controlled by switch outputs.

For example, a voltage synthesizer type receiver has been proposed in which preset channel selection can be performed by operating a switch.

This preset receiver addresses the memory by the outputs of the band select switch and channel select switch, reads out the band and channel signals preset at the address of the addressed memory, and sets them in the up/down counter for manual setting. It is configured to receive radio waves of a preset desired band and channel by converting the output into an analog signal and supplying it to a variable capacitance diode forming a tuning circuit.

In this case, the above-mentioned channel select switch is configured by a non-lock type switch, and the band select switch is configured by a rotary switch, and the channel select signal output from this channel select switch and the band select switch are Each time an output band select signal is detected, the memory output is read into an up/down counter and controlled.

However, in conventional electronically tuned receivers, the outputs of the channel select switch and band select switch are different in the standby state, meaning that the channel select switch is all off in the standby state, while the band select switch is One is selected and turned on, and it only turns off momentarily when a band is selected.

As described above, in order to detect the switch outputs in different standby states, there is a drawback that two types of circuits are required for each type of switch.

Therefore, the present invention was made in order to solve the above-mentioned problem, and is an electronic tuning receiver that uses two types of switches, a channel select switch and a band select switch, which have different standby states. It is an object of this invention to easily configure a control circuit for reading a rememory receiving station whose receiving station has been preset by a signal from the receiver without malfunction.

1 and 2 show an embodiment of an electronically tuned receiver according to the present invention, in which 1 is a pulse generator that selectively generates up/down pulses U/D and clock pulses KC by manual operation; 2 is a binary up/down counter that receives the clock pulse KC as a count input in response to the up pulse U or down pulse D of the pulse generator 1, and 3 inputs the upper few bits of the count output of the up/down counter 2. 4 is a reception band display that digitally displays the oscillation signal, and 4 corresponds to the output of the up/down counter 2 by selecting and combining the output signals of each stage obtained by dividing the oscillation signal with the output signal of the up/down counter 2. A pulse synthesizer 5 for obtaining a serial pulse train of the number of pulses is a low-pass filter, and together with the pulse synthesizer 4 constitutes a DA converter.

Reference numeral 6 denotes a band select switch that selects a band by switching and supplying the DC output of the low-pass filter 5 to a tuning circuit (not shown), and fixed contacts a''-c are in charge of bands A to C, respectively.

γa to γe are channel select switches constituted by non-lock type switches, 8 is a band select switch having fixed contacts a to c in charge of A to C bands, and this band select switch 8 and the band select switch 6 are linked.

9 latches the outputs of the channel select switches Ta to γe and the band select switch 8 as inputs, and stores the output of the up/down counter 2 at the address designated by this signal, or stores the output at the designated address. Read the contents and use up/down counter 2
A read/write memory 10 supplies inputs to the outputs of the channel select switches la to γe and the output of the band select switch 8, and a preset switch 11.
is off, the channel select switch γa
= r A control circuit that supplies a load signal to the up/down counter 2 when an output of e is generated, and also supplies a write signal W to the read/write memory 9 when it is on, and suppresses the chattering included in the switch output. A chuckling prevention circuit is built-in to prevent this.

In this case, the control circuit 10 having the chattering prevention circuit is configured as shown in FIG.

In FIG. 2, reference numeral 12 denotes an OR gate whose inputs are the outputs of the channel select switches ra-re, 13 denotes an OR gate whose inputs are the outputs of the contacts a to C of the band select switch 8 and the preset output Ps of the preset switch 11; 14 is a flip-flop whose set input is the output of the OR gate 12; 16 is an AND gate that determines the match between the output of the OR gate 12 and the output of the flip-flop 140; and 11 is the output of the OR gate 13 and the flip-flop 150. 18 is an OR gate which inputs the output of AND gate 16°1γ, 19 is a chuck ring prevention circuit,
D type lunch 20 and D type flip flop 2
1.

The launch 20 uses the output of the OR gate 18 as a data input and a reset input, and uses the clock pulse CP as a clock input.

Further, the flip-flop 21 uses the latch 200 set output Q as a data input.

22 is a NOR gate which inputs the reset output Q of the flip-flop 21 and the preset signal Ps and outputs the write signal W; 23 is the set output Q of the flip-flop 210;
, is a Nant gate which receives the preset signal P8 as input and outputs the load signal.

In the voltage synthesizer type electronic tuning receiver configured in this way, the pulse generator 1 is operated (rotated)
For example, when an up pulse U is generated, this up pulse U is supplied to an up/down counter 2, and the up/down counter 2 sequentially counts up the clock pulse KC.

The parallel count output of the up/down counter 2 is supplied to a pulse synthesizer 4, where the signals of each stage, which are frequency-divided oscillation signals corresponding to the output of the up/down counter 2, are selectively synthesized to produce a corresponding pulse. The number of serial pulse trains is converted into two.

The output signal of the pulse synthesizer 4 has high frequency components removed by a low-pass filter 5, and becomes a DC voltage signal corresponding to the output of the up/down counter 2.

This DC voltage signal is applied to a variable capacitance diode of a tuning circuit (not shown) selected by the band select switch 6, and the corresponding frequency is tuned.

Further, the count output of the up/down counter 2 is supplied to a reception band indicator 3 which is constituted by, for example, 32 light emitting diodes arranged in a straight line. By inputting the upper few bits of the count output of the down counter 2 and lighting only one corresponding light emitting diode, the position of the receiving station in the receiving band is digitally displayed.

The above explanation is an explanation of the operation during manual operation.

Next, preset channel selection will be explained.

With the desired station selected by the method described above, first turn on the preset switch 11, then turn on any of the channel select switches la to re corresponding to the channel you want to preset, and the control circuit 1
A write signal W is supplied from 0 to the read/write memory 9, and the band select switch 8 of the read/write memory 9 and the channel select switches 7a to 7a which are turned on are
The count output of the up/down counter 2, that is, the digital signal that is the basis of the tuning frequency being received, can be stored at the address specified by re.

In this way, desired frequencies are preset for other channels as well.

Next, when performing preset channel selection, select the address where the digital signal corresponding to the desired station is stored by selecting the band select switch 8 and the channel select switch ra=1.
Select by e.

When such an operation is performed, since the preset switch 11 is off, the control circuit 10 supplies a load signal to the up/down counter 2.

As a result, the readout signal of the read/write memory 9, which read out the outputs of the band select switch 8 and the channel select switch γa-re as addresses, is up/down.
The down counter 2 reads the signal in parallel, and its output is supplied to the tR pulse synthesizer 4, where the same tuning operation as in manual operation is performed.

From now on, to change the preset selection within the same band, it is only necessary to selectively turn on the l channel select switches ra to re, and if only the bands are different but the channels are the same, only the band select switch 8 needs to be switched. The control circuit 10 detects the off output at the time of this switching and controls the up/down counter 2.

Next, the operation of the control circuit 10 will be explained using FIG. 2.

First, in the standby state, the channel select switches ra-re are all off, and the band select switch 8 selects one of the fixed contacts a"'-c.

Therefore, in the standby state, the output of the OR gate 12 is '0' and the output of the OR gate 13 is '1'.

In this case, the flip-flop 14 is connected to the OR gate 12.
However, since the output of the OR gate 12 is "O", the output of the AND gate 16 is set to "0".
It is.

In addition, in the standby state, flip-flop 1
5 is not set by the output of the OR gate 130 ``1'', and therefore the AND gate 1t is O''.

Therefore, in the standby state, even if switch outputs of different states are input, the outputs of the gates N6 and 1F are both "O", and accordingly, the latch 20 and flip-flop 210 are set via the overgate 18. Output Q
Both are turned on.

Next, when any of the channel select switches Ia to re is selected, the output of the OR gate 12 becomes "091".
It changes from 1″ to 1″.

In this case, if there is no chuck ring in the output of the channel select switch ra-re, when the output of the OR gate 12 changes from nOt+ to "1", the "i" output of the OR gate 12 and the flip-flop 140 Coincidence with the set output Q is sought, and the output of the AND gate 16 becomes 1'', and accordingly, the latch 20 becomes the latch mode via the overgate 18 at the falling edge of the clock pulse CP, and the latch 20 is set. Output Q can be kept at 1''.

When the launch 200 set output Q becomes "1", the flip-flop 21 is set at the next rising edge of the clock pulse CP and its set output Q becomes "1", and the reset output 0 resets the flip-flops 14 and 15. Along with this, the latch 20 is also reset.

Therefore, the set output Q of the latch 20 becomes 1'101t, and at the next rising edge of the clock pulse CP, the flip-flop 21 is reset and returns to the standby state.

Therefore, the output of the flip-flop 21 is only output for one cycle of the clock pulse CP.

Next, when the band select switch 8 is switched, all fixed contacts a''c are momentarily turned off at the time of switching.

As a result, when the band select switch 8 is switched, the output of the OR gate 13 momentarily becomes "0'".

When the output of the OR gate 13 becomes "0", the flip-flop 15 is set and the output of the OR gate 13 becomes "1".
When the signal is restored, the output of the Antoge'-41i/ becomes 1'', and it is detected that the band has been switched.

Next, considering the case where the output of the OR gate 12, that is, the output of the channel select switch ra-re, includes a chuck ring, if the output of the OR gate 12 has a chuck ring, the output of the AND gate 16 This chuck ring will also be output.

This chucking is also output to the latch 200 set output Q via the overgate 18 during the period when the clock pulse CP is "1".

However, when the clock pulse CP is N 017,
If the input becomes O'' even once, the reset state is activated and the latch 20 enters the reset state, so that the flip-flop 21 does not change even at the next rising edge of the clock pulse CP.

Therefore, in order to send out a set output from the chuckling prevention circuit 19, it is necessary to change the output of the OR gate 12 to "1" and then at least the "0" of the next clock pulse CP.
``0'' must hold n 1 n.

Therefore, as long as the width of each chuckling pulse is within 1/2 period of the clock pulse CP, chuckling can be reliably prevented no matter how long it continues.

In this case, since each switch output and the clock pulse CP are not visible, the time until the output pulse is sent out varies depending on the state of the clock pulse CP at the time the input changes, and the chucking at the rising edge of the input pulse is 1/2 to 3/2 of clock pulse CP after finishing
After a period an output pulse is generated.

In this way, when the set output Q is output from the flip-flop 21 and the preset switch 11 is off and the reset signal R8 and preset signal P8 are 091, the O'' signal that does not include the chuck ring is output from the Nant gate 23. A load signal is sent.

Further, when the preset switch 11 is turned on and the preset signal Ps is "1", only the output of the AND gate 22 becomes 1'' and the write signal W is sent out.

Further, even if chattering is included in the output of the OR gate 13, that is, the output of the band select switches a, b, and c, chattering can be similarly prevented.

In this way, the control circuit 10 has a first control circuit that is set by the output of the channel select switch ra=re and reset upon sending out the load signal (2) or the write signal (W).
flip-flop 14 and the first flip-flop 1
40 input/output a first gate circuit 16 whose numbers match;
a second flip-flop 15 that is set by the output of the band select switch 8 and reset upon sending out the load signal (2) or the write signal W; and a second gate circuit 1γ that matches the input and output signals of the second flip-flop 150; It has an OVER function circuit 18 which takes a sum signal of the outputs of the first and second gate circuits 16.1r, and compares the output of the OVER function circuit 18 with the output of the preset switch 11. It is configured to selectively output the write signal W.

As explained above, in the electronically tuned receiver according to the present invention, there are two types of switches (
Changes in the output (channel select switch and band select switch) can be easily and reliably detected with a simple control circuit, and the same control circuit can be used even when two types of switches are in the standby state. It has excellent effects such as increased versatility of IC-based control circuits.

[Brief explanation of the drawing]

1 and 2 are principal circuit diagrams showing an embodiment of the electronic tuning receiver according to the present invention, and FIG. 3 is a timing chart of the second receiver section. 1...Pulse generator, 2...Up...
Down counter, 4...Pulse synthesizer,
5...Low pass filter, 6.8...
Band select switch, ta-re...Channel select switch, 9...Read/write memory, 10...Control circuit, 11...
・Preset switch, 19... Chuckling prevention circuit, 20... D type latch, 21.
...D type flip-flop.

Claims (1)

[Claims] 1. An up/down counter whose up and down counts are operated manually, a DA converter that converts the count output of the up/down counter into an analog signal and supplies it to the variable capacitance diode of the tuning section, and a standby state. A read/write memory that is addressed by the band select switch and channel select switch and supplies its readout signal to the up/down counter, and an output of the band select switch and an output of the channel select switch. As an input, the switching operation of the band select switch and the selection operation of the channel select switch are detected, and a load signal for reading the read signal of the read/write memory into the up/down counter is supplied to the up/down counter. and a control section configured to supply a write signal for reading the output signal of the up/down counter to the read/write memory by operating the preset switch, and the control section is configured to supply the read/write memory with a write signal for reading the output signal of the up/down counter by operating the preset switch. a first flip-flop which is reset when the load signal or the write signal is sent; a first gate circuit which matches the input/output signals of the first flip-flop; and a first gate circuit which is set by the output of the band select switch a second flip-flop that is reset upon transmission of the load signal or the write signal;
It has a second gate circuit that matches the input and output signals of the flip-flop, and an OW function circuit that takes a sum signal of the outputs of the first and second gate circuits. An electronic tuning receiver configured to selectively output the load signal and the write signal in comparison with the output.