JPS5816786B2 - TV signal frame synchronization detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television signal frame synchronization detection method, and more particularly to a method for detecting frame synchronization required when digitally processing and encoding a television signal.

As shown in FIG. 1, a circuit for digitally processing a television signal converts a television signal 1 into a digital signal using an A/D converter 2 and sends the digital signal to a processing section 3.

On the other hand, the television signal 1 is separated into synchronization signals by a synchronization separation circuit 4 and sent to a frame synchronization detection circuit 5, and on the other hand, it is sent to a phase lock oscillator 6, and the generated clock signal is supplied to the frame synchronization detection circuit 5. The digital signal is also supplied to a timing circuit 7, and the digital signal is processed in the processing section 3 according to the timing signal generated by the timing circuit 70, and then transmitted through, for example, a PCM line 8.

On the receiving side, the processing unit 9 performs reverse processing, and the D/A converter 1
0, it is converted to analog and output.

In circuits that digitally process such television signals, it is often necessary to detect frame synchronization.

With analog synchronization separation, horizontal and vertical (field) synchronization can be detected, but frame synchronization cannot be determined.

An object of the present invention is to provide a method for detecting a frame synchronization signal of a television signal when the television signal is converted into a digital code and processed.

According to the present invention, in a circuit that converts a television signal into a digital code and processes it digitally, a phase lock oscillator that locks to the phase of a synchronization signal of the television signal and an output of the phase lock oscillator are input to generate the television signal. A counter that counts from the rising edge of the synchronization signal and a differentiation circuit that differentiates the synchronization signal and inputs the differential output to the counter are provided, and a predetermined count value of the counter is used to determine a specific line of the television signal. generates a position pulse for detecting the position before and after the falling edge of the horizontal sync pulse and equalization pulse of the horizontal sync signal, and detects the position pulse generated before the falling position, the sync signal, and the falling edge of the horizontal sync signal; A logical operation is performed between the position pulse generated after the position and the inverted signal of the synchronization signal, and the output of the logical operation is input to an AND circuit, and when the output of the AND circuit becomes 1, the television signal is A television signal frame synchronization detection method is proposed that is characterized by detecting frame synchronization.

Embodiments of the frame synchronization detection method for television signals according to the present invention will be described in detail below with reference to the drawings.

The gist of the present invention is to focus on the fact that the horizontal synchronization signal of a specific line of the synchronization waveform of the vertical synchronization part (including blanking) of a color television NTSC signal has a horizontal synchronization pulse and an equalization pulse in the first half. , frame synchronization is detected by detecting the positions of these pulses.

Figure 2 shows the horizontal synchronizing signal on the 263rd line of the NTSC signal.
There is only one in the frame.

The rising and falling positions of pulse 11 in the figure are 0 and 0.075H, respectively, and the rising and falling positions of pulse 12 are 0.5H and 0, respectively.
．． It is 54H.

Therefore, a counter that is set at the rising edge of the synchronous signal 11 and reset at the rising edge of the synchronous waveform when the count number is 0.54H or more is 0.075H-α, 0.0
75H+α, 0.54H-α, 0.54H+α (however, α
is a small value selected in consideration of waveform distortion, etc.

) to 4iF/) pulses 13a, 13b, 13c and.

The present invention attempts to generate 13d and detect a frame synchronization signal based on this.

FIG. 3 shows a circuit according to the present invention.

As shown in the figure, the synchronization signal is generated by the phase lock oscillator 21.
The circuit 21 applies a clock pulse to the counter circuit 22.

On the other hand, the synchronization signal is applied to the differentiating circuit 23 and the gate circuits 26a and 26c, and is also applied via the gate 25 to the gate circuits 26b and 26d.

The counter starts counting when the synchronizing signal rises and is reset when the count corresponds to 0.54H or more, and its output is input to the pattern match address decoder 24.

The pattern match address decoder 24 is set at the rising edge of the synchronization signal as shown in Figure 2, and the count number is 0.54H.
In the above cases, it is set at the next rising edge of the synchronization signal, and becomes 0.
．． 075H-α, 0.075H+α, 0.54H-α,
Four pulses corresponding to 0.54H+α (13 in Figure 2)
a, 13b, 13c, 13d).

That is, in the address decoder 24, as shown in FIG.
Four pulses are generated at the positions of +α, 0.54H-α, and 0.54H+α, and these pulses, together with the synchronization signal and the inverted synchronization signal, are applied to the gates 26a and 26, respectively.
latch 27a via b, 26c, 26d, respectively.
, 27b, 27c.

27d.

The latches 27a to 27d have one input terminal connected to a gate (26a).

The outputs of 26b, 26c, and 26a are input, the reset signal of the counter 22 is input to the other input terminal, and the inverted synchronization signal of 5YNC1 is input to 5YN.
When displayed as C, latch A (27a) is 5YNC・(
Set at 0,075H-α), latch B (27b) is 5YNC・(0,075H+α)
Latch C (27c) is set at 5YNC-(0,54-α), latch D (27d) is set at 5YNC·(0,54+α), and waveforms as shown in FIG. 4C are obtained.

The outputs A, B, C, and D of these latch circuits are applied to the AND circuit 28, respectively, and the output X of the AND circuit 28 is applied to the AND circuit 28.
When X=A-B-C-D=1, the 263rd line is detected.

At this time, since the horizontal synchronization position is also fixed, both synchronizations are detected.

However, latches A, B, C, and D are reset at the same time as the counter.

The counting clock is also supplied by a phase lock generator 21 locked to a synchronization signal.

If one pulse 2 is applied to the AND circuit 28 before the latch is reset, a synchronizing pulse as shown in FIG. 4e can be obtained at any point in X=A-B-C-D-Z.

This also allows the horizontal synchronization phase to be freely selected.

As explained in detail above, according to the present invention, when a frame synchronization signal is required to convert and process a television signal into a digital signal, the television signal is converted from the rising edge of the synchronization waveform of the television signal by a predetermined count value of the counter. By generating a position pulse to detect the position before and after the falling edge of the horizontal synchronizing pulse and equalization pulse of the horizontal synchronizing signal of the specific line of the 1st line, performing a logical operation with the synchronizing signal and latching its output. The frame synchronization and horizontal synchronization of the signal are detected simultaneously, and although the horizontal synchronization signal of the 263rd line of the NTSC signal is used in the embodiment of the present invention, it is of course not limited to this.

[Brief explanation of the drawing]

Fig. 1 shows a circuit that converts a television signal into a digital signal and processes it, Fig. 2 shows a horizontal synchronization signal at the beginning of the 263rd line of an NTSC signal, and Fig. 3 shows an embodiment of the frame synchronization detection method according to the present invention. The circuit diagram shown in FIG. 4 is a waveform diagram of each part for explaining the operation of the circuit shown in FIG. 3. In the figure, 5 is a frame synchronization detection circuit, 22 is a counter, 24 is a pattern match address decoder, 27a,
27b, 27c, and 27d are latch circuits, and 28 is an AND circuit.

Claims (1)

[Claims] 1. In a circuit that converts a television signal into a digital code and processes it digitally, a phase lock oscillator that locks to the phase of a synchronization signal of the television signal and an output of the phase lock oscillator are input to convert the synchronization signal of the television signal. A counter that counts from the rising edge of , and a differentiation circuit that differentiates the synchronization signal and inputs the differentiated output to the counter are provided, and the horizontal synchronization signal of a specific line of the television signal is determined by a predetermined count value of the counter. generates a position pulse for detecting the position before and after the falling of the horizontal synchronizing pulse and the equalization pulse, and the position pulse that occurs before the falling position and the synchronizing signal and the position pulse that occurs after the falling position. performs a logical operation on the position pulse and the inverted signal of the synchronization signal, inputs the output of the logical operation to an AND circuit, and detects frame synchronization of the television signal when the output of the AND circuit becomes 1. A television signal frame synchronization detection method characterized by: