JPS5816800B2 - Channel shift switch redundancy configuration method for time division switching equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a redundant configuration system for channel shift switches in a time division exchange.

To increase reliability of operation, it is common practice to multiplex devices and switch to a backup device in the event of a failure of the active device.

Such a redundant configuration has been adopted in the past in time division switching equipment as well.

FIG. 1 is a block diagram of an example of a channel shift switch redundant configuration system of a conventional time division switch, in which 1 is a transmission line for transmitting time division multiplexed channels, and 2 and 3 are configured as channel shift switches. A communication path system,
4 and 5 are gates, 6.1 is data bus memory, 8,
9 is an address control memory, io and ii are address counters, and 12 is a control circuit.

In this case, the communication path system is duplicated, and if one communication path system has a failure, switching is made to the other communication path system, which is on standby as a backup.

Here, a case where a channel shift switch is used as the communication path system is shown.

In FIG. 1, the communication line systems 2 and 3 connected to the transmission line 1 for transmitting time-division multiplexed channels are configured as channel shift switches having exactly the same structure, and the gate 4
, 5, data bus memory 6.7, address control memories 8 and 9, and address counters 10 and 11, respectively.

The control circuit 12 writes the same data to the same address in the address control memories 8 and 9, and controls the gates 4.5 to connect only one of the data bus memories 6.1 to the transmission line 1.

These work as follows.

The control circuit 12 selects a pair of channels to be connected in a known manner and one address (one of 1 to n) equal to 6.70 in the data bus memory to be used for the connection, and selects the corresponding address in the address control memories 8 and 9. One equal address of the data bus memory 6.7 described above is written to each address (two of 1 to 1) corresponding to the channel.

The address control memories 8 and 9 contain the contents stored at the address corresponding to the channel number indicated by the address counter 10. read data bus memory 6.1.

The data bus memory 6.1 reads the contents stored at the addresses transmitted from the address control memories 8 and 9, sends it onto the transmission line 1 via the gates 4 and 5, and then transmits the information on the transmission line 1. Write to the same address via gates 4 and 5.

By periodically repeating such operations, connections between channels using the same address in the data bus memories 6 and 7 are established.

The communication path systems 2 and 3 operate in exactly the same way, but the control circuit 1
2, only one of the gates 4.5 is in a connected state, only one of the communication line systems 2 and 3 is connected to the transmission line 1, and the other is in a standby state as a reserve.

This configuration has disadvantages in that it requires duplicate communication path systems of channel shift switches having the same structure, and also duplicates memories, making it impossible to reduce their capacity.

It is an object of the present invention to eliminate the above-mentioned drawbacks of the conventional system and to reduce the overall memory capacity by duplicating only a portion of the channel shift switch, which is a communication path system.

According to the present invention, the present invention has a data bus memory for connecting time-division multiplexed channels, and has a correspondence between the channels to be connected and the addresses of the data bus memory used for the connection. In a channel shift switch of a time division switch having an address control memory, the data bus memory is divided into a plurality of parts that do not mutually share the same address, and the address control memory is capable of storing any address of the data bus memory. Provide the same number of partitions as the above data bus memory,
Each divided portion of the data bus memory is mapped 1:1 with the divided portions of the data bus memory, and each divided portion of the data bus memory is operated only when an address included in the divided portion is specified by the address control memory associated with it. This can be achieved by configuring to perform write or read operations.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which numerals 1 to 11 indicate the same components as in FIG. 1, 13 is a control circuit, and 14 and 15 are circuits for specific functions.

In this embodiment as well, there are two communication path systems configured as channel shift switches, as shown by 2 and 3.
Provide multiple layers.

In addition, in the communication path systems 2 and 3, gates 4 and 5, address control memories 8 and 9, and address counters 10 and 1
Although data bus memories 6 and 7 are provided with exactly the same memory in duplicate, the number of data bus memories 6 and 7 may be n addresses in total.

That is, the data bus memory is divided into two parts 6 and 7 which do not mutually share the same address.

Data bus memory 6 (addresses 1 to m) is accessed only from address control memory 8, and data bus memory 1 (addresses m+1 to n) is accessed only from address control memory 9.

Further, identification circuits 14 and 15 identify which of the data bus memories 6 and 7 is being accessed, and only one of the gates 4 and 5 coupled to the accessed data bus memory 6 and 1 is connected.

If one of the communication path systems 2 and 3 becomes faulty, only the other normal one can be used, but in that case, the data bus memory 6.1 is used only by the normal one, so its address range is Normal communication path system data bus memory 6 or 1
limited to only one.

These work as follows. The control circuit 13 selects a pair of channels to be connected using a known method and one address (1 to n) of the data bus memory 6 or 7 used for the connection.
one of the above-mentioned data bus memories 6 or 7 is written to the addresses (two of 1 to 1) corresponding to the channel in the address control memories 8 and 9, respectively.

The address control memories 8 and 9 contain the contents stored at the address corresponding to the channel number indicated by the address counters 10 and 11 in synchronization with the channel on the transmission line 1 in a known manner (corresponding to the address of the data bus memory 6 or 7). )
is transmitted to the data bus memory 6.1.

When the address transmitted from the address control memory 8 (or 9) is within its own address range 1-m (or m+1 to n), the data bus memory 6 (or 1) reads its memory contents and reads the memory contents from the gate 4 (or 5) onto the transmission line 1, and then the information on the transmission line 1 is written to the same address via the gate 4 (or 5).

By repeating such operations, connections between channels using the same address of data bus memory 6 (or 7) are established.

Identification circuits 14 and 15 are address control memories 8,
9 to the data bus memory 6.7, and if the address is in the range of 1 to m of the data bus memory 6, the identification circuit 14 connects the corresponding gate 4, and the address is m+1- of data bus memory 1
In the case of a range of n, the identification circuit 15 connects the corresponding gate 5.

Therefore, the control circuit 13 selects the data bus memory 6.
．． It is possible to use either communication path system 2 or 3 by simply changing the address of communication path system 7.

In the above, the case where the data bus memory is divided into two and the address control memory is duplicated is explained, but the present invention is applicable when the data bus memory is divided into three or more parts and the address control memory is made triple or more. can also be applied.

Furthermore, although the description has been made assuming that the addresses of the data bus memory are continuous from 1 to n, the present invention can also be applied even if the addresses are discontinuous.

In the above configuration, it is possible to detect faults in the data bus memory and address control memory independently in each of the multiple communication path systems using parity checks, etc. However, in the address control memory, multiple installed address control memories are compared with each other. It is also possible by

According to this method, it is possible to directly determine whether or not the contents of a plurality of installed atrus control memories match.

As explained above, according to the present invention, the data bus memory for connecting time-division channels is divided and used by a plurality of communication path systems, and the channels to be connected and the addresses of the memory are Since the address control memory indicating correspondence is completely multiplexed, normal communication path system 1
This has the advantage that any channels can be connected to each other as long as there is one, and the total amount of data bus memory can be greatly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a channel shift switch redundant configuration system of a conventional time division switch, and FIG. 2 is a block diagram of an embodiment of the present invention. 1... Transmission line for transmitting time-division multiplexed channels, 2, 3... Communication path system configured as a channel shift switch, 4, 5... Gate, 6
,7...Data bus memo! ,I,8,9・°・
・°・Address control memo! ,l,10,11・
...Address counter, 12, 13...
Control circuit, 14, 15...Identification circuit.

Claims (1)

[Claims] 1. A time division switch having a data bus memory for connecting time division multiplexed channels, and an address control memory indicating the correspondence between the channels to be connected and the addresses of the data bus memory used for the connection. In the channel shift switch, the data bus memory is divided into a plurality of parts that do not share the same address, and address control memories capable of storing any address of the data bus memory are provided in the same number as the number of divisions of the data bus memory. each divided portion of the data bus memory is assigned a 1:1 correspondence with the divided portion of the data bus memory, and when an address included in the divided portion is specified by the address control memory associated with it, each divided portion of the data bus memory is A channel shift switch redundant configuration system for a time division switch, characterized in that the channel shift switch is configured to only perform write or read operations.