JPS581851B2 - lobus filter - Google Patents

Description

Detailed Description of the Invention As a tuning device for a so-called electronically tuned tuner using a voltage-controlled variable reactance element as a tuning element, the system obtains a binary code corresponding to a channel selected by operating a tuning switch, and By converting the binary code into a pulse width modulation signal and smoothing this pulse width modulation signal with a low-pass filter, a DC voltage whose magnitude changes depending on the selected channel is obtained, and this DC voltage is used as the channel selection voltage. It is conceivable that the signal is supplied to an electronic tuner to receive the selected channel.

According to this tuning device, the tuning voltage can be easily adjusted compared to the conventional one in which variable resistors are provided for the number of channels and the tuning voltage is obtained by adjusting the movable element. Also, by integrating the circuit, various effects such as lower cost can be obtained.

Prior to explaining the present invention, an example of this channel selection device is shown in FIGS.
Let's explain with reference to Figure 3.

FIG. 1 shows the overall configuration of the channel selection device. Numeral 10 is a clock pulse generator which generates a clock pulse Ao having a frequency of, for example, 4 MHz and a period .tau. of 0.25 .mu.sec.

20 is a timing counter that counts this clock pulse Ao, the period is 0.5 μsec, and the pulse width is τ=
Period is 4.096m from pulse A1 of 0.25μsec
Pulse A14 with a pulse width of 2.048 msec
14 by sequentially divided pulses A1 to A14 up to
form a code of bits, so the state of that code is T
= 214 = 163 with 4.096 msec as one cycle period
It changes in 84 ways.

30 is a channel memory, which has addresses corresponding to, for example, 16 reception channels, and each address contains a 14-bit tuning code corresponding to that channel and the fact that the channel is a low channel of VHF broadcasting. A band indication signal indicating whether it is a high channel or UHF broadcast can be stored in memory.

The channel memory 30 is configured such that, after the channel selection code and band instruction signal corresponding to the channel are stored in each address by a program operation described later, the contents are retained even if the power is cut off.

40 is an addressing circuit for addressing, that is, for example, 16 channels to be made to correspond to each desired channel.
switches S1 to S16, and each switch S1 to S16.
an address counter 41 that obtains an addressing signal consisting of a 4-bit code; One end of the switches S1 to S16 is connected to the output lines L1 to L16 of the decoder 42, respectively.
The other end is connected in common to the switching transistor 43
The neon tubes N1 to N16 are connected to the output lines L1 to L16 of the decoder 42, respectively.
The contactor output of the transistor 43 is supplied to an inverter 44, and the output of the inverter 44 is a pulse Ag with a period of 0.128 msec from the timing counter 20 mentioned above.
The output of the NAND circuit 45 is supplied to the address counter 41, and this becomes "0".
The counter 41 increments each time.

The address designation signal from the add counter 41 is then supplied to the channel memory 30.

50 is a band indication signal forming circuit, one end of which is grounded, respectively, for a VHF low channel switch SL, a high channel switch SH, and a UHF switch SU, and a signal obtained at the other end is connected to inverters 51L, 51H, and 51.
NAND circuits 52L, 52H and 52 through U respectively.
The band instruction signal is supplied from the memory 53 to the channel memory 30.

Reference numeral 60 denotes a channel memory control circuit, which is provided with a mode changeover switch 61 and a writing switch 62. During programming, the switch 61 stores the channel selection code and band corresponding to each channel in each address of the channel memory 30 in advance. When the instruction signal is to be memorized, the switch is switched to the contact a side where a positive voltage is obtained, and when the channel is selected, the switch is switched to the grounded contact b side.The signal PA from this switch 661 is supplied to the NAND circuit 63. Further, one end of the write switch 62 is grounded, and the signal obtained at the other end is supplied to the NAND circuit 63 through the inverter 64, and the output of the NAND circuit 63 is sent to the command signal forming circuit 6.
5 and is supplied to the circuit 6 depending on the switching state of the switch 61.
A command signal for writing or reading is supplied to the channel memory 30 from 5.

Further, the signal PA from the switch 61 is applied to the NAND circuits 52L, 52H and 52U of the band instruction signal forming circuit 50 described above.
is supplied to

70 is a channel selection code generation counter, which counts sweep pulses (described later) during programming and generates 14-bit channel selection codes B1 to B14, which are supplied to the channel memory 30; The signal PA from the mode changeover switch 61 is supplied to the NAND circuit 72 through the inverter 71, and the switching transistor 4 of the addressing circuit 40
3 and the collector output of a transistor 74 of a time constant circuit 73 that detects the rise of the power supply voltage are supplied to a monostable multivibrator 75, and the output of the monostable multivibrator 75 is supplied to a NAND circuit 72, The output of the circuit 72 is supplied to this channel selection code generation counter 70 through an inverter 76, and during channel selection, the 14-bit selection codes C1 to C14 read from the channel memory 30 for each channel selection operation are used for this selection. The signals are supplied to the station code generation counter 70 and are directly used as the output codes B1 to B14 of the force counter 70.

80 is a sweep pulse generation circuit for generating the above-mentioned sweep pulses during programming; in this example, either an upward sweep or a downward sweep can be selected, and for each, either a low-speed sweep or a high-speed sweep can be selected. In this case, a low speed up sweep switch 81FU, a low speed down sweep switch 81FD, a high speed up sweep switch 81CU and a high speed down sweep switch 81CD are provided, and each switch outputs a signal of "0" when turned on. This switch 81FU, 81FD
, 81CU and 81CD are sent to the inverter 821.
, 822, 823 and 824 through the NAND circuit 831
, 832, 833, and 834, respectively, and the period from the timing counter 20 is T=4.096 m.
sec pulse A14 is supplied as a high-speed sweep pulse to NAND circuits 833 and 834, and pulse A14 is supplied to a frequency divider 84 and divided by, for example, 1/(64),
Pulses with a period of 262.144 msec from this are supplied as low-speed sweep pulses to NAND circuits 831 and 832, the outputs of NAND circuits 831 and 833 are supplied to NAND circuit 85, and the output thereof is supplied to inverter 86. The outputs of the NAND circuits 832 and 834 are supplied to the NAND circuit 87, and the output is supplied to the inverter 88 to form the downward sweep pulse PD. During programming, these upward sweep pulses PU and downward sweep pulse PD are selectively supplied to a channel selection code generation counter 70.

Reference numeral 90 denotes a pulse width modulation circuit, which has a flip-flop circuit 91, 14 exclusive OR circuits 901 to 914, and an OR circuit 92, as shown in FIG. The period is T=4.
A pulse A14 of 096 msec is supplied to the set side of the flip-flop circuit 91, and at the falling edge of the pulse A14, the flip-flop circuit 91 enters the set state, and its output pulse PW becomes "1". The same bits of the circulation codes A1 to A14 from the timing counter 20 and the channel selection codes B1 to B14 from the channel selection code generation counter 70 are supplied to 914, and the outputs of these exclusive OR circuits 901 to 914 is supplied to the OR circuit 92, and the output PO of this OR circuit 92 is supplied to the flip-flop circuit 91.
The flip-flop circuit 91 enters the reset state and its output pulse PW becomes "0" when it falls from "1" to "0".

Therefore, as is clear from FIG. 3, the circular codes A1 to
At the time when A14 returns from the state (11111111111111) to the state (00000000000000), the output pulse PW becomes "1" and the cyclic code A1 to A1
4 does not match the channel selection codes B1 to B14, the output of one of the exclusive OR circuits 901 to 914 is "1", and therefore the output PO of the OR circuit 92 is "1".
When the circulating codes A1 to A14 match the channel selection codes B1 to B14 within one cycle T, the outputs of the exclusive OR circuits 901 to 914 are all "0".
Therefore, the output PO of the OR circuit 92 becomes "0", the output pulse PW becomes "0", and the output pulse PW becomes
The circulation codes A1 to A14 are (11111111111
111) From the state (00000000000000)
The state remains "1" from the time it returns to the state until it matches the channel selection codes B1 to B14, and the channel selection codes B1 to B1
4 changes, the pulse width of this output pulse PW changes.

100 is a low-pass filter that smoothes the output pulse PW of this pulse width modulation circuit 90 and extracts the average value of the DC voltage, and 110 is its drive circuit.

120 is an electronically tuned tuner, VHF tuner and UHF
A voltage-controlled variable reactance element such as a variable capacitance diode is used as each tuning element, and in the case of a VHF tuner, the tuning coil can be switched between a low channel and a high channel. There is.

Then, according to the band instruction signal from the channel memory 30, switching between the VHF tuner and the UHF tuner and VH
The F tuner is switched between a low channel and a high channel, and the DC voltage from the low-pass filter 100 is supplied to the variable reactance element as a tuning voltage, and the receiving frequency is determined by this tuning voltage.

130 is a video intermediate frequency amplification circuit, and 140 is a video detection circuit.

To program the above-mentioned device, reset the channel selection code generation counter 70, switch the mode selector switch 61 to the contact a side, and if the channel is allocated in the Kanto region, first select "Channel 1". ” is turned on.

When the switch S1 is turned on, the transistor 43 in the addressing circuit 40 is turned on, and its collector output becomes "0", and therefore the output of the inverter 44 becomes "1", and the pulse Ag from the timing counter 20 becomes 1.
The output of the NAND circuit 45 becomes "0" for each address, and the address counter 41 increments.

Then, the 4-bit code from the address counter 41 is converted by the decoder 42, and when the code is determined according to the switch S1, the output line L1 of the decoder 42 is converted.
The output obtained at the switch S1 becomes "0", which turns off the transistor 43 and keeps the output of the NAND circuit 45 at "1", stopping the counter 41 from advancing. An addressing signal of the corresponding code is supplied to the channel memory 30, and the add corresponding to the switch S1 is designated.

Next, the VHF low channel switch SL to which channel 1 belongs is turned on.

When the switch SL is turned on, the output of the inverter 51L becomes "1" in the band instruction signal formation circuit 50,
Since the output PA of the mode changeover switch 61 is "1", the output of the NAND circuit 52L is "0", and this is sent to the channel memory 3 from the memory 53 as a band instruction signal.
0 to the tuner 120 through the tuner 120.
Band switching is performed to the low channel of the VHF tuner.

Next, for example, the high-speed up sweep switch 81CU of the sweep pulse generation circuit 80 is pressed to turn it on.

When the switch 81CU is turned on, the output of the inverter 823 becomes "1", and every time the pulse A14 with a period of T=4.096 msec becomes "0", the output of the NAND circuit 833 becomes "1", and the low-speed upward sweep switch 81FU is off, the output of the inverter 821 is "0", and therefore the output of the NAND circuit 831 is "1", so every time the pulse A14 becomes "0", the output of the NAND circuit 85 is "0", and therefore the output of the inverter 86 is "0". The output PU becomes "1", which is counted by the channel selection code generation counter 70 as a high-speed rising sweep pulse, and the channel selection code B from the counter 70 is generated.
1 to B14 as shown in Figure 3 (000000000
Starting from the state of 00000), timing counter 2
One cycle period T of circulation codes A1 to A14 from 0 = 4.0
It changes sequentially in the upward direction every 96 msec.

Therefore, since the circulation codes A1 to A14 change every time τ = 0.25 μsec, which is the pulse width of the pulse A1, the pulse width of the output pulse PW of the pulse width modulation circuit 30 changes from zero as shown in the figure. Starting from the beginning, it increases by τ every cycle T, and accordingly, the tuning voltage from the low-pass filter 100 increases by, for example, about 2 mV every cycle T, and the reception frequency at the tuner 120 gradually increases.

For example, when one channel is received while looking at the screen, the user releases the high-speed upward sweep switch 81CU to turn it off.

When the switch 81CU is turned off, the supply of the high-speed upward sweep pulse PU to the counter 70 is cut off, and the counter 70 stops advancing, and the tuning codes B1 to B14 from now on are used to instruct the tuner 120 to receive channel 1. It stops with the appropriate tuning voltage being supplied.

Then, the writing switch 62 is turned on.

When the switch 62 is turned on, the output of the inverter 64 in the channel memory control circuit 60 becomes "1", the mode selector switch 61 is switched to the contact a side, and the output PA is "1", so the NAND circuit 63 The output of becomes "0", and the erase pulse PE is first supplied from the command signal forming circuit 65 to the channel memory 30, and the memory contents of the channel memory 30 at the address designated as corresponding to channel 1 are erased as described above. Then, a write pulse PI is supplied, and the channel selection codes B1 to B14 corresponding to one channel from the channel selection code generation counter 70 and the band instruction from the memory 53 of the band instruction signal forming circuit 50 are sent to this address. A signal is written.

Next, when writing "3 channels", the same thing is done, with the mode changeover switch 61 switched to the contact a side, first turn on the address designation switch S2 that should correspond to channel 3, then turn on the low channel switch Turn on SL and then e.g. fast up sweep switch 8
1CU is turned on, and when it is ready to receive 3 channels, the switch 81CU is turned off, and then the writing switch 62 is turned on. In this case, switch 81CU is turned on.
When 1 CU is turned on, the channel selection code generation counter 70 starts from the state where it generates the channel selection code corresponding to the previous one channel, and reaches the state where it generates the channel selection code corresponding to the next three channels. It becomes like this.

In this way, the channel selection code and band instruction signal corresponding to each channel can be sequentially written into each add in the channel memory 30.

When turning on the low-speed ascending sweep switch 81FU instead of turning on the high-speed ascending sweep switch 81CU, the channel selection code generation counter 70 selects the high-speed ascending sweep pulse 64.
Driven by a slow rising sweep pulse with twice the cycle, the tuning codes B1 to B14 from this are 64T = 262.144m
The pulse width modulation circuit 90 changes sequentially every sec.
The pulse width of the output pulse PW increases by τ every 64T, the tuning voltage from the low-pass filter 100 increases by about 2 mV every 64T, and the time required to change the receiving frequency is 64 times that of the above case. .

When turning on the high-speed downward sweep switch 81CD or the low-speed downward sweep switch 81FD, the channel selection codes B1 to B14 from the channel selection code generation counter 70 sequentially change in the downward direction, and in this way the switch 81FU
, 81FD, 81CU, and 81CD as appropriate, it is possible to write a channel selection code that will receive each channel in the best condition.

After completing the program operation in this manner, the mode selector switch 61 is switched to the contact b side.

To select a channel, one of the switches S1 to S16 corresponding to the channel to be selected may be turned on while the power is turned on.

When the power is turned on, the mode selection switch 61 is switched to the contact b side, so the signal PA from this is "0", while the switch 62 is off and the output of the inverter 64 is also "0".
Since it is "0", the output of the NAND circuit 63 is "1",
A read pulse PR is supplied from the command signal forming circuit 65 to the channel memory 30.

When the power is turned on, for example, the address counter 41 of the add specifying circuit 40 is reset, and the code from this point on specifies an address corresponding to one channel, and therefore corresponds to one channel of the channel memory 30. A tuning code corresponding to one channel and a band instruction signal indicating that it is a VHF low channel are read from the address, and the band instruction signal is supplied to the tuner 120 to perform band switching. At the moment when the power is turned on, the transistor 74 is turned on and its collector output becomes "0", but after 50 msec, for example, the transistor 74 is turned off and its collector output becomes "1".
This rise triggers the monostable multivibrator 75, and its output becomes "1" for a certain period of time. In this case, the signal PA from the mode selector switch 61 is "0" and the output of the inverter 71 is "1". Therefore, the output of the NAND circuit 72 becomes "0" for this certain period of time, and therefore the output of the inverter 76 becomes "1", and the tuning code corresponding to one channel is read out from the channel memory 30 by the pulse PB of this certain period of time. is supplied to the channel selection code generation counter 70, and this is directly sent to the counter 70.
The output codes are B1 to B14.

For example, when switch S2 is turned on to receive channel 3, an address designation signal designating an address corresponding to channel 3 is sent from add counter 41 to channel memory 30 by the same operation as during programming.
The channel selection code and VH corresponding to the 3 channels are supplied to the memory 30 from the address corresponding to the 3 channels.
A band instruction signal indicating that it is the low channel of F is read out, and the band instruction signal is supplied to the tuner 120 to perform band switching.0 Then, the address corresponding to channel 3 is specified from the address counter 41 in this way. When the address designation signal becomes available and the transistor 43 turns from on to off, and its contactor output rises from "0" to "1", the monostable multivibrator 75 is triggered by the rise, and the monostable multivibrator 75 is triggered as described above. Similarly, the pulse PB is supplied to the channel selection code generation counter 70, and the channel selection codes corresponding to the three channels read from the channel memory 30 are supplied to the channel selection code generation counter 70, and this is directly input to the counter 70. The output codes are B1 to B14.

Therefore, the pulse width of the output pulse PW of the pulse width modulation circuit 90 becomes a constant value corresponding to the three channels, and the channel selection voltage from the low-pass filter 100 becomes a constant value corresponding to this, so that the pulse width of the output pulse PW of the pulse width modulation circuit 90 becomes a constant value corresponding to the three channels. 3 channels are received.

The same thing applies when trying to receive other channels.

Note that the specific configuration of the pulse width modulation circuit 90 is not limited to the example shown in the figure, and various configurations are possible. For example, by changing the number of pulses within the period T, the overall pulse width within the period T may be changed. You can also do it.

Furthermore, the frequency of the output from the video intermediate frequency amplification circuit 130 is discriminated, and the optimum channel selection code corresponding to each channel is automatically stored in the channel memory by controlling the increment of the channel selection code generation counter 70 based on this discrimination output. It is also possible to write to 30.

By the way, in such a tuning device, if the level of the alternating current component contained in the tuning voltage obtained from the low-pass filter is high, this becomes an anti-damage signal and appears on the screen, which is undesirable.

When using a normal low-pass filter consisting of a resistor 1 and a capacitor 2 as shown in FIG. 4, this alternating current component can be reduced by increasing the capacitance of the capacitor 2.

However, when a capacitor with such a large capacity is used, the response speed to pulsed input signals becomes slow, making it impossible to receive the channel instantly when switching channels. There are drawbacks.

In view of this point, the present invention provides a low-pass filter that can sufficiently reduce the alternating current component without slowing down the response speed.

An example of a low-pass filter according to the present invention and its drive circuit will be described below with reference to FIG.

In the low-pass filter 100 according to the present invention, for example, an input terminal 101 to which a pulse signal is supplied is connected to the collector of a transistor 104 via a resistor 102 and a first capacitor 103, the emitter of the transistor 104 is grounded, and the resistor 102 and the capacitor A connection point 103 is connected to the base of the transistor 104 via a second capacitor 105, and an output end 106 is led out from this connection point.
In addition, there is a resistor 1 between the base and collector of the transistor 104.
07 is connected, and the collector of the transistor 104 is connected via a resistor 108 to a power supply terminal from which a positive DC voltage +VCC is obtained.

Here, these values are selected so that the relationship holds when the resistance values of the resistors 102 and 108 are R and RL, respectively, and the capacitances of the capacitors 103 and 105 are C1 and C2, respectively.

Considering the alternating current component in the low-pass filter 106 configured in this way, if the current flowing through the resistor 102 is io, the current flowing through the capacitor 103 is ic, and the current flowing through the capacitor 105 is ib, then the conditional expression (
From 1), most of the collector current of the transistor 104 flows through the capacitor 103, so ic=hfe·ib, and io=ib+ic.

And the output voltage eo is Therefore, substituting equation (2) into equation (3) yields.

By the way, assuming that the capacitance C0 of the capacitor 2 of the ordinary low-pass filter shown in FIG. 4 is C0=C1+C2, and the resistance value of the resistor 1 is R, and conditional expression (1) is satisfied,
The output voltage eo' obtained from this is as follows.

Therefore, from equations (4) and (5), is guided.

That is, according to the low-pass filter according to the present invention, the alternating current component is suppressed to about 1/(hfe)·(C0)/(C2) compared to a normal low-pass filter as shown in FIG. 4 from equation (6). It is something that can be done.

Furthermore, the response speed of the low-pass filter according to the present invention to a pulse signal is as follows: In the ordinary low-pass filter shown in FIG. 4, the resistance value of resistor 1 is R, and the capacitance of capacitor 2 is
It is equal to that when 0=C1+C2.

Therefore, according to the present invention, the alternating current component can be sufficiently reduced without slowing down the response speed.

Further, a drive circuit 110 for driving this low-pass filter 100 well is configured as follows.

That is, as shown in the figure, an input terminal 111 is connected to the base of an npn transistor 112, and this transistor 11
The emitter of No. 2 is grounded, the collector is connected to the power supply terminal via a resistor 113, and the collector is connected to a resistor 114.
is connected to the base of the pnp transistor 115a through the resistor 116, and connected to the base of the n-type transistor 1 through the resistor 116.
The base and emitter of the transistor 115a are connected via a resistor 117, and the connection point thereof is connected to a power supply terminal.The base of the transistor 115b is grounded via a resistor 118.
The emitter of transistor 15b is grounded, and the transistor 11
The collectors of filters 5a and 115b are commonly connected, and an output terminal 119 is led out from the connection point, which is connected to an input terminal 101 of a low-pass filter 100.

Therefore, when a pulse is supplied to the input terminal 111, at the high potential of the pulse, the transistor 112 is turned on, so that the transistor 115a is turned on and the transistor 115b is turned off, and a charging current is supplied to the low-pass filter 100 through the transistor 115a. flows, and at the low potential of the pulse, the transistor 112 is turned off, so the transistor 115a is turned off, the transistor 115b is turned on, and the discharge current from the low-pass filter 100 flows through the transistor 115b.

That is, since the current flows through the forward internal resistance of the transistor at both the high potential and the low potential of the pulse, the low-pass filter 100 is not affected by the output impedance of the circuit in the preceding stage.
A more stable DC output can be obtained from the low-pass filter 100.

Note that, as shown in FIG. 6, this drive circuit 110 includes two np type transistors instead of the pnp type transistor 115a.
The n-type transistors 115c and 115d may be replaced by directly connected transistors.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing the overall configuration of an example of a channel selection device for explaining the present invention, FIG. 2 is a system diagram of an example of its essential parts, and FIG. 3 is a waveform diagram for explaining the invention. 4 is a connection diagram of an example of a normal low-pass filter, FIG. 5 is a connection diagram of an example of a low-pass filter and its drive circuit according to the present invention, and FIG. 6 is a connection diagram of a modified example of the drive circuit. 100 is a low-pass filter, 110 is a drive circuit thereof, 102 is a resistor, 103 and 105 are first and second capacitors, and 104 is a transistor.

Claims (1)

[Claims] 1. The input terminal to which a periodic signal is supplied is grounded through a resistor, a first capacitor, and the collector/emitter of the transistor in order, and the connection point between the resistor and the first capacitor is connected through a second capacitor. A low-pass filter connected to the base of the transistor and having an output terminal derived from the connection point.