JPS5823016B2 - Senkiyokusouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning device that uses an electronic tuning tuner and converts the output of a reversible counter from analog to analog to form a tuning voltage for the tuner without using a potentiometer.

In order to facilitate understanding of the present invention, a channel selection device to which the present invention can be applied will first be explained.

In FIG. 1, 1 indicates an electronic tuning tuner, in which a variable capacitance diode is provided in each tuning circuit, and a tuning voltage vo formed as described later is used as a reverse bias voltage of the variable capacitance diode. The reception frequency (reception channel) is determined by the level.

In reality, the electronic tuning tuner 1 is given a band switching signal so that it can switch between the high and low channels of VHF and the channels of each UHF band for reception. It is omitted for simplicity.

Reference numeral 2 indicates a video frequency amplifier, 3 a video detector, 4 a video amplifier, and 5 a cathode ray tube.

6 is an AFT circuit which performs frequency discrimination on the output of the video intermediate frequency amplifier 2 via a limiter, shapes the waveform of the discriminated output, and generates AFT correction commands EU and ED shown in FIG. 2A and B. ing.

That is, correction command E. is the normal tuning point f when the receiving frequency is changed.

It becomes “1” from a frequency 1.2 MHz lower than (f
o 50 kHz) ”i maintains the state of “1”,
In a frequency range other than this, □ becomes "0", and the correction command ED becomes "1" from the normal tuning point (fo +50 kHz), resulting in f.

It maintains the state of "1" up to a frequency 1.2 MHz higher than that, and becomes "0" in the other frequency range.

The values of 1.2 MHz and 50 kHz are examples, but (fo±50 kHz) is the best tuning point.

The configuration for forming the tuning voltage will be described below. Reference numeral 11 denotes a channel memory having addresses corresponding to, for example, N receivable channels; each address has n focus selections corresponding to that channel. It is designed to memorize station codes.

This channel memory 11 is a nonvolatile memory that retains its contents even if the power is turned off.

Reference numeral 12 denotes an address designation circuit, which includes N switches S1 for address designation, that is, N switches S1 to be made to correspond to reception channels.
-sN are provided, and by selectively operating any one of switches 81-SN, the corresponding address of the channel memory 11 is designated.

Reference numeral 13 denotes a channel memory control circuit, which is equipped with a mode changeover switch SW1 and a write switch 5W2 (!:), and the mode changeover switch 3 inch SW1 controls the write state (program mode) and read state (tuning mode) of the channel memory 11. is switched, and by operating the write switch SW2 in the write state, the n-focus code is written to a designated address in the channel memory 11.

14 is a counter for generating a channel selection code, which is configured as a reversible counter, and its output (
Binary code) A1 to An step in the increasing direction, and subtract (D
OWN) input causes its outputs A1 to An to step in the decreasing direction.

During programming, the sweep pulses are counted to generate n-focus channel selection codes A1 to An, and these are supplied to the channel memory 11, while during channel selection, they are read from the channel memo IJ-11 for each channel selection operation. The n-bit channel selection codes B1 to Bn are supplied to the channel selection code generation counter 14, and are used as output codes A1 to An.

15 is a pulse generation circuit for generating addition or subtraction manual pulses for the counter 14, and is provided with an upward sweep switch 16U and a downward sweep switch 16D, and each switch generates a signal that becomes "0" when turned on. This switch 16U and 16
The signal from D is supplied to the AND circuit 19.20 through the inverters 17 and 18, while the pulse P1 of a predetermined frequency from the pulse oscillator 21 is supplied to the AND circuit 19.20.
supplied to

Therefore, when the upward sweep switch 16U is turned on, an addition manual pulse is applied to the counter 14 via the AND circuit 19 and the OR circuit 23, while the downward sweep switch 16D
When turned on, a subtraction input pulse is applied to the counter 14 via the AND circuit 20 and the OR circuit 24, and a sweep pulse is applied to the counter 14 while these switches 16U or 16D are pressed.

Also, AND circuits 25 and 26 are connected to OR circuits 23 and 24.
output is supplied.

The output of the pulse oscillator 21 is supplied to the AND circuits 25 and 26, and one of the AND circuits 25 is supplied with the output of the pulse oscillator 21.
A correction command EU is supplied from the FT circuit 6, and a correction command ED is supplied to the other AND circuit 26.

Therefore, when the correction command EU is generated, the AND circuit 2
A correction addition pulse is supplied to the counter 14 through the AND circuit 26 and the OR circuit 23, and a correction subtraction pulse is supplied to the counter 14 through the AND circuit 26 and the OR circuit 24 when the correction command ED is generated.

An AND circuit 22 is provided, and its output is set to "1" only when both switches 16U and 16D are off, and the output of this AND circuit 22 is supplied to AND circuits 25 and 26. Ru.

In other words, priority is given so that no correction pulse is applied while a sweep pulse is being applied to the counter 14.

31 is the tuning code A − obtained from the output of the counter 14.
Let A be the analog signal or tuning voltage V.

change to n This is a DA converter that converts

Various devices can be used as the DA converter 31, but as an example, the channel selection code A1 is converted by a sweep pulse.
A separate timing counter is provided that generates a code for n focus during one cycle when ~An changes, and is driven so that its contents go around once within the above-mentioned one cycle, and from the time when the channel selection code changes, It is possible to use means for forming a pulse with a pulse width up to the point in time when this channel selection code and the output code of the timing counter match, and smoothing this pulse.

To program a reception channel with the above configuration, set the channel selection code generation counter 14 to the reset state, operate the mode switch 3-inch SW1 to set the channel memory 11 to the write state, and then program the channel selection code in the Kanto region. If so, the switch S1 corresponding to channel 1 is first turned on, and the address corresponding to the switch S1 is specified.

Thereafter, in the pulse generating circuit 15, the upward sweep switch 16U is turned on.

When the switch 16U is turned on, the output of the inverter 17 becomes "1", and the addition manual pulse P1 having a cycle of T1 is supplied to the counter 14 via the AND circuit 19 and the OR circuit 23.

FIG. 3A shows this pulse P1, and this pulse P1 causes the channel selection codes A1 to An from the counter 14 to be changed to B in the same figure.
As shown in Figure C, the tuning voltage V from the DA converter 31 starts from a state of (00...0) and gradually changes in an upward direction, as shown in Figure C.

increases by ΔV, and therefore the reception frequency increases.

When the user is ready to receive one channel while looking at the screen, he or she releases the upward sweep switch 16U to turn it off and stop supplying the upward sweep pulse.

Therefore, the tuning codes A1 to An from the counter 14 are the tuning voltages ■ such that one channel is received.

The tuner 1 is stopped in a state where the signal is supplied to the tuner 1.

In this case, the normal tuning point f.

Since the AFT operation works in the range of ±1.2 MHz centered on A correction pulse is applied to the point to pull it to the best tuning point.

Thereafter, the write switch SW2 is turned on to erase the contents of the address specified by the switch S1, and then the channel selection codes A1 to An corresponding to one channel from the counter 14 are written to this address.

The same goes when writing the next 3 channels.
It is sufficient to turn on the switch S2 to be made compatible with 3 channels, then turn on the upward sweep switch 16U, and when it is ready to receive 3 channels, turn off the switch 16U and turn on the write switch SW2.

Next, when selecting a channel, the mode changeover switch SW1 is operated to put the channel memory 11 into a read state.

Then, one of the switches S1 to sN corresponding to the channel to be selected is turned on and the address is specified.

The channel selection codes B1 to Bn at the specified address are read out and written to the counter 14, which directly becomes the output codes A1 to An of the counter 14, and then converted to a predetermined tuning voltage V by the DA converter 31.

, so you can receive the channel corresponding to the operated switch.

In this tuning operation, when a channel corresponding to the tuning code B1 to Bn read from the channel memo IJ-11 is received, if the tuning point deviates from the normal tuning point due to temperature fluctuations, etc., the deviation will be corrected. A correction command ED or ED is generated from the AFT circuit 6 depending on the direction, and a correction pulse is added or subtracted from the channel selection code transferred to the counter 14 until the best tuning point is reached.

In such a channel selection device, the period of the sweep pulse T1 is the operating time of the switch 16U or 16D.

Considering the time required to judge whether the image is good or bad, the response speed of the AFT operation, the frequency range that can be corrected, etc., it cannot be made too short.

Furthermore, since the counter 14 is used to perform AFT, the amount of change ΔV in the tuning voltage for one step when the output codes A1 to An of the counter 14 increments cannot be made very large.

Due to these limitations, coarse tuning is performed using short-cycle sweep pulses so that two types of sweep pulses, short-cycle and long-cycle, can be generated.

Fine tuning was achieved using long period sweep pulses.

However, there is a drawback that fine tuning takes a long time.
Further, there are problems in that the switch operation is troublesome and the configuration is complicated.

The present invention takes the above-mentioned points into account and is designed to shorten the sweep time without causing any trouble.

For this reason, in the present invention, as shown in FIG. 4A, a group of pulses P20 including a plurality of pulses P2 having a synchronization τ is generated based on a switch operation (upward sweep switch 16U or downward sweep switch 16D) from its period τ. These pulses are formed at long time intervals T2, and these pulses are supplied to the counter 14, and the amount of change in the receiving frequency of the tuner 1 due to the group of pulses P2 is selected so as not to exceed the operating frequency range of the AFT.

That is, the output codes A1 to An of the counter 14 change every period τ as shown in FIG. 4B.

Therefore, if a group of pulses P20 includes 5 pulses P2, this will cause the tuning voltage to increase by 5ΔV as shown in FIG. 4C.

changes. The amount by which the reception frequency changes due to the change in tuning voltage (5ΔV) caused by this group of pulses P20 is AF
The frequency should be selected as large as possible without exceeding the operating frequency range of T (approximately 2.4 MHz), for example, 2 MHz.

According to the present invention, the sweep switch 16U or 16D
5τ, for example, 200m5 while either one of the
The reception frequency changes by 2MHz in a short period of time, and then T
2. For example, the receiving frequency is fixed for 1 second, then the receiving frequency changes again by 2 MHz in a short period of time, and then the receiving frequency is fixed for 1 second, and this operation is repeated.

Since the frequency changes every second in steps of 2 MHz, even in the worst case, it will be brought within the APT operating frequency range, and the AFT operation will automatically bring the frequency to the normal tuning point. can.

Therefore, in the device shown in Fig. 1, the frequency is set to 2MHz.
The time required to change z of 4T1 can be shortened to 4τ(T,>τ), and the sweep time is significantly shortened.

However, by setting (T1<T2), the time for determining whether the screen is good or bad and identifying the contents can be extended, and the operation becomes easier.

Furthermore, coarse tuning and fine tuning do not necessarily have to be used separately, which simplifies the configuration and improves operability.

Furthermore, in terms of shortening the sweep time only, the amount by which the reception frequency changes with one pulse is reduced to 2MHzc! It is conceivable to choose a large value such as However, according to the present invention, there is an advantage that the counter 14 etc. can also be used for the AFT.

An embodiment of the present invention for generating a sweep pulse as shown in FIG. 4A will now be described with reference to FIG. 5.

In FIG. 5, reference numeral 41 indicates a pulse oscillator consisting of an astable multi-by-break, which is connected to a pair of transistors 42.
a and 42b, from which a pulse with a period of 100 m5 is generated.

The base of one transistor 42b of the pulse oscillator 41 is connected to the output of the NAND circuit 43 via a diode, and the output of the NAND circuit 43 is connected to the sweep switch 16U or 1.
Turn on either one of 6D.

The pulse oscillator 41 performs the oscillation operation only while the value is "1".

The output of this pulse oscillator 41 is supplied to a binary decimal counter 44, and its output (4 pins) is supplied to a decoder 45.

The counter 44 receives the output of the NAND circuit 43 from the inverter 4.
6, and is cleared by the fall of the output of the inverter 46, that is, by turning on the sweep switch, at which time the output becomes (oooo), and from then on, the pulse oscillator 41
It advances every 100m5 by the output of .

Then, at the output terminal 47 of the decoder 45, a positive pulse P3 having a pulse width of 200 m5 and occurring every second is obtained.

This pulse P3 is supplied to AND circuits 48 and 50, and is also supplied to AND circuit 4 via inverters 52 and 53.
9 and 51.

These AND circuits 48 to 51 are supplied with a pulse P2 of, for example, 10 kHz and a period τ of 0.1 ms from a pulse oscillator 54.

Further, the AND circuit 48 is supplied with the output of the inverter 55 which becomes "1" by turning on the upward sweep switch 16U, and the AND circuit 50 is supplied with the output of the inverter 55 which becomes "1" by turning on the upward sweep switch 16U.
When turned on, the output of the inverter 56 which becomes "1" is supplied, and the AND circuits 49 and 51 are supplied with correction commands EU and ED from the AFT circuit 6.

The outputs of the AND circuits 48 and 49 are supplied to the counter 14 (not shown) as an addition input via an OR circuit 57, which is similar to that shown in FIG. is supplied as a subtraction input to .

In the configuration shown in FIG. 5, when the upward sweep switch 16U is turned on, for example, as shown in FIG. Output terminal 4 of
7, the pulse P3 shown in FIG. 6B is applied to the sweep switch 16U.
Occurs while the is on.

On the other hand, the pulse oscillator 54 is constantly oscillating, and this generates a pulse P2 with a period τ of 0.1 ms as shown in FIG. A group of pulses P2 including pulses P2 of
0 will occur at 1 second intervals.

By supplying these 2000 pulses P2 to the counter 14 via the OR circuit 51, the reception frequency increases to 2M
Hz increases.

In this way, the invention can be implemented.

Furthermore, since the pulse P3 is supplied to the AND circuits 49 and 51 via the inverters 52 and 53, the AFT operation does not work during the positive period (200 ms) of the pulse P3, and only during the negative period (800 ms) of the pulse P3. AFT operation works.

This is done because the same period is used as the sweep pulse and AFT correction pulse, so once the
This is to avoid the inability to raise or lower the reception frequency that has been drawn to the best tuning point in the FT operation.

To achieve a similar purpose, the period of the sweep pulse can be changed to AF
It may be configured to be shorter than the period of the T correction pulse, or a priority may be provided to disable the AFT operation while the sweep switch 16U or 16D is on.

Note that the channel selection device shown in FIG. 1 was configured to turn on the sweep switch 16U or 16D only when programming to store the channel selection code corresponding to the received channel in the channel memory 11; The present invention can also be applied to a configuration in which sequential channel selection is performed in which the channels are received in order, and similar effects can be obtained in this case as well.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an example of an electronic channel selection device to which the present invention can be applied, FIG. 2 is a route diagram used to explain the AFT circuit, and FIG. 3 is a time chart used to explain the operation of the channel selection device. FIG. 4 is a time chart used for explaining the present invention, FIG. 5 is a connection diagram of essential parts of an embodiment of the present invention, and FIG. 6 is a time chart used for explaining the same. 1 is an electronic tuning tuner, 6 is an AFT circuit, 11 is a channel memory, 14 is a reversible counter, 15 is a pulse generation circuit, 16U and 16D are upward and downward sweep switches,
31 is a DA converter, 41.54 is a pulse oscillator, 44
is a counter, and 45 is a decoder.

Claims (1)

[Claims] 1 A selection system that converts the output of the counter into a tuning voltage and supplies it to an electronic tuning tuner, and automatically brings the tuning point to the best tuning point when the reception frequency of this tuner deviates within a predetermined frequency range. In the station equipment, a group of pulses including a plurality of pulses is formed at a time interval longer than the period of each pulse in this group of pulses based on a switch operation, and these pulses are supplied to the counter. ,
A channel selection device that selects an amount of change in the reception frequency of the tuner due to the group of pulses so as not to exceed the predetermined frequency range.