JPS5818679B2 - Analog-Digital Henkan Souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital conversion device, and more particularly to an input device for converting an analog input signal into a digital signal in a control computer, measurement data collection system, etc. and introducing it into a data processing device. It is about improvement.

Generally, this type of analog-to-digital converter i (hereinafter referred to as an A-D converter) is used.

) is one that sequentially selects and scans a large number of analog input signals with a full scale of about 10 mV to 10 V, further converts the analog input signals into digital signals, and then sequentially introduces the digital signals to a data processing device by time division. The number of digits to be converted is 8 bits to 1 binary number.
Six bits, usually about 12 bits, are used, and a total conversion accuracy of about 0.1% is often required.

First, a conventional A/D converter will be explained based on FIG.

In FIG. 1, A1 to An are analog input signals from the outside, and 1 is composed of a relay or a semiconductor switch, etc., and the analog input signals A1 to A are time-divisionally t.
Sequentially at time intervals of 1 to tn? Scanner circuit that sends out
2 is an operational amplifier with excellent linearity, stable gain, and low DC drift; 3 is a sample-and-hold amplifier (hereinafter referred to as S/H amplifier) with excellent retention performance; and 4 is a time-divisionally sequential input by the scanner circuit 1. An analog-to-digital converter (hereinafter referred to as an AD converter) inputs the sent-out analog input signals through the amplifiers 2 and 3 and converts them into digital signals.

), 5 is an analog-to-digital converter.

However, in control computers, analog input signals are taken in through long-distance wiring in electrically noisy environments such as factories or power plants, so they contain various types of interference noise, especially noise from power lines. Commercial frequency common mode noise is large.

For this reason, the scanner circuit 1 and the operational amplifier 2 must have a high common-mode noise suppression ratio and be able to operate without problems even when high-voltage common-mode noise is introduced.
Preferably, it is galvanically isolated from the internal circuit of the digital converter.

This is because if the channels are connected in a direct current manner, if a failure occurs in an obstructive component, a failure in one channel may cause the entire operation to be incorrect or lead to a safety accident.

Figure 2 shows the above scanner section with an isolation transformer and a field effect transistor (Field Effect Transistor).
This is an example of direct current separation using a transistor (hereinafter abbreviated as FET), in which the transistor is made conductive only for the time when a certain channel is selected, and the signal is sent to the operational amplifier 2.

To make the FET conductive, specifically, as shown in Figure 3, another pulse transformer Tll is installed between the gate electrode and the source electrode.
Normally, a gate conduction pulse is applied while maintaining direct current insulation.

In this case, an MO8 type FET with always-off characteristic enhancement is suitable so that it does not conduct when not selected.

Bipolar transistors can also provide always-off characteristics, but the internal voltage drop during conduction is nonlinear, so they are not suitable for analog scanners that require high precision.

In the case of Figure 3, if FET Then, even if it is an enhancement type MO8, the gate voltage O
In (2), when the reverse voltage between the source and the drain exceeds 2 to 3 V, it becomes conductive, so it cannot be used for positive and negative polarity inputs with a relatively large voltage input.

In addition, Fig. 3a shows an FET on one side of the isolation transformer T1.
A switch is inserted, and b is one inserted at the midpoint of the 12 windings of the isolation transformer.

When the analog input is a positive and negative polarity signal, two signals are connected in series in a symmetrical manner, that is, with opposite polarity, as shown in Figure 4.
It is conceivable that one FET could be used for each analog input channel.

Figure 4a shows an input signal applied to the source electrode of the FET. When terminal 1 is at a high potential, X2 is off even if the FET of Xl is conductive, and when terminal 1i is at a high potential, X2 Even if becomes conductive, Xl continues to be off.

In FIG. 4, an input signal is applied to the drain side of the FET, and when the l terminal is at a high potential, X1 is in the off state, and when the 11 terminal is at a high potential, X2 is in the off state.

In FIG. 4C, an FET switch is inserted at the winding neutral point of the isolation transformer T2, which is similar to the case where an OFF state is ensured by two elements in series.

However, as mentioned above, in the practical situation of this type of device, various types of noise, especially large common mode noise at commercial frequencies, are often superimposed.

For example, in Figure 4a, when a high voltage is applied to the input terminals I and 11 in the positive direction in the same phase, the source electrodes of FETs Raise the potential of the primary winding of T1.

Next, when a negative voltage is applied to the input terminal [, 11 in the same phase, xl
, the source of x2 has a negative potential compared to the drain, so unless a positive potential is applied to the gate electrode, the FET
)X2 continues to be off, but the isolation transformer T1
A high voltage is applied between the source and drain of the FET and the positive charge stored in the next winding, and due to the magnitude of the input common mode noise, the maximum source-drain breakdown voltage of DfETXl x2 is exceeded, destroying the FET. It comes to that.

In the case of Figure 4, when the common mode noise added to 1.11 is negative, X1 and X2 are conductive, and when the common mode noise is positive, X1 and x
2 is in the off state, but depending on the size of the common mode noise, the FE
TX1 and X2 are destroyed.

In FIG. 4C, the case is exactly the same as in case b, but when the FET is turned on, the charge is accumulated not in the winding of the isolation transformer T2 but in the circuit including the pulse transformer T13.

Although the case where the FET is an N-channel device has been described above, a similar problem will occur if the FET is a P-channel device simply by reversing the positive/negative relationship.

This invention does not cause the above-mentioned disadvantages even in severe situations where both positive and negative analog voltages are input and high voltage common mode noise is added, and the analog voltage can be operated normally and with high reliability.
Various concrete measures are provided to obtain a digital conversion device, and the drawings will be described in detail below.

In the circuit shown in Fig. 5, the electric charge caused by the common mode noise that causes breakdown of the FET in Fig. 4C is the pulse transformer T.
It is accumulated in the circuit between the source and the gate of the FET including FET 3.

In this case, the constant voltage diodes are FETs Xl, X2
If it is inserted directly between the source and drain of the insulating transformer T2, current will flow through the primary winding of the isolation transformer T2 as the common-mode noise voltage rises and falls, which is inconvenient.
It is preferable to insert a constant voltage diode between 11 and the source electrode of the FET.

As described above, in the analog-to-digital converter according to the present invention, the enhancement type MO8-FET is combined with a constant voltage diode as described above, and the polarity of the two-wire analog input signal for each channel is both positive and negative. This has the effect of providing an effective and highly accurate isolated scanner even when large common-mode noise is superimposed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional analog-to-digital converter, and Figure 2 shows the scanner circuit using an isolation transformer and FE.
A block diagram showing an example of a known circuit configured with T, FIG. 3a
, b is a circuit diagram showing a specific example of a switch using an FET, FIG. FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. The same reference numerals in the figures indicate the same or corresponding parts, and A
1 to An are analog input signals, 1 is a scanner circuit, 2 is an operational amplifier, 3 is a sample-and-hold amplifier, 4 is an analog-to-digital converter, 5 is an analog-to-digital converter, X is a field effect transistor, T1 to Tn is an isolation transformer, T11 to T13 are FET driving pulse transformers, and Z is a Zener diode.

Claims (1)

[Claims] 1. A scanner circuit that sequentially and time-divisionally captures multiple channels of two-channel, positive and negative polarity analog input signals using isolation transformers and electronic switches provided for each channel, and converts the sequentially captured analog signals into digital signals. In an analog-to-digital converter equipped with an analog-to-digital converter for converting, one of the above-mentioned isolation transformers
The next winding is divided into two, the undivided terminals of the above-mentioned - next winding are connected to the two input wires, and the respective drain electrodes are connected to each terminal of the winding created by the above-mentioned division. , two time-division switch field effect transistors whose source electrodes are interconnected are provided, and a constant voltage diode is provided between the source electrode of the field effect transistor and the two input lines, and the The above field effect transistor is connected to the cathode side of each voltage regulator diode.
An analog-to-digital conversion device characterized in that the input line is connected to the input line when the field effect transistor is a channel, and to the source electrode of the field effect transistor when the field effect transistor is a P channel.