JPS6010450B2 - Analog-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital conversion device, and more specifically, an input device that converts an analog input signal into a digital signal in a control computer, measurement data collection system, etc. and introduces it into a data processing device. This relates to improvements in equipment.

Generally, this type of analog-to-digital converter (hereinafter referred to as A
- It is called a D conversion device.

) is a device that sequentially selects and scans a large number of analog input signals with a full scale of about low V to 10 V, further converts the analog input signals into digital signals, and then sequentially introduces the digital signals to a data processing device by time division. Yes, the number of digits to be converted is 8 bits to 16 binary numbers.
Bits, usually about 12 bits, are used, and a total conversion accuracy of about 0.1% is often required. First, a conventional A/D converter will be explained based on FIG. 1.

In FIG. 1, A, ~An are analog input signals from the outside, and 1 is composed of a relay or a semiconductor switch, etc., which inputs the analog input signals A, ~An in a time-division manner t.
, ~tn scanner circuit that sequentially transmits data at time intervals of 2
numeral 3 is an operational amplifier with excellent linearity, stable gain, and low DC drift; numeral 3 is a sample-and-hold amplifier (hereinafter referred to as S/day amplifier) with excellent holding performance; and numeral 4 is a time-divisionally sequential transmission of signals by the scanner circuit 1. An analog-to-digital converter (hereinafter referred to as an A-D converter) inputs the analog input signals obtained through the amplifiers 2 and 3 and converts them into digital signals.

) 10 is an analog-to-digital converter. However, analog input signals for control computers, etc. are taken in through long-distance wiring in electrically noisy environments such as factories or power generation stations, so they contain various types of interference noise, especially on power lines. The commercial frequency in-phase noise (common mode noise) from

For this reason, it is necessary that the scanner circuit 1 and the operational amplifier 21 have a large common-mode noise suppression ratio and can operate without any problem even if a large amount of common-mode noise is introduced. It is preferable that the internal circuits of the digital converter be isolated in terms of DC.This is because if they are connected in DC, a failure in one channel will protect the entire operation in the event of a failure in a component circuit. This is because there is a risk that the above-mentioned scanner section is connected to an isolation transformer and a field effect transistor (Field Effect Transistor).
ldEffectTra ship istor. This is an example of DC separation using a FET (hereinafter abbreviated as "FET"), and "the transistor is made conductive only for the time when a certain channel is selected, and the transistor is sent to the operational amplifier 2. Specifically, to make the FET conductive, a third As shown in the figure, it is usual to apply a gate conduction pulse while maintaining DC insulation between the gate electrode and the source electrode by another pulse transformer T,.

In this case, it is appropriate that the FET be of the normally-off characteristic enhancement type MOS type so that it does not conduct when not selected. Bipolar transistors can also provide always-off characteristics, but the internal voltage drop during conduction is nonlinear, so they are not suitable for use in analog scanners that require high precision. In the case of Figure 3, if the FETX is an N-channel type, there is no problem if the polarity of the input signal A is such that i is a positive high potential and U is a low potential, but conversely, if terminal i is a low potential and terminal 5 is a high potential, then Even in an enhancement type MOB, the source at the gate voltage OV.

When the reverse voltage between the drains is 2 to 3 V or more, the conductive state is reached, so a relatively large voltage input cannot be used for positive and negative polarity inputs. Note that FIG. 3a shows an isolation transformer T with an FET switch inserted on one side of the input, and Lb with an isolation transformer T inserted at the midpoint of the winding. If the analog input is a bipolar signal, it may be possible to use two FETs connected in series in a symmetrical manner, that is, inversely sacrificial, as shown in FIG. 4, for each analog input channel.

Figure a shows how to apply an input signal to the source electrode of the FET. X
Even if 2 becomes conductive, X continues to be off. Figure 4b shows an input signal applied to the drain side of the FET, and when the i terminal is at a high potential, X is in the off state.If the ii terminal is at a high potential, X2 is in the off state. This is similar to the case of point b, where an FET switch is inserted into the winding neutral point of the isolation transformer T2, and the off state is ensured by two elements in series.However, as mentioned above, in the practical situation of this type of device, various noises, especially In-phase multiple tones with large commercial frequencies are often superimposed.

For example, in Fig. 4a, if a high voltage is applied to input terminals i and ii in the positive direction in the same phase, FETX, ? A positive voltage is applied to the source electrode of X2 compared to the drain electrode, and it becomes conductive, raising the potential of the primary winding of the isolation transformer T. Next, when a negative voltage is applied in the same phase to the input state i, U',
Since the source of X2 has a negative potential compared to the drain, unless a positive potential is applied to the gate electrode, FETX, ? X2 continues to be off, but a high voltage is applied between the source and drain of the FET and the positive charge stored in the primary winding of the isolation transformer T, and depending on the magnitude of the input common mode noise, the FET ,, the maximum source-drain breakdown voltage of X2 is exceeded and the FET is destroyed. In the case of Fig. b, if the common-mode noise added is negative, X,, X2 are conductive, and when the common-mode noise is positive, X,, X2 are off, but depending on the magnitude of the common-mode noise. is FETX,? X2 ends up destroying it. In Fig. 4c, it is exactly the same as in case b, but FE
When T conduction is appropriate, the charge is accumulated not in the winding of the isolation transformer T2 but in the circuit including the pulse transformer T,3. Although the case where the FET is an N-channel device has been described above, if the FET is a P-channel device, the same problem will occur if the positive/negative relationship is reversed. This invention can be used in both positive and negative directions.

This invention provides various concrete measures to obtain a normal and highly reliable analog-to-digital converter that does not cause the above-mentioned disadvantages even under severe conditions such as input of analog voltage and high voltage common mode noise. The drawings will be explained in detail below. Fig. 5 is a circuit diagram showing an embodiment of the present invention. The circle is an isolation transformer whose primary winding is divided into two parts, and the primary winding of this isolation transformer T2 is F to connect to the line
The feature is that the source electrode is used instead of the drain of the ET.

As shown in Figure 6, many FETs have similar structures, with the source S and drain D being symmetrical with respect to the gate G. The side to which the pond end is connected is considered to be the source electrode. By connecting in this way, the series connection of two FETs becomes a pair of drain electrodes, and since there is no ground capacitance or conductor volume between which to accumulate static charge other than the wiring, it is necessary to insert a constant voltage diode between them. Even without this, it is possible to create a configuration in which the FET is not destroyed by common mode noise. In particular, two FETs can be combined into one using integrated circuit technology.
It is advantageous if the structure is formed on a single silicon chip. However, in this configuration, it is not possible to use only one pulse transformer, so two pulse transformers T, .
, T,2, or one pulse transformer T,3 may be provided with two secondary windings as shown in FIG. 5b. As described above, according to the present invention, common mode noise can be removed with a simple configuration.

Brief explanation of the drawings Figure 1 is a block diagram of a conventional analog-to-digital converter, and Figure 2 shows a scanner circuit using an isolation transformer and an FE.
A block diagram showing an example of a known circuit configured with T, FIG. 3a
, b are circuit diagrams showing specific examples of switches using FETs, Figures 4 a, b, and c are circuit diagrams that can be easily analogized to switches when the analog input signal is a two-wire positive and negative signal. Figures a and b are circuit configuration diagrams showing one embodiment of the present invention, and Fig. 6 is a diagram showing the structure of an N-channel enhancement type MOS-FET for explaining the present invention.

The same reference numerals in the figures indicate the same or corresponding parts, and A
, ~An is an analog input signal, 1 is a scanner circuit, 2 is an operational amplifier, 3 is a sample-and-hold amplifier, 4 is an analog-to-digital converter, 5 is an analog-to-digital converter, X is a field effect transistor, T, ~ Tn is an isolation transformer, T, . ~T, 3 is a pulse transformer for FET driving, Z is a Jenner diode, D is a normal diode,
R is a resistor and C is a capacitor.

Leopard 1 Hall 2 hammers Traditional 3 illustrations Figure 4 key 5 diagram Sadao figure

Claims (1)

[Claims] 1. A scanner circuit that sequentially receives multiple channels of two-wire positive and negative polarity analog input signals in a time-sharing manner using an isolation transformer and an electronic switch provided for each channel;
In an analog-to-digital converter equipped with an analog-to-digital converter that converts sequentially captured analog signals into digital signals, the primary winding of the isolation transformer is divided into two, and two field-effect transistors are connected to the primary winding of the isolation transformer. In this case, the windings and the source electrodes of the field effect transistors are connected to each other, the drain electrodes are connected to each other, and a conductive wire is connected between the source electrode and the gate electrode of both transistors. An analog-to-digital converter characterized in that another isolation transformer is connected to provide a pulse input.