JPS5818709B2 - Data transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control method in a data processing device that has a buffer storage in addition to a main memory, and in particular, the present invention relates to a data transfer control method in a data processing device that has a buffer storage in addition to a main memory. The present invention provides a data transfer control method that minimizes the downtime of a processor when transferring data from a device.

In order to speed up data processing, the data processing device is equipped with a buffer storage with fast access time in addition to the main memory, and during data processing, part of the data stored in the main memory is transferred to the buffer storage. In addition, data processing is performed using this high-speed buffer memory as much as possible.

In such a system, if the table information necessary for data processing is transferred to the buffer storage, the necessary data is read from the main memory and stored in the buffer storage, while at the same time it is transferred to the processor execution unit. A so-called bypass method is used, in which the data is bypassed and transferred and used for data processing.

However, when data is transferred from the main memory to the buffer storage, data is transferred in blocks of 32 bytes, 64 bytes, or the like.

Then, this data in units of blocks is divided into 8 bytes each and the data is transferred multiple times, for example, in the case of 32 bytes, the data is divided into 4 times.

That is, as shown in FIG. 1, when transferring 32 bytes of data, for example, it is divided into four sections 0 to 3 of 8 bytes each.

This data is then transferred from, for example, section 2, in response to a request from the processing device.

In this case, data transfer is completed in the order of section 2 - section 3 - section ○ - section 1.

According to the above bypass method, the data of the first division 2 is
While being stored in the buffer storage, it is also transferred to the processor execution unit and used for data processing.

However, even if the processing device attempts to use the data in section 3 subsequent to section 2, the data in section 3 cannot be used subsequently.

That is, following the previously stored data of section 2, all of the data of section 3 - section 0 - section 1 is accumulated in the buffer register, and the valid bits corresponding to the block in question are stored on the buffer storage. It has the disadvantage that it cannot be used until it is turned on, and during that time, data processing has to wait.

In the case of data processing, the stored data is often used consecutively, so in such cases, the data of Category 2 is followed by the data of Category 3 - Category 〇 - Category 1, etc. It is hoped that this will be possible, since data processing will be faster if continuous data is readily available.

The present invention aims to provide a data transfer method that makes this possible. In a data processing system comprising: when transferring data from the main storage device to the buffer storage, the transfer data in units of blocks is divided into a plurality of sections, and the first transfer section of the transfer data in units of blocks is divided into a plurality of sections. , to the buffer storage, transfers it to the processing unit of the processor, further transfers the next transfer section of the block to the buffer storage, and temporarily stores it in a register during this transfer. It is characterized by

An embodiment of the present invention will be described below based on FIG.

In the figure, 1 is a buffer memory consisting of a tag section 1-1 and a data section 1-2, 2 is a store 9 register, and 3 is a buffer memory.
4 indicates a fetch contention register, 4 indicates a move register, 5 indicates an execution address register, 6 indicates a comparison circuit, and 7 indicates a memory address register.

During data processing, the processor first accesses the buffer memory 1 to obtain the necessary data, and attempts to obtain the data from the high-speed buffer memory.

That is, the address of the necessary data is transmitted to the execution address register 5, and the tag section 1-1 of the buffer memory 1 is searched.

The tag section 1-1 stores, for example, the address and valid bit of data stored in the data section 1-2.

Therefore, this required data is in the data section 1-2.
If the data is stored in the tag section 1-1, the comparison circuit 6 compares the address of the necessary data with the address stored in the tag section 1-1, thereby obtaining a match output.

In response to this match signal, the data stored in the data section 1-2 is transferred to the execution section of the processor via the fetch register 3.

If the buffer memory 1 does not contain enough data necessary for data processing, it is necessary to access the main storage device and transfer the necessary data to the buffer memory 1.

That is, the memory address register 7 reads data from the main memory (not shown) and stores and stores the data.
Transfer to buffer memory 1 via register 2.

For example, the data to be transferred has 32 data blocks.
When it is composed of bytes, as shown in Figure 1, 8
It is divided into four sections 0 to 3 separated by bytes, and the section requested by the processor is transferred first and then one after another.

If the processor requests partition 1, partition 1
- Section 2 - Section 3 - Section O are transferred in this order.

Partition 1, for which the processor was requested,
At the same time as being stored in the data section 1-2 of the memory 1, it is sent to the processor via the fetch register 3,
Used for data processing.

In the case of the present invention, a move register 4 is prepared,
Section 2, which is sent out following section 1, is stored in buffer register 1 and also in the move register 4, turning on the valid bit V of said register 4.

When the processor processes data, a protrusion occurs when the above-mentioned necessary category 1 is followed by category 2.

However, according to the present invention, the data in section 2 is moved.
Since it is stored in register 4, the processor sees that the valid bit of move register 4 is on and fetches the contents of move register 4.
By moving it to the register, the data in section 2 can be used immediately.

The size of the move register 4 is not limited to 8 bytes, which is enough to store only one section of data, but can be large enough to store data of two sections, or even 3 bytes, if necessary.
Appropriately sized items can also be used for classification.

As explained above, according to the present invention, data of consecutive sections are stored in the move register during data transfer, so that the processor can perform data processing following the first section. It can be used immediately when using data in the following categories.

Therefore, even if the buffer memory cannot be used during the period when the entire data of one block of 32 bytes is being transferred from the main memory to the buffer memory, the data processing operation of the processor will still transfer the contents of the move register 4. The processing operation can be executed continuously without being stopped.

That is, data processing speed can be increased.

Recently, there has been a tendency for the control unit of buffer memory to increase in size from 32 bytes to 64 bytes or 128 bytes.

If this happens, during the information transfer to the buffer memory,
That is, the buffer storage remains in an access-stopped state until the entire block, such as 64 bytes or 128 bytes, has been transferred.

For this reason, if the conventional method is used, the longer the block degree is, the longer the access suspension period may be.

However, in the present invention, a move register is provided,
Since the transferred data is temporarily stored and can be used while being transferred to the buffer register, there is no need to stop data processing by the processor.

Therefore, when the transfer block unit is large, it can be expected that the data processing speed will be further improved.

Recently, when transferring data by block loading, it is now possible to divide data into 8-byte blocks and transfer data discontinuously, taking into account the transferable intervals, instead of contiguously, in order to use main memory efficiently. It is being done.

Especially when this happens, use the move register.
By temporarily storing data that may be used next, the contents of the move register can be used for data processing as long as it is transferred to the move register. becomes.

Therefore, data processing speed can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating divisions during data transfer, and FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a buffer memory, 2 is a store register,
3 is a fetch register, 4 is a move register, 5 is an execution address register, 6 is a comparison circuit, and 7 is a memory register.
Each address register is shown.

Claims (1)

[Scope of Claims] 1. In a data processing system comprising a main storage device and a buffer storage for transcribing a part of data stored in the main storage device, data is transferred from the main storage device to the buffer storage. At this time, the transfer data in blocks is divided into a plurality of sections, and the first transfer section of the transfer data in blocks is stored in the buffer storage and transferred to the processing section of the processor, and further A data transfer control method characterized in that the next transfer section of the block is transferred to the buffer storage and temporarily stored in a register during the transfer. 2. A patent characterized in that, when a section of the block is accessed, a section temporarily stored in a register is used until all sections of the transferred data in blocks have been stored in the buffer storage. A data transfer control system according to claim 1.