JPS5818738B2 - cathode ray display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cathode ray display panel capable of constructing a relatively large display surface.

Generally, a cathode ray display panel has a three-terminal switching element such as a MOS-FET formed on an insulating substrate such as glass, and a plate electrode coated with a phosphor is connected to the drain electrode of the three-terminal switching element.

By selectively driving this three-terminal switching element and applying a predetermined voltage to the plate electrode, the phosphor is excited by the low-speed electron beam to emit light.

In order to enlarge this display surface, this MOS-F
The production yield of integrated circuits including ET and the like must be considered.

That is, FIG. 1 is a partially detailed perspective view showing a display substrate of a conventional cathode ray display panel.

In the figure, 1 is an insulating substrate such as a glass substrate, 2 is a silicon chip, 3 is a plate electrode connected to a drain electrode (not shown), 4 is a phosphor coated on this plate electrode 3, and 5 is on the silicon chip 2 6 is a gate pad on the silicon chip 2, 7 is a substrate lead, 8 is a source lead, and 9 is a gate lead.

However, in conventional cathode ray display panels, (a) wiring between substrate leads and source leads is complicated;

(B) There is always a space (dead space) between the silicone/chip, (C) It is difficult to die bond a large number of silicon chips on the sub-base 1-rate lead with good positional accuracy, ( 6) Wire bonding between the source lead and the source pad on the silicon chip is very difficult because the distance is short and there are steps between the wires.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a cathode ray display panel that does not require strict control of positional accuracy during wire bonding and can easily be constructed with a relatively large display surface.

In order to achieve such an object, the present invention forms a substrate electrode, which is a common electrode, on an insulating substrate such as glass, and connects a plurality of three-terminal switching elements to their drains. A plurality of semiconductor chips each having plate electrodes coated with phosphor are arranged in the row and column directions so that the plate electrodes are staggered, and gate line connection pads and gate line connection pads on each semiconductor chip are arranged. The source line connection pads are commonly connected, and will be explained in detail below using an example.

FIG. 2 is a plan view showing an embodiment of the display substrate of the cathode ray display panel according to the present invention.

In the figure, 10 is a substrate lead formed on an insulating substrate 1, 11a and 11b, 12a and 12.
b, ~16a and 16b are chips fixed on the substrate electrode 10, respectively.

In order to simplify the explanation, FIG. 2 shows a case in which two chips 11a to 16b are arranged horizontally and six chips are arranged vertically, alternately shifted by one pixel in each row.

In the chips 11a-16b, 17a and 1γb are gate line connection pads 18a-1 connected to the gate electrodes of three-terminal switching elements (not shown).
8f and 19a to 19f are gate line connection lines, 20
2 to 20C are source line connection pads connected to the source electrode of a three-terminal switching element (not shown); 213 to 2;
1h is a source line connection line, and 22 is a phosphor coated on a plate electrode 23 connected to a drain electrode (not shown).

Next, the assembly operation of the display substrate of the cathode ray display panel according to the above configuration will be explained.

First, a substrate electrode 10 is formed on an insulating substrate 1 made of glass or the like.

Then, a chip 11a is placed on this substrate electrode 10.
Arrange ~16b.

Next, for horizontal line bonding, connect the gate line connection lines 18a to 18f to the gate line connection pad 17a, and then connect the other gate line connection lines 19a to 19f to the gate line connection pad 17b and the gate line connection pad 17b. It is connected between the connection pad 17a.

Next, for vertical line bonding, each of the source line connection lines 21a to 21h is connected to the source line connection pads 20a to 20c for each vertical pixel.

Next, the display operation of the cathode ray display panel having the above configuration will be explained.

CI) First, when driving one row of chips arranged horizontally at a time, the gate line connection lines 182 to 18f are scanned as described above, and the source line connection lines 21a to 21h are scanned for each access time. The signals are input at the same time.

Now, if 18a is accessed, 21a.

21c, 21e, 21g... are input, for example, the source line connections 12lb and 21d of the chip 11a
Since the phosphor 22 is located below the phosphor screen, when there is a possibility that the luminescence state of the phosphor screen is different and uneven brightness occurs, it is necessary to apply an appropriate positive potential to the north line connecting lines 21b and 21d.

(n) In addition, when driving two wide chips arranged horizontally at once, the three-terminal switching element is made into an N channel, and the gate electrode is turned on when the potential is positive, and The source line connection line according to the above explanation is now a gate line (gate line 18a=f according to the above explanation is assumed to be a source line) 21a
, and 21b, 21C, and 21d, . . . , two lines are set as a scanning electrode line (gate electrode line).

Note that, of course, a negative potential may be applied to unselected scanning electrode lines.

Next, when performing multicolor display, for example, each chip 11a
It can be easily constructed by setting the phosphors at the left end position of 16b to red, green, and blue, and sequentially forming the phosphor screen.

It goes without saying that the source line and gate line in the above description may be interchanged.

As described above in detail, the cathode ray display panel according to the present invention has the following advantages: (1) dead space is extremely reduced, (g) wiring on an insulating substrate is simplified, and wiring during die bonding of chips is minimized; The positional accuracy does not need to be strict (wire bonding with zero step difference is almost eliminated, improving yield and reliability).The seams between the chips are noticeable due to the fact that each pixel is staggered and arranged in a staggered manner. The distance between pads for vertical line bonding is increased, which makes work easier, (■) colorization becomes easier, and (J) large screens can be easily constructed.

[Brief explanation of drawings]

FIG. 1 is a partially detailed perspective view showing a display substrate of a conventional cathode ray display panel, and FIG. 2 is a partially detailed plan view showing an embodiment of the display substrate of a cathode ray display panel according to the present invention. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Crycon chip, 3... Plate electrode, 4... Fluorescent material, 5... Source pad, 6 ...Gate pad, 7...Substrate lead, 8...
...Source lead, 9...Gate lead,
10...Substrate electrode, 11a to 16b
...Chip, 17a and 17b...
Gate line (or source line) connection pad,
18a to 18f and 19a to 19f... Gate line (or source line) connection lines, 20a to 2
0c...Source line (or gate line) connection pad, 21a-21h...Source line (or gate line) connection line, 22...Opening light body, 23... ...Plate electrode.

Claims (1)

[Claims] 1. A plurality of three-terminal switching elements, a plurality of plate electrodes connected to the drains thereof and coated with a phosphor, on an insulating substrate on which a substrate electrode as a common electrode is formed on the entire surface. The plurality of semiconductor chips are arranged in a staggered manner in the row and column directions, and plate electrodes arranged on each semiconductor chip are arranged in a staggered manner. A cathode ray display panel characterized in that gate line connection pads and source line connection pads provided are commonly connected. 2 For each semiconductor chip, change the emission color of its phosphor to red,
2. The cathode ray display panel according to claim 1, wherein the cathode ray display panel is green and blue, and bonding pads of the same color are connected by wire bonding to enable multicolor display.