JPS5818739B2 - cathode ray display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cathode ray display panel in which a plurality of semiconductor substrate chips each having a plurality of integrated switching elements are combined to increase the display area.

A conventional cathode ray display panel has a plurality of three-terminal switching elements such as MOS-FETs arranged in a matrix on one semiconductor substrate, the first terminal of which is connected to the phosphor layer, and the second terminal of the switching element connected to the phosphor layer. The third terminals are connected in common to form an anode.

And the second above. A combination of selectively applying a voltage to the third terminal and selectively driving the three-terminal switching element to selectively apply a voltage to the phosphor layer and excite the phosphor with a low-speed electron beam to emit light. The details are as shown in, for example, Japanese Unexamined Patent Publication No. 105768/1983.

Note that the first to third terminals are, for example, a P-channel FE.
When T is used, they correspond to the drain, source, and gate, respectively.

In order to increase the display area of a cathode ray display panel with such a structure, it is necessary to (A) make one semiconductor substrate chip itself large and integrate and house a large number of switching elements on it; (B) ) There are two possible methods: combining multiple small semiconductor substrate chips side by side.
From the viewpoint of yield in producing semiconductor substrate chips, the normal method (b) is adopted.

FIG. 1 shows a case where two semiconductor substrate chips 1 and 2 are combined, and FIG. 2 shows a case where four semiconductor substrate chips 4 to 7 are combined.

In FIG. 1, reference numeral 3 denotes a phosphor layer, which is omitted in FIG. 2 but is similarly provided.

In such a method, the second
．． In order to connect the third terminal to the drive circuit, at least two sides of each semiconductor substrate chip end (areas where pads for wire bonding are to be formed are required).

For example, in the case of FIG. 2, seams 9a to 9d occur between the semiconductor substrate chips 4 to 7, but it is possible to secure a region 8 for forming the above-mentioned bonding pad on the solid side of the chip.

However, when nine semiconductor substrate chips 14 are arranged in a row as shown in FIG.
A drop occurs.

Therefore, an object of the present invention is to provide the following when a large-screen cathode ray display panel is constructed by combining a plurality of integrated chips.
An object of the present invention is to provide a cathode ray display panel in which the screen is not divided by the bonding pads even if the bonding pads are formed at the joints of the integrated chips.

In order to achieve such an object, the present invention arranges phosphor layers in a staggered manner on each semiconductor substrate, and provides a bonding pad between each phosphor layer constituting the phosphor layer array at the edge of the substrate. It is something.

Hereinafter, the present invention will be explained in detail using Examples.

FIG. 41 is a plan view showing an embodiment of the present invention.

In the figure, 10 is a phosphor layer constituting pixels arranged in a staggered manner on a semiconductor substrate 14, and 11 and 12 are two rows in an empty area between the phosphor layers 10 arranged at the edge of the semiconductor substrate 14. Two rows of horizontal connection pads and two vertical connection pads are formed, and 13 is a bonding wire.

Although not shown in the figure, a three-terminal switching element is formed on the semiconductor substrate 14 in correspondence with each phosphor layer 10, the first terminal of which is connected to the phosphor layer 10, and the second terminal connected to the phosphor layer 10. The third element is commonly connected to the horizontal connection pad 11 and the vertical connection pad 12, respectively.

With this configuration, even if bonding pads (horizontal connection pads 11 and vertical connection pads 12) are provided at the joints of the semiconductor substrate 14, they will not be arranged in a straight line but in a zigzag pattern. Since the arrangement is such that the phosphor layer 10 is present between them, there is no non-light-emitting break in the light-emitting display as a whole.

As explained above, according to the present invention, when a plurality of semiconductor chips are combined, even if a bonding pad is placed at the joint, it is not noticeable, so a large screen can be formed with high density. There is an effect that can be formed.

[Brief explanation of drawings]

1 to 3 are plan views showing examples of combinations of semiconductor chips, and FIG. 4 is a plan view showing an embodiment of the present invention. 10... Phosphor layer, 11... Horizontal connection pad (ponding pad), 12... Vertical connection pad (ponding pad), 13...
...Bonding wire, 14...Semiconductor substrate.

Claims (1)

[Claims] 1 A three-terminal switching element whose first terminal is connected to a phosphor layer is placed in a multi-IJ rack, and a plurality of semiconductor substrates are assembled in which the second and third terminals of each element are commonly connected. In the cathode ray display panel in which an anode is formed, the phosphor layers are arranged in a staggered manner on each of the semiconductor substrates, and a bonding pad is provided between each phosphor layer constituting the phosphor layer array at the end of the semiconductor substrate, A cathode ray display panel characterized in that the plurality of semiconductor substrates are electrically connected to each other by bonding wires that connect between the bonding pads.