JPS5820146B2 - hand warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (In5u
rated Gate F 1eld Effect
The present invention relates to a semiconductor memory circuit using a transistor (abbreviated as IG-FET).

Generally, P-channel type IG-FET and N-channel type IG-FET
(, -FETs are fabricated on the same semiconductor substrate.Complementary memory circuits include dynamic and static types.
Static memory is now the mainstream, as it lacks the low power consumption performance that is a feature of complementary circuits.

By the way, although complementary circuits have low power consumption, their switching characteristics often operate at lower speeds than P-channel only circuits or N-channel only circuits, especially in high-speed operation such as computer memory. It is difficult to apply this method to applications that require

The access time tAcc of a static memory is the sum of the propagation delays of each circuit block, and can generally be expressed by the following equation.

tAcc =A t 10Ct +S 10θt...
...(1) In this formula (1), At is the delay time in the address and address decoder circuit, Ct is the read time for the memory cell to read data to the common input/output line, and St is the common input/output line The time θt that depends on the sensitivity of the sense circuit that detects the information read out is the delay time in the output control section and the output driver circuit.

On the other hand, there are two main manufacturing technologies for insulated gate type semiconductor integrated circuits: silicon gate technology using polysilicon for the gate electrode and aluminum gate technology using aluminum for the gate electrode.

If you look at these from a pattern design perspective, the former technology is better suited for efficient high-speed operation due to the addition of a polysilicon layer, which provides more flexibility in wiring than the latter technology. It is possible to design various patterns.

However, silicon gate structures are generally complex, require many steps, and have a high yield, and it is often more advantageous to adopt an aluminum gate structure in terms of cost.

FIG. 1 is an example of a matrix of memory cell groups.

In the figure, 1 is a row (address) decoder and driver circuit, 2 is a row decoder output line, 3 is an input/output line (data bus), 4 is a memory cell, 5 is ■10 (input/output) controller and sense amplifier circuit , 6 are column decoders and driver circuits.

FIG. 2 is a pattern plan view of one memory cell portion shown in FIG. 1, and the hatched portion is the aluminum wiring portion.

In the figure, 3□ is an input/output line, 3□ is an input/output line that has a complementary relationship with this input/output line, and these input/output lines 31 and 3□ are formed of impurity diffusion layers.

The dotted line portion 7 is the IG-FET of the memory cell 4, 8 and 9 are the power supply voltage vDD"SS supply lines, and 10 is the contact portion of the wiring.

FIG. 3 shows a circuit diagram corresponding to FIG. 2 above.

That is, in the above memory circuit, row decoder output lines 2 and input/output lines 3 intersect with each other in a matrix shape, and specifically, power supply lines 8 and 9 are further added.

When patterning this circuit with an aluminum gate structure, the method used in conventional complementary memory circuits is that the row decoder output lines that enter the memory cells of each row as gate inputs are made of aluminum, as shown in FIG. Also, the input/output lines perpendicular to these are wired in a diffusion (P+ or N+) layer.
Such a pattern layout has the advantage of reducing the number of contact holes and increasing the degree of integration.

However, from the standpoint of speeding up the operation, there are many problems, as the input/output line where the memory cell serves as a driver has a large amount of resistance and capacitance, and Ct in equation (1) becomes a dog, making it difficult to increase the speed of the circuit. had a limit.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory circuit that can be expected to operate at high speed while maintaining the same degree of integration as that of a conventional pattern arrangement.

An embodiment of the present invention will be described below with reference to FIG.

The features of this circuit are that the input/output lines (data bus) are wired entirely with aluminum, and the row (address) decoder output lines are formed with an impurity diffusion layer.

FIG. 4 is a pattern plan view of a memory cell portion of this circuit formed on a semiconductor substrate, and corresponds to the portion shown in FIG. 2.

Therefore, if FIG. 4 is converted into a circuit diagram, it will be equivalent to FIG. 3.

Also, as in the case of FIG. 2, the hatched portion indicates aluminum wiring.

In FIG. 4, 21 is an address decoder output line formed by diffusion, 221 is an input/output line, and 222 is an input/output line having a complementary relationship with this input/output line.

A portion 23 surrounded by a dotted line is a P-channel or N-channel IG-FET constituting a complementary circuit;

What can be seen from Figure 4 above is as follows.3 That is, in the conventional example shown in Figure 2, the input/output lines are diffused and the decoder output lines are made of aluminum. Resistance and capacitance increase.

Therefore, the memory cells act as drivers to read data to the input/output lines, and in order to increase speed, for example, in an IK-bit RAM (random access memory), the area of 1024 memory cells must be increased. Must be.

On the other hand, in the case of FIG. 4, the row decoder output line, which can be relatively large as a driver, is the driver of the diffusion line.

That is, since the operating speed in this case depends on the row decoder, it is only necessary to increase the size of 32 FETs corresponding to the 32 row decoder output lines of the decoder.

In this way, the pattern area of this circuit is smaller than that of the conventional example described above.In other words, if this circuit and the conventional example are made to have the same pattern area, the Ct of the above equation (1) can be made smaller in this circuit. , which enables high-speed operation.

Note that in the above embodiment, the power supply lines 24 and 25 are completely wired with aluminum to ensure the supply of sufficient current;
If only a small amount of current is required due to the low power consumption, which is an advantage of complementary circuits, it is easy to change the pattern design, for example, by omitting aluminum in the power supply line and taking the potential from the diffusion or semiconductor substrate. In this case, the degree of integration is further improved.

Further, the present invention is not limited to the above-described embodiment, and various modifications can be made, such as using seven IG-FETs and using the input/output line 221 as an input-only line as shown in FIG.

As explained above, according to the present invention, the address decoder output line is made of aluminum and the data bus is formed by diffusion.
A semiconductor memory circuit with a small pattern area and capable of high-speed operation can be provided.

[Brief explanation of drawings]

Fig. 1 is an overall configuration diagram of a memory circuit, Fig. 2 is a pattern layout diagram of a conventional memory cell section, Fig. 3 is a circuit diagram of the same, and Fig. 4
The figure is a pattern layout diagram of a memory cell portion according to an embodiment of the present invention, and FIG. 5 is a pattern layout diagram of a modification thereof. 21...Address decoder output line, 22□, 222.
...Data bus, 23.IC, -FET.

Claims (1)

[Claims] 1. In a semiconductor memory circuit in which memory cells are formed of P- and N-channel type IG-FETs, an address decoder selects an output line of the decoder, and data is read out to a data bus intersecting the output line, the address decoder output line is 1. A semiconductor memory circuit characterized in that the data bus is formed of an impurity diffusion layer and the data bus is formed of aluminum wiring.