JPS5820186B2 - solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device that prevents blooming.

FIG. 1 is a diagram showing the principle of a conventional MO8 type solid-state imaging device.

A photosensitive section 9 consisting of photodiodes 1 arranged in a matrix, and MO8 type FETs 91 to 9n for vertical readout switches for reading out optical signals accumulated in the photodiodes.
and MO8 type FET81~8m for horizontal readout switch
, a vertical shift register 3 and a horizontal shift register 2 for switching the respective switches in an orderly manner, and an output signal line 4.

The MO8 type FET for the vertical and horizontal changeover switches controls the gate voltage of the MO8 type F''ET by output pulses obtained from the outputs of each stage of the shift register to obtain switch operation.

However, in this solid-state imaging device, when the amount of incident light exceeds a certain level, a phenomenon called pluming occurs in which white vertical stripes appear on the screen, significantly degrading the image quality.

This is thought to be due to the reasons described below.

That is, as shown in FIGS. 2 and 3, the photodiode 1, which is illuminated by intense light, is forward biased by the large amount of charge 12 stored therein.

Thereafter, charges generated by the photocurrent overflow to the horizontal output line 10 through the parasitic transistor 111 configured under the vertical readout switch MO8 type FET 9i.

Charges 13 overflowing to the horizontal output line 10 during one horizontal period are read out simultaneously when charges of other photodiodes connected to the same horizontal output line 10 are read out, causing blooming.

Therefore, as shown in FIG. 4, plumping can be prevented by extracting the excess charge generated in the photodiode through an element 15i whose wall height is lower than that of the vertical readout switch MO8 type FET 9i. .

This is the M for extracting excess charge connected to the photodiode.
This is achieved by providing an OS type FET 15 i, a gate voltage control line for applying voltage to the gate of this MO8 type FET 15 i to adjust the wall height, and an excess charge extraction line for extracting excess charge. be able to.

However, since the area of a solid-state imaging device is constant, the additional provision of such elements and lines reduces the area of the photodiode and reduces sensitivity.

In particular, the area occupied by the gate voltage control line and the excess charge extraction line is large, which significantly deteriorates the sensitivity.

An object of the present invention is to provide a solid-state imaging device having a structure that can extract excess charge that causes blooming without newly providing such a gate voltage control line and an excess charge extraction line.

FIG. 5 shows the principle of the present invention and an embodiment thereof.

Excess charge is taken out by MOS type F for taking out excess charge.
Performed by ET 15 i.

However, the gate voltage of this MO8 type FET 15i is controlled by the DC video voltage applied to the horizontal output line 10, and excess charge is taken out through a line connected to the gate of the vertical switch MO8 type FET.

Also, here the vertical shift register is a vertical switch MO.
When turning off type 8 FET, use M for vertical switch.
The circuit configuration is such that the line connected to the gate of the O8 type FET is connected to the external power supply or ground at low impedance.

An example of such a circuit configuration is shown in FIG.

Hereinafter, the principle operation of the present invention will be explained using FIG. 6.

FIG. 6 shows the vertical structure of the sensor section (p-channel type) of the solid-state imaging device shown in FIG. 5 and the voltage relationship of each section.

The height of the wall in the part i of MO8 type FET 9 for vertical switch is the voltage of gate 20 and MO8 type FET for vertical switch.
It is determined by the lower voltage between the difference in the threshold value vT of ET and 10.7 V, which is the voltage at which the photodiode becomes forward biased.

Figure 6 is shown assuming that 10.7 V is lower.

On the other hand, the height of the wall at the MOS type FET 15i for extracting excess charge is the voltage difference between the video voltage and the threshold value vT applied to the MOS type FET 15i for extracting excess charge connected to the horizontal output line. It's decided.

This value is used to set the video voltage and the threshold value VT (the technique for setting the threshold voltage VT is generally well known today, so it will not be described in detail.

) can be freely selected, so as shown in FIG. 6, for example, by making the video voltage and the threshold value vT almost the same, the relationship shown in FIG. 4 can be realized.

On the other hand, the excess charge that has passed through the excess charge extraction MOS type FET is extracted through a line 20' connected to the gate of the vertical switch MO8 type FET.

This excess charge has no adverse effect on the vertical shift register described above.

Based on the above principle, MOS type FET for extracting excess charge
Excess charges that cause pluming can be extracted without providing a gate voltage control line and an excess charge extraction line.

[Brief explanation of the drawing]

Figures 1 to 3 are diagrams explaining conventional problems, and Figures 4 to 3
FIG. 7 is a diagram showing an embodiment of the present invention.

Claims (1)

[Claims] 1 A plurality of light receiving elements arranged in the horizontal (row) direction and vertical (column) direction, vertical readout switches corresponding to the light receiving elements, and output ends of the vertical readout switches located on the same column. A first line that is commonly connected, a horizontal readout switch that is connected to the -th line, an output line that commonly connects the output ends of the horizontal readout switches, and a control end of the vertical readout switch that is on the same row. a second line that is commonly connected; a horizontal scanning circuit that applies a horizontal scanning pulse to the control end of the horizontal readout switch; and a vertical scanning circuit that applies a vertical scanning pulse to the control end of the vertical readout switch via the second line. In the solid-state imaging device having a circuit, a switch for extracting excess charge is attached to each of the light receiving elements, the output end of the switch is connected to the second line in the subsequent stage, and the control end is connected to the first line in the previous stage. Connected solid-state imaging device.