JPS5821431B2 - Hand tie souchi - Google Patents
Hand tie souchiInfo
- Publication number
- JPS5821431B2 JPS5821431B2 JP4622174A JP4622174A JPS5821431B2 JP S5821431 B2 JPS5821431 B2 JP S5821431B2 JP 4622174 A JP4622174 A JP 4622174A JP 4622174 A JP4622174 A JP 4622174A JP S5821431 B2 JPS5821431 B2 JP S5821431B2
- Authority
- JP
- Japan
- Prior art keywords
- plate
- heat dissipation
- semiconductor element
- stud
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特に放熱性が改善された半
導体装置を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly provides a semiconductor device with improved heat dissipation.
半導体装置例えばトランジスタ、ダイオード、半導体集
積回路装置等は近時ますますその大電力化、高集積化が
望まれている。2. Description of the Related Art Recently, semiconductor devices such as transistors, diodes, semiconductor integrated circuit devices, etc. are desired to have higher power consumption and higher integration.
この大電力化、高集積化を達成するだめの必要条件の一
つに放熱性の向上がある。One of the requirements for achieving higher power consumption and higher integration is improved heat dissipation.
放熱の良否によって半導体装置の出力等が制限される。The output of a semiconductor device is limited depending on the quality of heat dissipation.
従来、半導体装置例えば大型半導体集積回路装置に用い
られている容器の構造を第１図に示す。FIG. 1 shows the structure of a container conventionally used for semiconductor devices, such as large-sized semiconductor integrated circuit devices.
同図において、１１はセラミック基板、１２は半導体素
子、１３はメタライズ配線層、１４は外部接続端子、１
５はセラミック枠、１６は蓋、１７は放熱用スタッド、
１８は放熱用フィンである。In the figure, 11 is a ceramic substrate, 12 is a semiconductor element, 13 is a metallized wiring layer, 14 is an external connection terminal, 1
5 is a ceramic frame, 16 is a lid, 17 is a heat dissipation stud,
18 is a heat radiation fin.
このような構造によれば、半導体素子１２はセラミック
基板１１の一主面の中央部の凹部へ収容され鑞材によっ
て固着される。According to such a structure, the semiconductor element 12 is accommodated in the recessed portion at the center of one main surface of the ceramic substrate 11 and fixed with a solder material.
又該半導体素子１２の電極からはリード線が導出され、
メタライズ配線層１３へ接続されて、これに連続する外
部接続端子１４へ接続される。Further, a lead wire is led out from the electrode of the semiconductor element 12,
It is connected to the metallized wiring layer 13 and connected to an external connection terminal 14 continuous thereto.
又蓋１６がセラミック枠１５へ固着されて、半導体素子
１２は気密封止される。Further, the lid 16 is fixed to the ceramic frame 15, and the semiconductor element 12 is hermetically sealed.
又、放熱用スタッド１７はセラミック基板１１の他主面
に設けられたメタライズ層へ固着され、該放熱用スタッ
ド１７へ放熱フィン１８が差し込まれ固定される。Further, the heat radiation stud 17 is fixed to a metallized layer provided on the other main surface of the ceramic substrate 11, and the heat radiation fin 18 is inserted and fixed into the heat radiation stud 17.
このような構造を有した容器へ半導体素子が収容されて
なる半導体装置においては、その動作状態における半導
体素子１２からの発熱はセラミック基板１１を介して放
熱用スタッド１７、放熱用フィン１８へ導かれる。In a semiconductor device in which a semiconductor element is housed in a container having such a structure, heat generated from the semiconductor element 12 in its operating state is guided to the heat radiation stud 17 and the heat radiation fin 18 via the ceramic substrate 11. .
この時、半導体素子１２とセラミック基板１１、あるい
はセラミック基板１１と放熱用スタッド１７との間の熱
膨張係数の差によって、半導体素子１２あるいはセラミ
ック基板１１にクラックを生ずる。At this time, cracks occur in the semiconductor element 12 or the ceramic substrate 11 due to the difference in thermal expansion coefficient between the semiconductor element 12 and the ceramic substrate 11, or between the ceramic substrate 11 and the heat dissipation stud 17.
又、放熱用フィン１８を放熱用スタッド１７へ差し込む
だけで確実に固定しようとする場合に、放熱用フィン１
８の内径と放熱用スタッド１Ｔの外径とを１ ／１００
Ｃｍｒｒｔ〕程の高い寸法精度をもって形成しなくて
はならない。Moreover, when trying to securely fix the heat dissipation fin 18 by simply inserting it into the heat dissipation stud 17, the heat dissipation fin 1
The inner diameter of 8 and the outer diameter of heat dissipation stud 1T are 1/100.
Cmrrt] must be formed with high dimensional accuracy.
又、このような高い寸法精度を有する部品間において差
し込み（圧入）が行なわれるだめに、この時セラミック
基板１１及び外部接続端子１４へ圧力が及ぼされ、これ
らの破壊、変形等を生ずる恐れがある。Moreover, since insertion (press-fitting) is performed between components having such high dimensional accuracy, pressure is applied to the ceramic substrate 11 and the external connection terminals 14 at this time, and there is a risk that they may be destroyed or deformed. .
本発明は、このような従来の半導体装置の有する欠点が
除去された半導体装置を得ることを目的とする。An object of the present invention is to obtain a semiconductor device in which such drawbacks of conventional semiconductor devices are eliminated.
本発明は、半導体素子からの発熱を、良好に放散するこ
とができる容器を得ることを目的とする本発明は、組立
時あるいは動作時にその構成要素に対して、熱的、機械
的な衝撃を与えることのない容器を得ることを目的とす
る。The object of the present invention is to obtain a container that can effectively dissipate heat generated from a semiconductor element.The present invention aims to provide a container that can effectively dissipate heat generated from a semiconductor element. The purpose is to obtain a container without giving.
もって本発明は、より信頼性が高く且つ大電力高集積半
導体素子を収容し得る半導体装置を得ることを目的とす
る。Accordingly, an object of the present invention is to obtain a semiconductor device that has higher reliability and can accommodate high-power, highly integrated semiconductor elements.
このため本発明によれば、貫通孔が設けられたセラミッ
ク基板の一面に前記貫通孔を覆ってベリリア板が固着さ
れ、前記ベリリア板の前記セラミック板側の面に無酸素
銅板及びモリブデン板を介して半導体素子が固着され、
前記ベリリア板の他面に無酸素銅板を介して放熱用スタ
ッドが固着されてなる半導体装置が提供される。Therefore, according to the present invention, a beryllia plate is fixed to one surface of a ceramic substrate provided with a through hole, covering the through hole, and an oxygen-free copper plate and a molybdenum plate are attached to the surface of the beryllia plate on the ceramic plate side. the semiconductor element is fixed,
A semiconductor device is provided in which a heat dissipation stud is fixed to the other surface of the beryllia plate via an oxygen-free copper plate.
次に本発明を図面をもって詳細に説明しよう。Next, the present invention will be explained in detail with reference to the drawings.
第２図は本発明による半導体装置である。FIG. 2 shows a semiconductor device according to the present invention.
同図において２１はセラミック基板、２２は半導体素子
、２３はメタライズ配線層、２４は外部接続端子、２５
はセラミック枠、２６は蓋、２７は放熱用スタッド、２
８は放熱用フィン、２９は両面モリブデンメタライズさ
れだべりリア（酸化ベリリウム：Ｂｅｏ）板、３０はモ
リブデン板、３１．３１’は無酸素銅板である。In the figure, 21 is a ceramic substrate, 22 is a semiconductor element, 23 is a metallized wiring layer, 24 is an external connection terminal, 25
is a ceramic frame, 26 is a lid, 27 is a heat dissipation stud, 2
8 is a heat radiation fin, 29 is a beryllium oxide (Beo) plate with molybdenum metallization on both sides, 30 is a molybdenum plate, and 31.31' is an oxygen-free copper plate.
このような構造によれば、半導体素子２２はセラミック
基板２１の中央部に設けられた貫通孔において、該セラ
ミック板２１の一方の主面に固着されたベリリア板２９
に、モリブデン板３０及び無酸銅板３１を介して固着さ
れる。According to this structure, the semiconductor element 22 is connected to the beryllia plate 29 fixed to one main surface of the ceramic substrate 21 in the through hole provided in the center of the ceramic substrate 21.
It is fixed through a molybdenum plate 30 and an acid-free copper plate 31.
又、半導体素子２２の電極からは、例えばアルミニウム
からなるリード線が導出され、例えばタングステン表面
に金メッキされたメタライズ配線層２３へ接続されてこ
れに連続する例えばコバールよシなる外部接続端子２４
へ接続される。Further, a lead wire made of, for example, aluminum is led out from the electrode of the semiconductor element 22, and connected to a metallized wiring layer 23 whose surface is plated with gold on the surface of, for example, tungsten, and connected to an external connection terminal 24 made of, for example, Kovar.
connected to.
又、例えばコバールからなる蓋２６が表面にメタライズ
されたセラミック枠へ固着されて半導体素子２２は気密
封止される。Further, a lid 26 made of Kovar, for example, is fixed to a ceramic frame whose surface is metallized, so that the semiconductor element 22 is hermetically sealed.
更に前記べＩＪ ＩＪア板２９の他面には無酸素銅板３
１′を介して放熱用スタッド２７が固着される。Furthermore, an oxygen-free copper plate 3 is provided on the other surface of the above-mentioned IJ IJ a board 29.
A heat dissipation stud 27 is fixed via 1'.
該放熱用スタッド２７には予め雄ねじが切られており、
該雄ねじと同ピツチの雌ねじを有する放熱用フィン２８
が、同放熱用スタッド２７へねじ込まれて取り付けられ
る。The heat dissipation stud 27 has a male thread cut in advance,
A heat dissipation fin 28 having a female thread of the same pitch as the male thread.
is screwed into the heat dissipation stud 27 and attached.
このような構造を有した半導体装置においては、その動
作状態においても半導体素子２２からの発熱はモリブデ
ン板３〇−無酸素銅板３１−ペリ；リア板２９−無酸素
銅板３１′−放熱用スタッド２７−放熱用フィン２８に
よって速やかに放散される。In a semiconductor device having such a structure, even in its operating state, heat generated from the semiconductor element 22 is dissipated from the molybdenum plate 30 to the oxygen-free copper plate 31 to the rear plate 29 to the oxygen-free copper plate 31' to the heat dissipation stud 27. - Rapidly dissipated by the heat dissipation fins 28.
この時、半導体素子２２とモリブデン板３０とはその熱
膨張係数がほぼ同じであるため、半導体素子２２にクラ
ックを生じない。At this time, since the semiconductor element 22 and the molybdenum plate 30 have substantially the same coefficient of thermal expansion, no cracks occur in the semiconductor element 22.
又、ベリリア板２９は、セラミック板に比べ熱伝導性が
良く半導体素子２２からの発熱を良好に放熱用スタッド
２７方向へ伝える。Furthermore, the beryllia plate 29 has better thermal conductivity than a ceramic plate and can efficiently transmit heat generated from the semiconductor element 22 toward the heat dissipation stud 27.
且つ半導体素子２２と放熱用フィン２８との間を電気的
に絶縁する。Moreover, the semiconductor element 22 and the heat radiation fins 28 are electrically insulated.
又無酸素銅板３１．３１’は、モリブデン板３０とベリ
リア板２９との間及びベリリア板２９と放熱用スタッド
２７との間に介在され、これらの構成要素間における熱
膨張係数の差により生ずる歪を吸収し、ベリリア板２９
にクラックが生ずるのを防止する。Further, the oxygen-free copper plates 31 and 31' are interposed between the molybdenum plate 30 and the beryllia plate 29 and between the beryllia plate 29 and the heat dissipation stud 27, and are designed to absorb strain caused by the difference in coefficient of thermal expansion between these components. absorbs, beryllia plate 29
Prevent cracks from forming.
又、放熱用スタッド２７は例えばモリブデンからなり熱
伝導性を良好とされ、放熱用フィン２８は例えばアルミ
ニウムからなり、加工性、放熱性等を良好なものとする
。Further, the heat radiation stud 27 is made of, for example, molybdenum and has good thermal conductivity, and the heat radiation fin 28 is made of, for example, aluminum and has good workability, heat radiation, etc.
又該放熱用スタッド２７と放熱用フィン２８とは通常の
ねじによる保合がなされるため、ここにおいては前記従
来の構造のような高い加工寸法精度を要求されない。Further, since the heat radiation stud 27 and the heat radiation fin 28 are secured together by ordinary screws, high machining dimensional accuracy is not required here as in the conventional structure.
しかもねじによる係合であるためその取り付け、取りは
ずしが極めて容易であり、この作業中にセラミック基板
２１及び外部接続端子２４に圧力が加わらず、これらの
破壊、変形を生ずる恐れがない。Moreover, since the screws are used for engagement, attachment and detachment are extremely easy, and no pressure is applied to the ceramic substrate 21 and the external connection terminals 24 during this operation, so there is no risk of their destruction or deformation.
更に放熱用スタッド２７に比べて放熱用フィン２８を充
分大きなものとすることができ放熱性をよシ向上させる
ことができる。Furthermore, the heat dissipation fins 28 can be made sufficiently larger than the heat dissipation studs 27, and the heat dissipation performance can be further improved.
このような本発明によれば、放熱性が良好であって、組
立て時、動作時においても各構成要素に対して熱的、機
械的な衝撃を与えることをく、もって信頼性が高く且つ
大電力、高集積半導体装置を収容し得る半導体装置を得
ることができる。According to the present invention, heat dissipation is good, and thermal and mechanical shocks are not applied to each component during assembly and operation, making it highly reliable and large-scale. A semiconductor device capable of accommodating power and highly integrated semiconductor devices can be obtained.
尚、以上の説明において、半導体素子として大型半導体
集積回路素子を掲げたが、本発明はこれに限られず、ト
ランジスタ、ダイオード等にも適用することができるも
のである。In the above description, a large-sized semiconductor integrated circuit element was used as the semiconductor element, but the present invention is not limited thereto, and can also be applied to transistors, diodes, and the like.
第１図は従来の半導体装置の構造を示す斜視図第２図は
本発明による半導体装置の構造を示す斜視図である。
第１図及び第２図において、１１．２１はセラミック基
板、１２，２２は半導体素子、１３゜２３はメタライズ
配線層、１４．２４は外部接続端子、１５ 、２５はセ
ラミック枠、１６．２６は蓋、１７，２７は放熱用スタ
ッド、１８．２８は放熱用フィン、２９はベリリア板、
３０はモリブデン３Ｌ３１’は無酸素銅板である。FIG. 1 is a perspective view showing the structure of a conventional semiconductor device. FIG. 2 is a perspective view showing the structure of a semiconductor device according to the present invention. 1 and 2, 11.21 is a ceramic substrate, 12 and 22 are semiconductor elements, 13.23 is a metallized wiring layer, 14.24 is an external connection terminal, 15 and 25 are ceramic frames, and 16.26 is a Lid, 17 and 27 are heat dissipation studs, 18 and 28 are heat dissipation fins, 29 is beryllia plate,
30 is molybdenum 3L31' is an oxygen-free copper plate.
Claims (1)
通孔を覆ってぺ、リリア板が固着され、前記ベリリア板
の前記セラミック板側の面に無酸素銅板及びモリブデン
板を介して半導体素子が固着され、前記ベリリア板の他
面に無酸素銅板を介して放熱用スタッドが固着されてな
ることを特徴とする半導体装置。1. A Lilia plate is fixed to one surface of a ceramic substrate provided with a through hole, covering the through hole, and a semiconductor element is fixed to the surface of the Berylia plate on the ceramic plate side via an oxygen-free copper plate and a molybdenum plate. and a heat dissipation stud is fixed to the other surface of the beryllia plate via an oxygen-free copper plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4622174A JPS5821431B2 (en) | 1974-04-24 | 1974-04-24 | Hand tie souchi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4622174A JPS5821431B2 (en) | 1974-04-24 | 1974-04-24 | Hand tie souchi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS50139674A JPS50139674A (en) | 1975-11-08 |
| JPS5821431B2 true JPS5821431B2 (en) | 1983-04-30 |
Family
ID=12741041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4622174A Expired JPS5821431B2 (en) | 1974-04-24 | 1974-04-24 | Hand tie souchi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821431B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5329276U (en) * | 1976-08-20 | 1978-03-13 | ||
| JPS5374365A (en) * | 1976-12-15 | 1978-07-01 | Toshiba Corp | Semiconductor ceramic package |
| DE2857170A1 (en) * | 1977-11-18 | 1980-12-04 | Fujitsu Ltd | SEMICONDUCTOR DEVICE |
| JPH0793394B2 (en) * | 1985-10-25 | 1995-10-09 | 株式会社日立製作所 | Ceramic package for mounting semiconductor substrate |
| JPS63164236U (en) * | 1987-04-15 | 1988-10-26 |
-
1974
- 1974-04-24 JP JP4622174A patent/JPS5821431B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS50139674A (en) | 1975-11-08 |
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