JPS5822833B2 - Memory addressing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an addressing method that automatically determines the address of each memory plane in an interleaved memory in which a plurality of memories operate simultaneously.

FIG. 1 explains interleaving applied to high-speed memory processing.

Interleaving is a method for high-speed memory processing, in which address buses and data buses are used in time-sharing between interleaved memories.

For example, when there are two interleaved memories, if one memory occupies the address bus, the other memory occupies the data bus.

In one memory, the address bus and the data bus are occupied in a time-sharing manner.

2゜ 2A and 2B are memory planes, 3 is an address bus, 4 is a data bus, 5 is a control line that specifies reading and writing, and 6 is a timing line, which constitutes a memory interface that connects the memory planes. .

The memory interface line can operate two or more memories at the same time by performing time-division transfer.

The numbers in each memory plane indicate the address,
Memory plane 2 and two people are interleaved,
2B is not interleaved due to the last odd memory plane.

Therefore, memory plane 2 has even addresses up to word 128, memory plane 2A has odd addresses up to word 128, and memory plane 2B has even addresses from word 128 to 19.
2, all consecutive addresses up to the word are stored.

The troublesome thing with this method is how to assign addresses.

The simplest possible method is shown in FIG.

The upper few bits and lower 1 bit are extracted from the address bus 3, and these are compared with the contents of the switch register 1 by the comparator 8.
When the comparison is made and a match is found, the memory plane is selected.

At this time, the coincidence signal 11 is transmitted to the memory array 9, and the memory operation is started.

The memory array address lines are fed by the remaining portion 10 of the address bus used for memory plane selection.

The problem with this method is that setting the switch 7 is time consuming.

Errors in switch settings may cause malfunctions such as double selection.

When interleaving is included, the switch settings are especially complicated, and setting errors are likely to occur.

Furthermore, although the above case is a case where all memory planes have the same capacity, there is also an interleaving case where memory planes with different capacities are provided.

FIG. 3 shows a configuration diagram at this time.

In FIG. 3, word memory planes 2A, 2B, 2 are shown at 64.
An example is shown in which a memory is configured with memory planes 2D and 2E of words C and 32.

As is clear from the figure, memory planes 2A and 2B and memory planes 2D and 2E are interleaved with each other.

The reason why the memory plane 2C is not interleaved is that the remaining planes are an odd number.

When such memory planes with different capacities exist, the switch settings become more complicated than in the case described in FIG. 1.

An object of the present invention is to provide a memory addressing system that automatically allocates addresses when a memory plane is inserted.

The gist of the present invention is to detect how many memories of the same capacity are installed and automatically determine the interleave mode based on this.

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 4 is a diagram showing an embodiment of the present invention.

The same symbols as in FIGS. 1 and 2 indicate the same contents, and the contents of the memory planes and the interfaces between the memory planes are different from the configuration in FIG. 2.

Since it is necessary to detail the interface between memory planes, two memory planes 200 and 201 as shown in the figure are assumed.

In each memory plane 200 and 201, instead of the switch register 7 and the comparator 80, an interleave control circuit 8A is used.
.

8B is provided.

These interleave control circuits 8A and 8B each have a line 1 for transmitting a plane address PLANEADDR.
2A, 12B.

12C1 Lines 13A, 13B, 13C for transmitting type count TYPE COUNT; Lines 14A, 14B for transmitting type TYPE.

14C, and has lines 15A, 15B, and 15C for transmitting interleaved mode IMODE.

For convenience in such a configuration, the one with the larger address will be referred to as the upper memory plane, and the one with the smaller address will be referred to as the lower memory plane.

In the figure, memory plane 201 is the upper level, memory plane 2
00 is defined as lower.

PLANE ADDR transferred by plane address lines 12A, 12B, and 12C is data for determining the address of each memory plane, and is transferred from lower to upper.

Each time this PLANE ADDR passes through each memory plane, that is, each time it enters and exits the interleave control circuit, it is added by the capacity of that memory plane and sent to the upper memory plane.

For example, if the memory has a total memory capacity of up to 1M words and the capacity of the smallest memory plane is 32 words, then P
LANE ADDR has a 5-bit configuration (5 lines for parallel transmission), and in the memory plane of 32 words,
+1", 64 word memory crane "+2", 12
In the memory plane of the word 8, it will be increased by "+4".

TYPE transferred by the type lines 14A, 14B, and 14C is data indicating the capacity of the memory plane, and is transferred from the upper to the lower.

Different codes are assigned to this data TYPE according to the capacity of the memory plane, and according to the specific memory capacity example above, the data TYPE is 2 bits (
In the case of parallel transmission, there will be two lines), and in the memory plane with word 32, it will be 00”, and in the memory plane with word word 64, it will be “00”.
In the memory plane of words 01" and 128, the side spirals will be 10" and so on.

TYPE COUNT transferred by type count lines 13A, 13B, and 13C is data indicating how many memory planes of the same capacity are consecutively mounted, and is transferred from lower to upper.

For example, when performing interleaving up to a maximum of 4 ways, TYPE COUNT is 2 bits (
For parallel transmission, there will be two lines).

At this time, the TYP sent from the upper memory plane
If E and your TYPE are the same, count up by ``+1'' and transmit it to the upper level, and if they are different, reset it to 0'' and transmit it.

Interleave mode lines 15A, 15B.

IMODE transferred in 15C is a signal for determining the interleave mode, and is transferred from higher to lower.

For example, if 4 memory planes of the same capacity are installed based on the value of TYPE C0UNT, 4-way (4
When there are two sheets, a 2-way signal is output.

The processing of each of the above signals is performed on each memory plane 200°201.
Interleave control circuits 8 A and 8 B in the memory array 9 each send a match signal 11 and an internal address 10 indicating that the memory plane has been selected to the memory array 9 .

Next, FIG. 5 shows the interleave control circuit 8A (or 8B).
An example will be shown in which a similar configuration is also used for .

This interleave control circuit includes an inflator 16,
It consists of a switch 17, a comparator 18, a selector 19, an inflator 21, an IMODE determination circuit 22, a comparator 23, and a multiplexer 28.

In the figure, the left side shows the interface with the lower memory plane, and the right side shows the interface with the higher memory plane.

First, the inflator 16 adds the PLANE ADDR(IN) sent from the lower level via the line 12A by the capacity of the memory plane, and sends the PLANE ADDR(O) to the upper memory plane via the line 12B.
UT) is output.

The upper TYPE (IN) sent via line 14B
) is sent to the comparator 18.

This comparator 18 has the TYPE of its own memory plane.
A self-TYPE signal is sent from the switch 17 indicating the capacity (since this indicates the capacitance, it may be in the printed board mode).

The comparator 18 compares the two, and when they match, a match signal 20 is sent to the selector 19.

Lower TYPECOU sent via line 13A
NT is incremented by "+1" through the inflator 21 and sent to the selector 19.

The selector 19 selects the signal of the inflator 21 when the match signal is true, and selects the value of zero (GD) when the match signal is false, and sends them to the upper layer via the line 13B.

The upper level data sent via line 15B IMODE is input to the IMODE determination circuit 22.

This determining circuit 22 determines IMODE from the match signal 20 and the TYPE COUNT (IN) sent via the line 13A.

This determining circuit 22 not only transmits IMODE to the lower level through the line 15A, but also determines the interleave mode of the plane.

At this time, IMODE (OUT) is determined according to the table shown in FIG.

The table shown in Figure 6 is for the case where the maximum number of interleaves is 4, and in the output of IMODE (OUT), IM
When ODE(OUT)AIJ''=''1'', 2-way (
Way) increment, IMODE (OUT) B also “1”
'' means 4-way.

Furthermore, in the above table, "passing" means sending IMODE from the upper plane to the lower plane as it is.

Such IMODE(OUT) is also output to the multiplexer 28.

In the multiplexer 28, this IMODE (OUT)
In response to this, the address bus 3 is divided into two outputs.

The first is bank address BANKADDR29 to indicate whether or not the plane has been selected, and the second is address 10 within the memory plane.

BANK ADDR29 is set to PLANE A by comparator 23.
When compared with DDR(IN) and they match, a match signal 11 is generated.

FIG. 1 is a diagram showing an embodiment of multiplexer 28. As shown in FIG.

This multiplexer 28 has selectors 24°25.26,
It consists of 27 pieces.

If the address bits through the address bus 3 are 20, then the 20 address lines 3-0.3-1, . . .
..., 3-17.

3-18 and 3-19 constitute the address bus 3.

When performing up to 4-way interleaving, memory plane selection is performed using several address lines below lines 3-19, 3-18, and 3-17 when there is no interleaving, and 2-way When interleaving is performed, several address lines below lines 3-0, 3-18 and 3-17 are used, and when 4-way interleaving is performed, lines 3-0, 3-1 and 3-1 are used.
This is done using several address lines below 7.

15 which is the output IMODE (OUT) A of the decision circuit 22
-2A, 15-2B which is IMODE(OUT)B is
This serves as a selection signal for the selectors 24, 25, 26, and 27, and the address selection as described above is performed here.
Create R29 and internal address 10.

In other words, as shown in the table below, each selector is 24°25.26
, 27, 2-way (2-'My), 4-way (
4-way) or an address line corresponding to no increment is selected.

Note that a well-known method can be applied to interleaving timing control.

For example, to simplify the explanation, we will explain only the address bus, excluding the data bus relationship, which requires consideration of read and write modes. First, when an address is sent from the memory control circuit 1, it is sent via the timing line 6. A message indicating that Atlus has been sent is sent to each memory plane.

Each memory plane checks whether the address indicates itself using the increment control circuit shown in FIG. .

This causes the memory control circuit 1 to start processing the next memory request.

The memory plane where memory requests are incremented (
For example, when the memory planes 2A and 2B are sent to the memory planes 2A and 2B shown in FIG. 3, the memory planes 2A and 2B are operated at the timing shown in FIG. 8 a-e.

As shown in FIG. 8a, when a memory request for address λ\2'' is given via address bus 3, two memory loops start operating as shown in FIG. 8d.

If the next memory request is for address XX3'' corresponding to memory plane 2B, as shown in figure a, memory plane 2B starts operating as shown in figure e, without waiting for memory plane 2A to operate. , become incremented.

On the other hand, when a memory request is made to a memory plane that has not been incremented (for example, 2C shown in FIG. 3), the memory plane 2C relationship is operated at the timing shown in FIGS. 9a to 9d.

As shown in FIG. 9a, when a memory request for address "128K" is given via address bus 3,
The memory plane 2C starts operating as shown in FIG.

If the next memory request is +1" at the address XX128 corresponding to the same memory plane 2C, as shown in FIG. 2A, it will not be accepted until the busy state of the memory plane 2C is released.

As described in detail above, according to this embodiment, the number of memory planes of the same capacity that are consecutively mounted is calculated (by the functions of the comparator 18, the selector 19, and the inflator 21), and the result is The comparator 2 then compares the selected address bit with the memory plane address (by the action of the determining circuit 22 and the alternator 28) to determine which bit of the address line is to be selected.
3) determines the address during interleaving.

Incidentally, at first glance, the above embodiment gives the impression that the operation is complicated and the cost increases, but in FIG. 5, the parts that require high speed are the multiplexer 28 and the comparator 23.
Although this requires the use of general high-speed logic elements, there is no problem with other parts being slow.

Therefore, FPLA (FieldProgrammable
e Logic Array) can be used,
And it only takes one piece.

For this reason, cost increase is not a problem.

According to the present invention, it is now possible to automatically determine addresses during interleaving.

[Brief explanation of the drawing]

Figure 1 is a general memory configuration diagram, Figure 2 is a conventional circuit side diagram for address determination, Figure 3 is another memory configuration diagram,
FIG. 4 is an embodiment of the present invention, FIG. 5 is a partial embodiment thereof, FIG. 6 is an explanatory diagram of its operation, FIG. 7 is a further partial embodiment, and FIGS. 9A to 9D are diagrams illustrating an example of timing of memory operation. 200.201...Memory plane, 8A. 8B...Interleave control circuit, 9...
...Memory array.

Claims (1)

[Claims] 1 In a memory where multiple memory planes, including memory planes with different capacities, are connected by address buses, data buses, control lines, and timing lines, and some of the multiple memory planes are mutually incleaved. Then, calculate how many memory planes of the same capacity are consecutively mounted in each memory plane, determine the bit selection on the address bus based on the calculated value, and select the bits on the address bus based on this determination. A memory addressing method in which a selection bit of a plane is compared with a plane address of the plane, and an address is determined according to the comparison result.