JPS5828675B2 - Interleaved memory addressing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an addressing method that automatically determines the address of each memory plane in an interleaved memory in which a plurality of memories operate simultaneously.

FIG. 1 illustrates memory interleaving.

2.2' and 2'' are memory planes, 3 is an address bus, 4 is a data bus, 5 is a control line that specifies reading and writing, and 6 is a timing line, which constitutes a memory interface that connects the memory planes. ing.

The memory interface line can operate two or more memories at the same time by performing time-division transfer.

The numbers in each memory plane indicate the address,
Memory planes 2 and 2' are interleaved,
2" is not interleaved for the last odd memory plane.

Therefore, memory plane 2 has even addresses up to word 128, memory plane 2' has odd addresses up to word 128, and memory plane 2'' has even addresses up to word 128, up to word 19.
2, all consecutive addresses up to the word are stored.

The troublesome thing with this method is how to assign addresses.

The simplest possible method is shown in FIG.

The upper few bits and lower 1 bit are extracted from the address bus 5, and compared with the switch register 7 and the comparator 8. When a match is found, the memory plane is selected. .

At this time, the coincidence signal 11 is transmitted to the memory array 9, and the memory operation is started.

The memory array address lines are supplied with the remainder of the address bus used for memory plane selection.

The problem with this method is that setting up the switches is cumbersome.

Errors in switch settings may cause malfunctions such as double selection.

When interleaving is included, the switch settings are especially complicated, and setting errors are likely to occur.

The present invention was devised to eliminate the drawbacks of the method using switches as described above, and its purpose is to automatically allocate addresses once the required number of memory planes are inserted. It is possible to provide an interleaved memory addressing scheme.

The feature of the present invention is that for each memory plane,
An adder, a selection logic circuit, and a comparison circuit are provided, and the adder adds only the memory capacity of the memory plane to the input of the addressing line provided between each memory plane to specify the memory plane address. The selected value is sent to the next memory plane, and the selection logic circuit determines which line of the address bus to select based on an interleave mode designation signal indicating how many memories are implemented in the memory group to be interleaved. , the selected address line is sent to a comparator, and the comparator compares the content of this address line with the content of the address designation line, and when they match, the memory plane is designated.

According to the present invention, an interleave mode designation signal indicating how many memories are installed in a memory group to be interleaved is input to a selection logic circuit, and the selection logic circuit automatically A specific address line is selected from the address bus, thereby automatically assigning addresses.

FIG. 3 shows an embodiment of the present invention.

This example shows the case of 2-way interleaving, where 2 and 2' indicate memory planes to be interleaved.

12 is an address designation line for designating a memory plane address; 13 is a selection logic circuit that selects and outputs a specific line 18 from the address bus 3 in response to a signal from the interleave mode designation signal line 17; A comparator 15 compares the line 18 selected by the selection logic circuit 13 with the content of the addressing line 12 and outputs a match output signal 11 if they match. The added value is output to the next memory plane 2' via the addressing line 12'.

As an example, the maximum capacity IM word is 64. Assuming that there are k words, there are four addressing lines 12, and the content of the addressing line 12 is (oooo), which is incremented by 1 in the adder circuit 15, and the content of the addressing line 12' is (0001). becomes.

Memory plane 2 is connected to interleave mode designation signal line 1 if memory plane 2' is not implemented.
7 is connected to the power supply Vcc via a resistor 16, and has a logic level of 1'', and when mounted, it is grounded, so it is +01''.

On the other hand, memory plane 2' is connected to signal line 17 on the bank board.
Since ' is grounded, 0'' is entered.

In the case of '1'', it is a mode in which no interleaving is performed, and the selection logic circuit 13 selects only the upper few bits (I
In the example of a memory of M words, the upper 4 bits) are taken out and sent via line 18 to comparator 14.

On the other hand, in the case of II O11, the mode is ink-leave, and the selection logic circuit 13 extracts the upper several bits and the lower 1 bit (in the example of an IM word memory, the upper 3 bits and the lower 1 bit). , to comparator 14 via line 18.

Comparator 14 compares the signal sent from selection logic circuit 13 via line 18 with the signal on address designation line 12, and if they match, outputs match signal 11.
, indicates that the memory plane is selected.

FIG. 4 shows a specific example of the selection logic circuit 13, which includes two selectors 18 and 19 and an inverter 20.
It consists of

The selector 18 selects one of the +16 and #O lines of the address bus 3 according to the signal level of the signal line 17 inputted via the inverter 20, and outputs it to A16.

The selector 18 selects line #16 when the output of the inverter 20 is at the OP level, and selects the line #O when the signal is at the +11++ level.

The signal level of the signal line 17 is directly input to the selector 19, and when it is +l 1 j + level, select = # = O, and in the case of f + Q 1 level, select Φ16 and select AO.
It is designed to output to .

Therefore, when +16 is selected for A16 by the selector 18, 4I-0 is selected for AO, and conversely, A
If +O is selected for 16, +16 is selected for AO.

The 4 bits from A16 to A19 are sent to the comparator 14.
The 16 bits O to A15 indicate the address within the memory plane.

Now, when the signal line 17 is at the "1" level, this is a mode in which no interleaving is performed, but at this time, =#= 16
~The upper 4 bits of #19 go to the comparator 14, =#=O-#
15 is used to indicate the address within the memory plane, and conversely, if the signal line 17 is at the 0° level, it is interleave mode, =ll-0,
4 bits +17, +18, -IN, 9 are comparator 14
To, #16. Temple 1. The 16 bits from Φ2° to #15 indicate the address of the memory plane.

As described above, according to the embodiment of the present invention, the level of the signal line 1γ changes by inserting a memory plane, and the interleaved address is automatically determined, making it possible to perform optimal interleaving.

Although the case of 2-way interleaving has been described above, addresses can be automatically assigned using the same method in 4-way or 8-way.

Figure 5 shows an example in which up to 4 ways are possible, with interleave mode designation signal lines 17-1, 17-2 to 17 to
Addresses are assigned depending on the contents of 1'' and 17-2''.

For example, to explain memory plane 2, if only memory plane 2 exists, both signal lines 17-1 and 17-2 will be 1', no interleaving, and memory plane 2
' is inserted, only 17-1 becomes pa 0', 2-way interleave, and memory plane 2',
If 2"' is inserted, both 17-1 and 17-2 become 0", so that a 4-way ink-leave is performed.
A signal is given to the selection logic circuit 13.

In the case of 2-way, the selection logic circuit 13 selects Φ16 and +0 of the address bus 3, but in the case of 4-way, 4I=16. Φ17 and #O2O2O3 choices 2
This is done according to the bit mode designation signal.

In FIGS. 3 and 5, symbols with suffixes that are not explained are equivalent to symbols without suffixes.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining memory interleaving,
Fig. 2 is a diagram showing one of the conventional methods, Fig. 3 is a diagram showing an embodiment of the circuit of the present invention, Fig. 4 is a diagram showing a specific example of a part of Fig. 3, and Fig. 5 is a 4-way diagram. FIG. 3 is a diagram showing an example of how to create an ink-leave designation signal. 13... Selection logic circuit, 14... Comparator, 15... Adder.

Claims (1)

[Claims] 1. In a plurality of memory planes connected by address buses, data buses, control lines, and timing lines, such that the memories of at least two memory planes are interleaved, each memory plane has an adder and a selector. A logic circuit and a comparator are provided, and the adder adds the memory capacity of the memory plane to the input of the address designation line provided between each memory plane to designate the memory plane address, and calculates the value as follows. The selection logic circuit determines which line of the address bus to select according to an interleaf mode designation signal indicating how many memories are implemented in the memory group to be interleaved, and determines which line of the address bus is selected. The comparator compares the content of this address line with the content of the address designation line, outputs a match signal when they match, and specifies the memory plane. An interleaved memory addressing method characterized by: