JPS5822886B2 - buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a totem pole buffer circuit.

Conventional totem pole type E/E (Enhanceme
nt/Enhancement) mode buffer circuit is shown in FIG.

This circuit is an enhanced MO8I transistor 1, 2
are connected in series between power supply terminal 3 and ground, the output of point A, which is the input to input terminal 4 inverted by impark 5, is used as the gate input to transistor 1, and the output of point B, which is inverted by inverter 7, is The output is used as a gate input to the transistor 2, and an output is obtained from the output terminal 6.

In this circuit, as shown in the operating waveform of Fig. 4, the output voltage amplitude is VDD-vth, for example, the power supply voltage VDD = -5V.
, when the threshold voltage Vth=-1.5V, the output voltage amplitude can only be -3.5VL.

Furthermore, as shown in FIG. 2, an E/D (Enhancement/Deplet
ion) mode buffer circuit, the output voltage amplitude is VDl)--5V directly obtained at terminal 6, but the first
To obtain the same rise time (of output) as the circuit shown,
The transistors 1' and 2 must be made large, which increases the load current and increases power loss, which is undesirable.

Therefore, an object of the present invention is to create a buffer circuit that can suppress power loss to the same level as the circuit shown in FIG. Our goal is to provide the following.

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

As shown in Figure 3, the power terminal 3 side is a depression type MO.
These transistors are connected in series so that the S transistor 1 and the ground side become the enhancement type MOS transistor 2, and the input to the input terminal 4 is inverted by the inverter 5.
The output at point B' is used as the gate input to transistor 1', and the inverted output at point B' is used as the gate input to transistor 2, and an output is obtained from output terminal 6.

At first glance, this circuit looks similar to the circuit shown in FIG. 1, but its operation is fundamentally different because the transistor 1' serving as the load is of the depletion type.

That is, since it is in E/D mode, the output voltage amplitude can be obtained as the power supply voltage VDD (=-5V), but
Unlike the circuit shown in FIG. 1, a steady current ILO (for charging the load capacitance) flows as shown in FIG.

In the case of the circuit shown in Fig. 2, there is only ILO, but in this circuit, during a transient period, that is, when the waveforms at points A' and B' are transient, the rise of the waveform at point A' is generally higher than B. Since the rise is slightly faster than the rise of point ', depletion type transistor 1' is turned on to a greater extent, and before transistor 2 is turned off, a large current ILP for charging flows from transistor 1' to load capacitance cL, resulting in a faster response time. Become.

Furthermore, since the transistor 2 is driven by the inverter 7, the response time becomes faster even if the transistor 2 is large.

In addition, in the case of an N-channel MO8 integrated circuit, the logic is positive both inside and outside the integrated circuit, so it is desirable to match the logic between the inside and outside of the integrated circuit, but in this circuit, the input of impark 7 is 1.
'', the output terminal 6 obtains 1'', so the logic can be matched both inside and outside the integrated circuit.

In addition, the shape pattern of the load transistor 1' may be smaller than that of the E/E mode circuit shown in FIG. Although necessary, in the case of the present circuit shown in FIG. 3, the same rise speed can be obtained with the above-mentioned size ratio of about 1Δ:1, which is extremely advantageous in terms of pattern area.

In addition, in the case of the circuit shown in FIG. 2, in order to obtain the same response speed as the present circuit shown in FIG. 3, it is necessary to increase the size of both transistors 1' and 2, which is undesirable since the power loss is also increased.

As described above, according to the present invention, in a 1-tempole type buffer circuit, the gate input of the MO8+- transistor on the power supply side is set to be an input that is in reverse phase and slightly ahead of the gate input of the MOS transistor on the ground side, and Since the transistor on the power supply side is of the depletion type, it is possible to obtain a sufficient output voltage amplitude, the signal response time is fast, the power loss is small, and the logic inside and outside the integrated circuit can be matched. A buffer circuit with advantages can be provided.

[Brief explanation of drawings]

FIG. 1 is a buffer circuit diagram of a conventional 1-tempole type E/E mode, FIG. 2 is a buffer circuit diagram of the same E/D mode, and FIG. 3 is a circuit diagram of an embodiment of the present invention. FIG. 4 is a signal waveform diagram for explaining the operation of the above circuit. 1'...depression type MOS transistor, 2...enhancement type MOS transistor, 5
, 7... Inverter, CL... Load capacity.

Claims (1)

[Claims] 1. A totem pole type buffer circuit ζ using a depletion type MOS transistor on the power supply terminal side and an enhancement type MOS transistor on the ground side, and means for inputting an input signal to the gate input of the depletion type MO8) transistor; the depletion type M provided between the gate of the enhancement type MOS transistor;
O8) A means for supplying a signal having an inverse relationship with the gate input of the transistor, the depletion type MOS
The gate input of the transistor is connected to the enhanced MO8I.
- A buffer circuit characterized by having an input that is in opposite phase to the gate input of a transistor and slightly advanced.