JPH0720056B2 - Output circuit - Google Patents

Description

The present invention relates to an output circuit, and more particularly to an output circuit used as an output buffer circuit or the like of a semiconductor integrated circuit.

[Conventional technology]

An example of a conventional output circuit is shown in FIG. In the figure, an input terminal IN is connected to the gate of a CMOS inverter circuit composed of a P-channel transistor Ptr ₁ and an N-channel transistor Ntr ₂ , and its output is a P-channel transistor Pt.
It is connected to the gate of a CMOS inverter circuit composed of r ₃ and N-channel transistor Ntr ₄ , and its output is output terminal OU.
Connect to T. Further, in order to set the driving capability of the output buffer large, the channel widths of the P-channel transistor Ptr ₃ and the N-channel transistor Ntr ₄ are increased.

[Problems to be solved by the invention]

The above-mentioned conventional output circuit can realize high driving ability by increasing the channel width of the transistor according to the external load, but at the same time, a large noise occurs due to an increase in the transient current at the time of switching, and its own logic There is a drawback that the operation may become unstable and an external integrated circuit may malfunction.

An object of the present invention is to provide an output circuit capable of suppressing a transient current when an output state changes, reducing noise during switching, and realizing a high driving capability.

[Means for solving problems]

The output circuit of the present invention includes a first buffer that transmits a signal as it is without affecting the circuit conditions on the input side and the output side, a second buffer that can be controlled to a high impedance state, and a delay circuit. And an exclusive OR circuit,
The first buffer receives a signal from an input terminal and outputs a signal to an output terminal, and the second buffer receives a signal from the input terminal through the delay circuit and outputs a signal to the output terminal. However, the input signal and the output signal of the delay circuit are input to the exclusive OR circuit, and the output signal puts the second buffer into a high impedance state.

〔Example〕

 The present invention will now be described with reference to the drawings.

1 and 2 are a circuit diagram and a waveform diagram for explaining the operation of an output circuit according to an embodiment of the present invention, respectively. The operation of this output circuit will be described below with reference to FIG.

When the input terminal 1 changes from a low level (hereinafter abbreviated as L) to a high level (hereinafter abbreviated as H), the buffer 5 tries to change from L to H, so that the output current I from the node 2 via the output terminal 8 is output. ₅ starts charging the capacitor CL. While the signal is being transmitted through the delay circuit 7, the output of the exclusive OR circuit 4 becomes H, and the buffer 6 is in the high impedance state.
Become HZ. Therefore, the capacitor CL is charged only with the output current I ₅ . When a signal is transmitted to the node 3 in the figure, the output of the exclusive OR circuit 4 becomes L, and the buffer 6 becomes the node 3
Signal H is output to start charging by the output current I ₆ .
In this way, the charge to the capacitor CL is performed by first adding the output current I ₅ of the buffer ₅ and then the output current I ₆ of the buffer 6. Also, when the input terminal changes from H to L, the charge of the capacitor CL is discharged by the same movement as above. As a result, the output circuit of the present invention can realize high driving capability and reduce noise during switching.

Furthermore, a circuit diagram is shown in FIG. 3 as another embodiment of the present invention. This output circuit has three stages of switching of the transient current. By doing so, noise during switching can be further reduced. In the figure, 9 is a node, 10 is an exclusive OR circuit, 11 is a buffer, and 12 is a delay circuit.

〔The invention's effect〕

As described above, in the output circuit of the present invention, switching of the transient current is divided into two stages, and the rate of change of the current with respect to time is reduced to reduce noise during switching.
Moreover, there is an effect that the driving ability can be kept large.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of FIG. 1, FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. 4 is a conventional example. It is a circuit diagram. 1 ... input terminal, 4 ... exclusive OR circuit, 5 ... buffer, 6 ... buffer, 7 ... delay circuit, 8 ... output terminal.

Claims (1)

[Claims] 1. A first buffer which transmits a signal as it is without affecting circuit conditions on an input side and an output side, a second buffer which can be controlled to a high impedance state, and a delay circuit. An exclusive OR circuit,
The buffer receives the signal from the input terminal and outputs the signal to the output terminal, and the second buffer receives the signal from the input terminal through the delay circuit and outputs the signal to the output terminal. An output circuit, wherein an input signal and an output signal of a delay circuit are input to the exclusive OR circuit, and the output signal sets the second buffer to a high impedance state.