JPS5823674B2 - Kioku Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit, and more particularly to a memory circuit with low power consumption that includes a memory cell having a PNPN structure under equal constraints.

The circuit configuration of the memory circuit is a symmetrical circuit that consumes power in both on and off states, such as a flip-flop circuit, and a symmetrical circuit that consumes power in both the on and off states, such as a flip-flop circuit, and a circuit that consumes no power in the off state, which utilizes the self-retaining property of the PNPN structure. There is an asymmetric circuit.

In general, the former circuit is often used because it has excellent characteristics in terms of operational stability and high speed, but when the latter circuit is used in applications that strongly require low power consumption, By taking advantage of these advantages, an excellent storage device can be realized.

For example, a memory circuit used as a holding circuit for a communication path switch for a telephone exchange is most likely to be held in an OFF state, and is strongly required to have low power consumption.

Therefore, a holding circuit for a communication path switch whose basic configuration is extracted and shown in FIG. 1 is introduced on page 521 of the collection of lectures at the 1971 National Conference of the Institute of Electronics and Communication Engineers.

The function of this circuit is according to the truth table shown in FIG. 2, and when the transistor Q1. Both the PNPN structure storage cell 1 made up of Q2 and the logic 1 input section 2 made up of transistor Q3 have the excellent feature of zero power consumption.

However, when the memory circuit shown in FIG. 1 is used in a memory device arranged in a matrix as shown in FIG. 3 for writing and non-destructive reading of information, it has the following drawbacks.

The first drawback is that non-destructive reading is difficult.

That is, selecting the memory cell 1 by the logical inputs of X and y immediately writes information to the memory cell 1.

Therefore, if you dare to perform non-destructive reading,
It is necessary to read the state of the memory cell 1 using a selection circuit different from the x and X inputs in a holding state in which the information does not change depending on the input.

For example, in the circuit shown in FIG. 1, a separate reading circuit 3 connected to the output Q is used to read out information in the memory cell 1 using a selection circuit different from the x and X inputs.

Providing a selection circuit with separate input terminals for writing and reading in this way increases the number of terminals when implementing a semiconductor integrated circuit, increases the number of control gates in the front stage of the selection circuit, and complicates control. It is uneconomical and uneconomical.

Furthermore, considering the power consumption of the control gate in the previous stage, an increase in the number of gates is not preferable in terms of reducing power consumption, which is a feature of the circuit shown in FIG.

The second drawback is that as shown in Fig. 3, if a decoder is connected before the x and In order to eliminate this drawback, it is necessary to add a third control force Z as shown in FIG. 3 and to configure its function so as to satisfy the truth table shown in FIG. 4, for example.

If a conventional AND gate is used to create these two input terminals, the power consumption in the control logic input section will increase, and the features of the circuit shown in FIG. 1 will be discounted.

Furthermore, when manufacturing a large-capacity storage device, the number of AND gates increases, which is uneconomical.

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, that is, to satisfy the truth table of three human labor shown in FIG. An object of the present invention is to provide a memory circuit that consumes low power in an off-hold state.

The present invention improves the logic input section for controlling a PNPN structure storage cell with zero off-holding power, and forms the logic input section using one PNP) transistor and three NPN) transistors, so that it can be operated by three people. The memory cell and the read circuit are operated under control to enable write operations and non-destructive reading of information in the memory cell, and the power consumption of the logic input section in the holding state is reduced.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 5 shows a first embodiment of a memory circuit according to the present invention, in which 1 is a PNP) transistor Q1 and an NPN) transistor Q2.
The storage cell has a PNPN structure, and 2 has three NPN) transistors Q3 and Q5 under the equality constraints shown in .

3 is a logic input section consisting of a PNP transistor Q6 and one PNP transistor Q4, and a readout section consisting of a PNP transistor Q7 and an NPN transistor Q8.

X, y, and Z are each logic input terminals, Q is an output terminal, and S is a read terminal.

The function of this circuit operates according to the truth table shown in FIG.

That is, a write operation is performed on the memory cell 1 with the ``0'' level applied to the Z input and the 11'' level applied to the X input.

At this time, if a level of ``1'' is applied to the X input, the transistor Q2 of memory cell 1 passes through transistors Q4 and Q3.
A base current of 1 is supplied, and the memory cell 1 is turned on and programmed.

Furthermore, if a level of 10'' is applied to the X input, the base current of the transistor Q2 is output through the transistors Q4 and Qa, and the memory cell 1 is written off.

When the X'0 level is applied to any one of x, y, and z, the emitter current of the transistor Q7 in the readout section is not supplied, and therefore the base current of the transistor Q8 is not supplied, so the readout operation is not performed. Not performed.

Next, when the Z input is at the ``0'' level and the X input is at the ``O'' level, the base current is not supplied to the transistor Q, so it is turned off, and a write operation is performed on the memory cell 1 regardless of the X input. is not performed and the previous state is maintained.

Further, in a state where the "l" level is applied to the z input, no write operation is performed to the memory cell 1, and the previous state is maintained regardless of whether the x or X input is present.

X, y. When the '1' level is applied to the 23-bit power, emitter current can be supplied to the transistor Q7 in the reading section through the transistors Q5 and Qa, whose bases and collectors are commonly connected.

Therefore, depending on the state of memory cell 1, read transistor Q
8 works.

In other words, if memory cell 1 is on, transistor Q
7, the transistor Q8 is driven and turned on, and if the memory cell 1 is in the off state, the transistor Q7. Q8 is also turned off and a read operation is performed.

Transistor Q7 in the read section is a PNP transistor and does not draw current from output Q to turn on memory cell 1.

Furthermore, the current amplification factors of transistors Qt and Q2 are made sufficiently large so that memory cell 1 is not turned off by the base current of transistor Q7 when memory cell 1 is on.

If you listen carefully, non-destructive reading is possible.

In this circuit configuration, since the memory cell 1 has a PNPN structure, power consumption is zero in the off state.

There are five holding states in which neither write nor read operations are performed, which is a combination of three people, and one of these is when X input'X
In the remaining four holding states, excluding the holding states of ``O'', y-input section 1'', and 2 input section 1'', the transistors constituting both the logic input section 2 and the readout section 3 are in the off state, and the power consumption is zero, resulting in low power consumption. A storage device that operates on power consumption can be configured.

FIG. 6 shows a second embodiment of the memory circuit according to the present invention, in which the reading method of the memory cell 1 is different from the memory circuit shown in FIG. 5. A transistor Q9 with a common collector is provided, and its emitter is a PNP for readout)
It is connected to the base of transistor Q7.

To read the information of the memory cell 1, if the memory cell 1 is in the on state in the read state of the If the memory cell 1 is in the OFF state, the emitter current of the transistor Q9 will not flow, so this is detected by the transistors Q7 and Qs of the reading section 3 as in FIG.

PNP) transistors Q1 and Q9 of memory cell 1 are semiconductor integrated circuits.

A multi-emitter structure that is often used can be applied.

There are various modified circuits for the PNPN structure memory cell 1. For example, FIG. 7 shows a third embodiment of the present invention, and as shown in the figure, saturation control is performed by adding a transistor Q1o and a diode D, which are currently being filed separately by the present applicant.

A memory cell 1 having a PNPN structure that has been subjected to the above is applied to the present invention.

That is, as shown in FIG. 7, transistors Q1t Q2
, If the logic input section 2 and the readout section 3, which are operated by three people, are connected to the memory cell 1 composed of Qto and the diode D, as shown in FIG. 5, a memory circuit according to the truth table shown in FIG. becomes.

The read state of the logic input section 2 is "X input section 1", y input section 1''
, Z input 11", so the transistor Q5. The common base and emitter of Q6 can be connected to any input.

FIG. 8 shows a fourth embodiment of the memory circuit according to the present invention in which the connection method of the logic input section 2 is changed.The common base of the transistors Q5 and Qa is connected to the Z input terminal, and the two emitters are connected to the X, respectively. It is connected to the y input terminal.

Similarly, FIG. 9 shows a fifth embodiment of the memory circuit according to the present invention, in which transistors Q5. The common base of Q6 is connected to the X input terminal, and the two emitters are connected to the Y and Z input terminals, respectively.

The circuit configurations shown in FIGS. 8 and 9 are both memory circuits according to the truth table shown in FIG.

Note that the transistors Q5 and Q6 may be two NPN transistors whose bases and collectors are commonly connected, or may be multi-emitter transistors commonly used in semiconductor integrated circuits.

Furthermore, FIG. 10 shows another typical connection example of the transistors Q5 and Q6 constituting the logic input section in another embodiment of the present invention, in which the base and collector are not commonly connected as in the above embodiment. The base of transistor Q50 and the emitter of transistor Qa are connected in common, and the emitter of transistor Q5 and the collector and base of transistor Q6 are respectively connected to the Works according to value table.

Similar to the relationships in FIGS. 5, 8, and 9, connections to the x, y, and z inputs can be made arbitrarily.

Note that the embodiments shown in FIGS. 5, 6, 7, 8, 9, and 10 above are examples in which only transistors that perform basic logic operations are used. However, it is of course possible to add other elements within a range that does not impair this logical operation.

For example, the commonly connected transistors of the logic input section may not be directly connected, but may be commonly connected through a suitable current limiting resistor, level shift diode, or the like.

Similarly, the connections between the logic input section 2 and the memory cell 1, between the logic input section 2 and the readout section 3, or between the memory cell 1 and the readout section 30 may also be connected through resistors, diodes, etc., instead of being directly connected to each transistor.

Of course, the circuit configuration of the logic input section 2 readout circuit 30 is not limited to the illustrated example, and an appropriate level shift circuit or current limiting resistor may be connected to operate the logic circuit with noise margin. Alternatively, a resistor for discharging the accumulated charge of the transistor may be connected to further increase the speed of operation.

Further, for the configuration of the memory cell 1 having the PNPN structure, a modified circuit including various additional elements can be applied, as shown in an example in FIG.

For example, transistor Q1 of memory cell 1. In order to reduce the saturation of Q2 and speed up the turn-off time, a resistor may be connected to the collector of transistor Q2, or a Schottkino rear diode may be connected between the base and collector of transistor Q2.

Also, an impedance element or a transistor may be connected between the base and emitter of transistor Q1 or Q2 to protect against the well-known di/dt effect of the PNPN structure.

By using these circuit configurations of the present invention, an excellent storage device with a large storage capacity can be realized according to the block diagram shown in FIG.

As explained above, according to the present invention, a PNPN structure storage cell can be controlled by three-person logic input to perform write and non-destructive read operations, and is an excellent memory with low power consumption in the holding state. A circuit is obtained.

In addition, by using three-person control, it is possible to expand the storage capacity by arranging the cells in a matrix, and to avoid the problem of always writing to any one cell even when selective control is performed by a decoder.

[Brief explanation of the drawing]

FIG. 1 is a conventional two-manpower storage circuit, FIG. 2 is a truth table of the two-manpower storage circuit shown in FIG. 1, and FIG. 3 is a block diagram of a memory device configured in a matrix in which the present invention is used. , FIG. 4 is a truth table of a three-person memory circuit according to the present invention, FIG. 5 is an embodiment of a memory circuit according to the present invention, and FIG.
7, 8, 9 and 10 all show other embodiments of the memory circuit according to the present invention.

Claims (1)

[Claims] 1. X, y that control write, read, and hold states
, Z3 consists of a human-powered logic input section, a storage cell with a PNPN structure under constraints controlled by the logic input, and a readout section, and the logic input section has at least one PNP structure.
) transistor and 3 ΩNPN) transistors, the emitter of the PNP) transistor is the X input, and the base is the 2
Connect the collector to the base of the first NPN) transistor, connect the emitter of the first ONPN) transistor to the X input, connect the collector to the storage cell, and connect the second and third ONPN
N) The base and collector of each transistor are commonly connected,
A memory circuit characterized in that the common collector is connected to the readout section, and the common base and the two emitters are each connected to one of the X, y, and Z inputs. 2 Xy, z to control write, read and hold status
3 human-powered logic input section and a PNPN structure storage cell with equal constraints controlled by the logic input. The logic input section consists of at least one PNP transistor and three NPN transistors, the emitter of the PNP transistor is the X input, the base is the Z input, and the collector is the first ONPN transistor. the emitter of the first NPN) transistor is connected to the X input, the collector is connected to the memory cell, the emitter of the second NPN transistor is connected to the base of the third NPN) transistor, the third ONPN) The collector of the transistor is connected to the readout section, and the collector and base of the second ONPN transistor and the emitter of the third NPN transistor are each connected to one of the X, y, and Z inputs. Characteristic memory circuit.