JPS5823950B2 - Semiconductor device and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices such as high frequency transistors and diodes with improved electrode structures, and a method for manufacturing the same.

Conventionally, the electrode structure of a planar microwave transistor is constructed as shown in FIG.

The structure will be specifically explained with reference to FIG.

For example, a base region 2 is formed inside the semiconductor substrate 1 from one main surface of a semiconductor substrate 1 made of silicon, an emitter region 3 is formed from the main surface within the base region, and the rest of the substrate 1 is a collector region 4. It has become.

Further, an oxide film 5 is deposited and has an opening that exposes a part of the surface of the emitter region 3 and the base region 2.
On the exposed surfaces of the emitter region 3 and the base region 2, an emitter lead electrode 6 and a base lead electrode 7, which are metal layers made of, for example, titanium and aluminum, are formed in ohmic contact with each other.

A silicon oxide film 8 having openings that expose parts of the emitter extraction electrode 6 and the base extraction electrode 7 is formed on these extraction electrodes, and on this silicon oxide film 8, An emitter bonding pad 9 and a base bonding pad 10 made of aluminum metal layers are deposited to contact the emitter extraction electrode 6 and the base extraction electrode 7 through the openings.

Such an electrode structure in which the extraction electrode and the bonding pad are formed separately (hereinafter referred to as a double electrode) is used for the following two reasons.

(a) Since there is a large distance between the bonding pad and the collector area below it, it is possible to create a so-called MOS (MOS).
) The parasitic capacitance of the structure is reduced.

Therefore, the base-collector capacitance and the emitter-collector capacitance are reduced, and frequency characteristics are improved.

(b) In order to improve the frequency characteristics, a thin emitter width and a narrow base region are required, and therefore an electrode width of 3 to 4 μm or less is required.

A thin metal layer is preferable to form such a thin electrode, but a thicker metal layer is preferable for bonding, so a double structure is used to facilitate bonding.

Such double electrode formation has been easily accomplished in the past without any problems in the case of aluminum-based electrodes as described above.

On the other hand, compared to the aluminum layer, the gold layer is more susceptible to electromigration.
), so it can be used up to high current densities, and because it has corrosion resistance and ductility, it has the advantage of being able to create a metallurgically stable assembly by thermocompression bonding a gold wire to a gold layer.

Therefore, gold thread electrodes have come to be widely used as electrodes for semiconductor devices that require reliability.

Of course, when used alone, it is easy to form a eutectic alloy with silicon at low temperatures, which deteriorates the characteristics of the device and also has poor adhesion to the silicon oxide film, so a gold-molybdenum two-layer electrode is generally used.

Used in multilayer structures such as gold-platinum-titanium two-layer electrodes.

By the way, the double electrode structure of the gold thread electrode requires the following two conditions regarding the metal layer forming the bonding pad.

(a)' Sputtering method or CV D (chemica
It must have good adhesion to the silicon oxide film obtained by the LVAP deposition method.

(b)' It must be a metal layer that has good adhesion to gold, which is the uppermost metal layer of the extraction electrode, has electrical resistance contact, and does not chemically react with gold.

However, for example, in the gold-molybdenum two-layer structure, the adhesion between the molybdenum and the silicon oxide film (sputtered CVD film) is not very good, so peeling often occurs during bonding, and the gold-platinum-titanium three-layer structure A dual electrode structure that satisfies the above two requirements, such as titanium and the gold of the extraction electrode reacting at relatively low temperatures (below 400°C) to form a high-resistance layer, has been developed for the first time.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that do not cause peeling during bonding and do not form high resistance in the lead-out electrode portion.

An embodiment of the present invention will be described below with reference to FIG. 2 g=h.

Note that all figures are cross-sectional views of striped emitters.

FIG. 2g is a diagram of a silicon transistor at the time when the steps up to electrode formation have been completed, in which a base region 22 is formed inside the semiconductor substrate 21 from the entire surface thereof, and the base region 22 is further formed within the base region 22 on the main surface. An emitter region 23 is formed therein, and the remainder of the base body 21 is a collector region 24.

Further, a silicon oxide film 25 is deposited to expose a portion of the surfaces of the emitter region 23 and base region 22.

A conductive layer 26 having a thickness of approximately 500 layers of titanium, 2,000 layers of molybdenum, and 10,000 layers of gold is continuously deposited on the main surface using an electron beam evaporator (FIG. 2b).

Subsequently, the photoresist is patterned using a conventional PEP (photolithography) technique, and using this as a mask, the conductive layer 26 is selectively etched (FIG. 2C).

After completing the formation of the conductive layer which will become the extraction electrode in this way, a silicon oxide film 27 of about 1 μm is deposited on the main surface using a sputtering device or a CVD device (FIG. 2d).

Subsequently, 300A of titanium and 700A of molybdenum are deposited on the silicon oxide film 27 using a sputtering device or an electron beam evaporation device.

A first metal layer 28 with a thickness of about 1000A of gold is deposited (
FIG. 2 e) The conductive layer 28 made of gold-molybdenum-titanium and the silicon oxide film 27 are formed by using ordinary PEP technology.
The holes are formed by continuous etching (Fig. 2f).

A gold layer (second metal layer) 29 is deposited on the surface of the article having the openings thus obtained by using resistance heating vapor deposition or the like.
~2 μm deposits (Figure 2g).

Subsequently, the gold layer 29 and the first metal layer 28 made of gold-molybdenum-titanium are selectively etched using conventional PEP techniques to form the desired bonding pads (see FIG. 2h).
).

In a double-electrode structure transistor formed through such a process, there is no metal other than titanium or molybdenum between the bonding pad and the extraction electrode, and the contact is gold-gold, so there is no extra contact resistance. It becomes a double electrode that is chemically and electrically stable.

Further, since the contact surface between the bonding pad and the underlying silicon oxide film has a chikune silicon oxide film structure, the adhesion is very good and there is no problem of the electrode peeling off during bonding.

Further, in the above embodiment, a metal layer made of gold-molybdenum-titanium was used as the metal layer 28 deposited on the silicon oxide film 27, but aluminum, which exhibits good adhesion to silicon oxide films like titanium, may be used instead of titanium. The metal layer made of gold-molybdenum-aluminum used in the above may also be used.

Although the microwave transistor has been described above, the present invention can of course be applied to other semiconductor devices including Schottky junction diodes and interconnects in integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional microwave transistor having a double electrode structure, and FIG. 2 (a=h) is a process sectional view for explaining an embodiment of the present invention. 21...Semiconductor base, 22...Base region, 23...Emitter region, 24...
・Collector region, 25° 27... Silicon oxide film, 26... Conductive layer made of gold-molybdenum-titanium, 28... First layer made of gold-molybdenum
The metal layer 29 is a gold layer (second metal layer).

Claims (1)

[Scope of Claims] 1. A conductive layer provided on a semiconductor substrate and having at least the uppermost layer made of gold, an insulating film provided on the conductive layer and having an opening, and a periphery of the opening in the insulating film. a first metal layer having good adhesion with the insulating film provided on the insulating film; 1. A semiconductor device comprising: a second metal layer made of gold; and a second metal layer made of gold. 2. A step of forming a conductive layer on a semiconductor substrate, the uppermost layer of which is gold, a step of forming an insulating film on the conductive layer, and a step of forming a first conductive layer having good adhesion with the insulating film on the insulating film. a step of forming a metal layer, a step of selectively etching the first metal layer, and etching the insulating film using the first metal layer left in the step as a mask to expose the conductive layer. A method for manufacturing a semiconductor device, comprising: a step of forming a second metal layer made of gold on the conductive layer and the first metal layer exposed in the step.