JPS5824012B2 - Manufacturing method of mounting body - Google Patents
Manufacturing method of mounting bodyInfo
- Publication number
- JPS5824012B2 JPS5824012B2 JP54030366A JP3036679A JPS5824012B2 JP S5824012 B2 JPS5824012 B2 JP S5824012B2 JP 54030366 A JP54030366 A JP 54030366A JP 3036679 A JP3036679 A JP 3036679A JP S5824012 B2 JPS5824012 B2 JP S5824012B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- resin
- opening
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
- H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、実装体の製造方法に関しIC,LSI等の素
子上に形成された電極端子を外部回路の電極端子へ電気
的に導出する方法として、従来いくつかの方法が開発さ
れたが、最とも公知な方法として25〜37ψμmのA
u、A1等の極細線で、前記電極端子同志を熱圧着法も
しくは超音波法によって接続する、いわゆるワイヤボン
ディング技術がある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a packaged body, and relates to a method for electrically leading out an electrode terminal formed on an element such as an IC or LSI to an electrode terminal of an external circuit. was developed, but the most known method is the A
There is a so-called wire bonding technique in which the electrode terminals are connected to each other by thermocompression bonding or ultrasonic bonding using ultrafine wires such as U and A1.
この方法では、電極端子数が少ない場合には、接続の信
頼性も高いが、近年のLSIの様に1素子内の機能数が
高まるにつれ、前記電極端子の数も40〜70端子と多
くなってくると、この接続を行なうのに2回のボンディ
ングを必要とするため、接続数が極めて多くなる。In this method, the reliability of the connection is high when the number of electrode terminals is small, but as the number of functions in one element increases as in recent LSIs, the number of electrode terminals increases to 40 to 70 terminals. In this case, since bonding is required twice to make this connection, the number of connections becomes extremely large.
すなわち素子の電極端子数が70端子を有する場合には
、その接続数は140個にも達する。That is, if the element has 70 electrode terminals, the number of connections reaches 140.
このために接続の信頼性を低下させ、かつこの接続工程
での低コスト化の実現は困難であった。This lowers the reliability of the connection and makes it difficult to reduce the cost of this connection process.
又、外部回路への接続にあたっても、前記IC,LSI
素子を−たん、回路基板に固定する必要があり、かつ極
細線で接続する時、素子表面より極細線が彎曲した形で
持ち上がるため、薄型、小型化したパッケージの実現は
著しるしく困難であった。Also, when connecting to external circuits, the above-mentioned IC, LSI
The device must be fixed to the circuit board, and when it is connected using ultra-fine wires, the ultra-fine wires are lifted up in a curved manner from the surface of the device, making it extremely difficult to create a thinner and more compact package. Ta.
この様な欠点をなくするために、前記電極端子をたとえ
ば70個一度に処理する、いわゆる極細線を用いないワ
イヤレス技術が実用化されてきた。In order to eliminate such drawbacks, a so-called wireless technology that does not use ultra-fine wires has been put into practical use, which processes, for example, 70 electrode terminals at once.
例えばこのワイヤレス技術におけるビームリード方式は
、前記素子がシリコンのウェハプロセス段階で前記素子
の電極端子に矩形状の電極リードを形成するものである
。For example, in the beam lead method in this wireless technology, a rectangular electrode lead is formed on the electrode terminal of the element at the stage of processing a silicon wafer.
ところが、ビームリード方式では電極端子から伸びた電
極リードの形成されるシリコン面には素子を形成する事
が出来ない。However, in the beam lead method, elements cannot be formed on the silicon surface where electrode leads extending from electrode terminals are formed.
このため1ウエハー内での素子が形成される有効面積は
、完全に全ウェハー内に素子が形成された場合に較べ5
0〜60チとなりウェハーの利用効率が極めて悪くなる
。Therefore, the effective area in which elements are formed within one wafer is 55% compared to when elements are formed completely within the entire wafer.
0 to 60 inches, resulting in extremely poor wafer utilization efficiency.
すなわち、リードの長さは通常0.7〜1.2朋である
から、1素子の周辺のこの長さにひってきするシリコン
領域は完全にリード形成のためにしか存在しない、した
がって高価なシリコンウェハーを無駄に使用するばかり
か、電極リード形成の製造工程が複雑であるためにかえ
って、高価となり薄型化、小型化は実現されるが、低コ
スト化の実現は困難であった。That is, since the lead length is usually 0.7 to 1.2 mm, the silicon area around this length around one element exists solely for lead formation, and therefore requires expensive silicon. Not only is the wafer wasted, but the manufacturing process for forming electrode leads is complicated, which makes it more expensive, and although thinner and more compact devices can be achieved, it has been difficult to achieve lower costs.
又フィルムキャリヤ方式では、ウェハプロセス段階で素
子の電極端子上に金属突起物(通常バンプと呼ばれる)
を設け、この金属突起物にポリイミドフィルム上に形成
したSnメッキ処理したCu箔のリードを加圧加熱させ
、Au−8n共晶を形成する事によって、接続を行なう
ものであるが、この方式においては、金属突起物とリー
ドとの接続を行なわなければならないため、接続の箇所
数がワイヤポンチ゛イング法と同じくなるためかえって
工数が増る。In addition, in the film carrier method, metal protrusions (usually called bumps) are placed on the electrode terminals of the device during the wafer process stage.
The connection is made by applying pressure and heating to the Sn-plated Cu foil lead formed on the polyimide film on the metal protrusion to form an Au-8n eutectic. In this method, since the metal protrusion and the lead must be connected, the number of connection points is the same as in the wire punching method, which increases the number of man-hours.
本発明は表面に外部接続用の電極端子が形成されている
たとえばIC,LSI等の素子にメッキ法を用いること
によりリード電極を形成する方法により、上記不都合を
解消できる方法を提供するものである。The present invention provides a method for solving the above-mentioned disadvantages by forming lead electrodes by plating on elements such as ICs and LSIs, which have electrode terminals for external connection formed on their surfaces. .
以下、本発明の実施例を図面とともに説明する。Embodiments of the present invention will be described below with reference to the drawings.
第1図においてポリイミド、ポリエステル等の連続した
樹脂フィルム1には第1の開孔部2が設けられ、10〜
100μm厚さのCu、A1等の第1の金属膜3が接着
剤等で、樹脂フィルム1に貼付される。In FIG. 1, a continuous resin film 1 made of polyimide, polyester, etc. is provided with first openings 2, and
A first metal film 3 of Cu, A1, etc. having a thickness of 100 μm is attached to the resin film 1 with an adhesive or the like.
次いで第1の金属膜3には後述する素子4の電極端子5
近傍を開孔した第2の開孔部6が形成される。Next, the first metal film 3 is provided with an electrode terminal 5 of the element 4, which will be described later.
A second aperture 6 is formed in the vicinity.
この第2の開孔部6は第2図aに示す如く列方向の素子
4の電極端子5にまたがる様に長孔であっても良いし、
あるいは第2図すの如く素子の電極端子5に相当する円
孔であっても良い。This second opening 6 may be a long hole so as to span the electrode terminals 5 of the elements 4 in the column direction, as shown in FIG. 2a, or
Alternatively, it may be a circular hole corresponding to the electrode terminal 5 of the element as shown in FIG.
第3図に示す素子4はIC,LSIの如き電子回路素子
で、ダイシングソーによって分割され、素子表面には、
樹脂7が塗布される。The element 4 shown in FIG. 3 is an electronic circuit element such as an IC or LSI, and is divided by a dicing saw.
Resin 7 is applied.
この樹脂7は少なくとも熱硬化性樹脂で接着性を有する
樹脂であって、例えば、感光性樹脂の如きものでも良い
。The resin 7 is at least a thermosetting resin having adhesive properties, and may be, for example, a photosensitive resin.
塗布が終れば、第1の金属膜3の開孔部6と素子4の電
極端子5とを位置合せし、熱圧着させ、硬化し固定させ
る(第3図a)。When the coating is completed, the openings 6 of the first metal film 3 and the electrode terminals 5 of the element 4 are aligned, thermocompressed, and cured and fixed (FIG. 3a).
次に第1の金属膜3をマスクとして、第2の開孔部6に
露出している樹脂7をプラズマ処理又はスパッター処理
によって開孔し、素子4の電極端子5を露出させる(第
3図b)。Next, using the first metal film 3 as a mask, the resin 7 exposed in the second opening 6 is opened by plasma treatment or sputtering to expose the electrode terminal 5 of the element 4 (Fig. 3). b).
しかるのちこの露出部6′の電極端子5を含み、第1の
金属膜3上に第2の複数層からなる金属膜8を真空蒸着
法で被着せしめる(第3図C)。Thereafter, a second metal film 8 consisting of multiple layers is deposited on the first metal film 3, including the electrode terminal 5 of the exposed portion 6', by vacuum evaporation (FIG. 3C).
第2の複数層からなる金属膜8は、Cr−CuyCr−
Cu−Au、Cr−Ni、Cr−Ag、Cr Au、
Ti CuyT i −A u等の組合せであって、
Cr、Ti膜は直接素子又は第1の金属膜表面と接し、
付着強度を高めるための材料であり、Cu、Ag、Au
、Niは導電性を高めるための材料である。The second metal film 8 consisting of multiple layers is Cr-CuyCr-
Cu-Au, Cr-Ni, Cr-Ag, CrAu,
A combination of Ti CuyT i -A u, etc.,
The Cr, Ti film is in direct contact with the element or the first metal film surface,
A material for increasing adhesive strength, including Cu, Ag, and Au.
, Ni is a material for increasing conductivity.
Cr、Ti膜は500〜2000人、 Cu 、 Ag
、Au 、Niは3000〜20000λ被着する。Cr, Ti film: 500-2000 people, Cu, Ag
, Au, and Ni have a thickness of 3000 to 20000λ.
次に第2の複数層からなる金属膜8上に感光性樹脂膜9
を塗布し、素子4の電極端子5近傍の金属膜3の開孔部
6′を含み、樹脂フィルム1まで延在した矩形状のパタ
ーン9′を光蝕刻法によって形成する(第3図d)。Next, a photosensitive resin film 9 is placed on the second metal film 8 consisting of multiple layers.
A rectangular pattern 9' including the opening 6' of the metal film 3 near the electrode terminal 5 of the element 4 and extending to the resin film 1 is formed by photoetching (FIG. 3d). .
こうしたのち、金属膜3もしくは第2の複数層からなる
金属膜8を一方の電極として、感光性樹脂9による矩形
状のパターン9′の金属膜8が露出した面にAu、Ag
、Cu等の第3の金属膜10をメッキ処理して形成する
。After this, using the metal film 3 or the second metal film 8 made of multiple layers as one electrode, Au, Ag, etc.
, Cu, or the like is formed by plating.
しかるのち、感光性樹脂9および第1の金属膜3、第2
の複数層からなる金属膜8をエツチング除去すれば第3
図eの状態を得る。After that, the photosensitive resin 9, the first metal film 3, and the second
If the metal film 8 consisting of multiple layers is removed by etching, the third
Obtain the state shown in Figure e.
第4図は第3図eの斜視図である。FIG. 4 is a perspective view of FIG. 3e.
素子4は電極端子5上に第2の複数層からなる金属膜8
を介してメッキにより形成した金属膜10が設けられ、
金属膜10は電極リードとなる。The element 4 has a second multilayer metal film 8 on the electrode terminal 5.
A metal film 10 formed by plating is provided through the
The metal film 10 becomes an electrode lead.
又、前記電極リードとしての金属膜10の他端は樹脂フ
ィルム1上に第1の金属膜1および第2の複数層からな
る金属膜8を介して固定される。Further, the other end of the metal film 10 as the electrode lead is fixed onto the resin film 1 via the first metal film 1 and the second metal film 8 consisting of multiple layers.
このように、本発明では素子4の電極端子5上にメッキ
処理により容易かつ正確に外部接続用の電極リードが形
成できる。As described above, in the present invention, electrode leads for external connection can be easily and accurately formed on the electrode terminals 5 of the element 4 by plating.
第3図e1の状態の素子を他の回路基板に実装する場合
には電極リード10のAの部分より切断して素子4を樹
脂フィルム1より取りはずし、他の基板にリード10を
接続すればよい。When mounting the element in the state shown in Fig. 3 e1 on another circuit board, it is sufficient to cut the electrode lead 10 from the part A, remove the element 4 from the resin film 1, and connect the lead 10 to the other board. .
又、本発明の製造方法においては、樹脂フィルム1は単
なる搬送のための材料であるから消耗する事がない。Furthermore, in the manufacturing method of the present invention, the resin film 1 is not consumed because it is simply a material for conveyance.
したがって素子が取りはずされた後、何回でも再生使用
する事が出来る。Therefore, after the element is removed, it can be recycled and used any number of times.
更に素子4は電気的に良品のみを選別して使用出来るの
で、製造上の歩留りを著しるしく向上させ、低コスト化
が可能となる。Furthermore, since the elements 4 can be used by selecting only electrically good products, manufacturing yield can be significantly improved and costs can be reduced.
以上の方法により以下にのべる効果が発揮される。The above method provides the following effects.
■ 既に述べた如くフィルムキャリヤ方式は素子チップ
の取扱いがテープ搬送であるために量産性に富むものの
、ウェハ状態で形成された電極リードとを接続するため
のボンディング工程(通常ILBと呼ばれる)を必要と
する。■ As mentioned above, the film carrier method is highly suitable for mass production because the element chips are handled by tape transport, but it requires a bonding process (usually called ILB) to connect the electrode leads formed on the wafer. shall be.
このボンディング工程によって熱(400〜500°C
)、圧力(30〜60g/パッド)がバンプおよび素子
の電極上に加わるためにAA電極端子が変形し、Al電
極端子上の一部を覆っているCVD S t 02膜に
クラックが発生する。This bonding process heats (400-500°C)
), the AA electrode terminal is deformed due to the pressure (30-60 g/pad) applied on the bump and the electrode of the device, and cracks occur in the CVD S t 02 film covering part of the Al electrode terminal.
このクラックによりAl電極端子が露出するため、この
部分よりAl電極端子の腐蝕性溶液が浸入し、Al電極
端子を溶解させてしまい、バンプの強度を低下させ、バ
ンプ間の接触抵抗を高くする等、信頼性を低下さす原因
となっていた。Since the Al electrode terminal is exposed due to this crack, the corrosive solution of the Al electrode terminal enters from this part and dissolves the Al electrode terminal, reducing the strength of the bump and increasing the contact resistance between the bumps. , which caused a decrease in reliability.
しかしながら本発明の製造方法による電極リードの形成
においては、リードの形成が、メッキ法で形成される(
これは丁度フィルムキャリヤ方式のバンプ形成と同一な
手法で形成される)ため、フィルムキャリヤ方式の如く
、ILB工程を必要とせず、かつCVD5102のクラ
ックの発生がないから工数の削減ならびに信頼性を高め
る事が出来る。However, in forming electrode leads by the manufacturing method of the present invention, the leads are formed by a plating method (
(This is formed using the same method as bump formation using the film carrier method), unlike the film carrier method, there is no need for an ILB process, and there is no cracking of CVD5102, reducing man-hours and increasing reliability. I can do things.
更にフィルムキャリヤ方式における電極端子上へのバン
プ形成は、メッキ工程がウェハ状態で行なわれるために
、不良チップも含めて全チップの電極端子上にバンプが
形成される。Furthermore, in the film carrier method, bumps are formed on the electrode terminals of all chips, including defective chips, because the plating process is performed on the wafer.
このために不良チップに形成されたバンプ(例えばAu
バンプ)はまったくの無駄となる。For this reason, bumps formed on defective chips (e.g. Au
bump) is a complete waste.
しかし、本発明においては、良品のみをあらかじめ選別
し、良品のチップのみに電極リードを形成出来るため、
材料の無駄を除く事が出来、製造コストが廉価になる。However, in the present invention, only good chips can be selected in advance and electrode leads can be formed only on good chips.
Waste of materials can be eliminated and manufacturing costs can be reduced.
■ また、ビームリード方式はビームリードの分だけウ
ェハ面積を占有する必要があるからウェハ当りのチップ
の収率は著しるしく悪くなるし、不良チップに対しても
ビームリードの形成を行なうので、その分だけ材料が無
駄になり、製造コストが高くなる。■ Also, in the beam lead method, it is necessary to occupy the wafer area by the amount of the beam lead, so the yield of chips per wafer deteriorates significantly, and since beam leads are also formed for defective chips, This wastes material and increases manufacturing costs.
しかるに本発明の製造方法においては、ウェハ面積を余
分に損失する事もないし、又、良品のチップのみを選別
して、製造プロセスに投入出来るため製造コストを廉価
に出来る。However, in the manufacturing method of the present invention, there is no additional loss of wafer area, and since only good chips can be selected and input into the manufacturing process, manufacturing costs can be reduced.
又、電極リードを形成されたチップがフィルムテープ上
に連続して、載置された状態であるので、チップの取扱
いが容易で、量産性に富む等の特徴を有するものである
。Furthermore, since the chips on which the electrode leads are formed are placed continuously on the film tape, the chips are easy to handle and can be easily mass-produced.
次に、本発明の他の実施例の方法を説明する。Next, a method according to another embodiment of the present invention will be described.
第5図のポリエステル、ポリイミド等の樹脂フィルム1
1には開孔部12が設けられ、第1の感光性樹脂13が
樹脂フィルム11上に貼りつけられる。Fig. 5 Resin film 1 made of polyester, polyimide, etc.
1 is provided with an opening 12, and a first photosensitive resin 13 is pasted onto the resin film 11.
第1の感光性樹脂13はフィルム状の感光性樹脂を第1
図の如く圧着しても良いが、ローラ塗布装置によって樹
脂フィルム11上に均一に形成する事が出来る。The first photosensitive resin 13 is a film-like photosensitive resin.
Although pressure bonding may be used as shown in the figure, it is possible to uniformly form the resin film 11 on the resin film 11 using a roller coating device.
次いで第6図のとと<IC,LSI等の素子14を樹脂
フィルム11の開孔部12の中央部に設置し、第1の感
光性樹脂13面上に圧着固定する。Next, an element 14 such as an IC or an LSI shown in FIG. 6 is placed in the center of the opening 12 of the resin film 11 and fixed by pressure on the surface of the first photosensitive resin 13.
しかるのち素子14の電極素子近傍と樹脂フィルムの一
部を光蝕刻法により開孔部15,16を形成する(第6
図a)。Thereafter, openings 15 and 16 are formed in the vicinity of the electrode element of the element 14 and a part of the resin film by photolithography (sixth hole).
Diagram a).
樹脂フィルム11上の第1の感光性樹脂13は樹脂フィ
ルム11の両端に位置する如くに形成される。The first photosensitive resin 13 on the resin film 11 is formed so as to be located at both ends of the resin film 11.
第6図a・の状態で120〜180℃の温度で第1の感
光性樹脂は熱処理され、熱硬化される。The first photosensitive resin is heat-treated at a temperature of 120 to 180° C. in the state shown in FIG. 6a, and is thermally cured.
次に素子14面を含む第1の感光性樹脂13上に真空蒸
着法により複数層からなる金属膜17を全面に被着する
(第6図b)。Next, a metal film 17 consisting of multiple layers is deposited over the entire surface of the first photosensitive resin 13 including the surface of the element 14 by vacuum evaporation (FIG. 6b).
金属膜17は、Cr−Cu、Cr−Cu−Au、Cr−
Ni、Cr−Ag。The metal film 17 is made of Cr-Cu, Cr-Cu-Au, Cr-
Ni, Cr-Ag.
Cr−Au 、 T i −Cu 、 T 1−Au等
の組合せであって、Cr、Ti膜は直接素子表面と接し
、素子表面との付着強度を得るための材料であり、Cu
、Ag、Au。A combination of Cr-Au, Ti-Cu, T1-Au, etc., where the Cr and Ti films are in direct contact with the element surface and are materials for obtaining adhesion strength with the element surface, and Cu
, Ag, Au.
Niは導電性を高めるための材料である。Ni is a material for increasing conductivity.
複数層からなる金属膜17上に第2の感光性樹脂膜18
を塗布する。A second photosensitive resin film 18 is formed on the metal film 17 consisting of multiple layers.
Apply.
第2の感光性樹脂18は、フィルム状の感光性樹脂を貼
りつけても良いが、ローラ塗布装置によって金属膜17
上に塗布しても良い。The second photosensitive resin 18 may be pasted onto the metal film 18 using a roller coating device.
It may be applied on top.
次に第1の感光性樹脂の開孔部15(素子14の電極端
子近傍)を含み樹脂フィルム11まで達する矩形状のパ
ターン19を形成する。Next, a rectangular pattern 19 that includes the openings 15 (near the electrode terminals of the element 14) in the first photosensitive resin and reaches the resin film 11 is formed.
これを第6図Cに示した。This is shown in Figure 6C.
しかるのち複数層からなる金属膜17を一方のメッキ電
極としてメッキ法により第2の感光性樹脂18によって
形成した矩形状のパターン19の金属膜17が露出した
面Au、Ag、Cu等の金属層20を形成させる。Thereafter, a surface of a rectangular pattern 19 on which the metal film 17 of a rectangular pattern 19 is formed by plating with the second photosensitive resin 18 using the metal film 17 consisting of multiple layers as one plating electrode is coated with a metal layer of Au, Ag, Cu, etc. Form 20.
メッキ処理が終れば、第1、第2の感光性樹脂を除去し
、更に露出した複数層からなる金属膜17の一部を除去
すれば、第6図dの形状を得る。After the plating process is completed, the first and second photosensitive resins are removed, and a portion of the exposed metal film 17 consisting of multiple layers is removed to obtain the shape shown in FIG. 6d.
第6図dにおいて素子14の電極端子には金属膜17を
介してメッキにより形成した電極リード(金属層)20
があり、この電極リード20は樹脂フィルム14上に金
属膜17により接した構造となっている。In FIG. 6d, an electrode lead (metal layer) 20 is formed on the electrode terminal of the element 14 by plating with a metal film 17 interposed therebetween.
The electrode lead 20 has a structure in which it is in contact with a resin film 14 via a metal film 17.
すなわち素子14は樹脂フィルム11の開孔部12に電
極リード20を介して固定された状態となっている。That is, the element 14 is fixed to the opening 12 of the resin film 11 via the electrode lead 20.
第7図に第6図dの状態の外観を示す。FIG. 7 shows the appearance of the state shown in FIG. 6d.
このように、第6図の方法にても前述の実施例と同様に
電子回路素子の実装体を得ることができる。In this way, the method shown in FIG. 6 can also provide a packaged electronic circuit element in the same manner as in the above-mentioned embodiments.
なお、第6図においてもdのBの位置より切断すれば、
フィルム11と素子14を切り離すことができる。In addition, in Fig. 6, if you cut from position B of d,
The film 11 and the element 14 can be separated.
そして、第6図の製造方法においても、樹脂フィルム2
は最終工程までなんら損傷する事がないので、再生し何
回も再使用する事が出来る。Also in the manufacturing method shown in FIG. 6, the resin film 2
Since there is no damage until the final process, it can be recycled and reused many times.
以上第6図の方法でも第3図の方法と同様の効果を得る
ことができる。The method shown in FIG. 6 can also achieve the same effect as the method shown in FIG. 3.
以上のように、本発明は従来のビームリード、フィルム
キャリヤ方式のもつ欠点を一掃し、独特の製造方法を提
供するものであり、低コストで信頼性の高い、薄型、小
型化したリード端子を有する半導体装置等の電子回路素
子の実装体を得ることができ、高密度実装に大きく寄与
するものである。As described above, the present invention eliminates the drawbacks of the conventional beam lead and film carrier methods, and provides a unique manufacturing method, which enables a thinner and smaller lead terminal to be produced at low cost and with high reliability. This makes it possible to obtain a packaged body for electronic circuit elements such as semiconductor devices, which greatly contributes to high-density packaging.
第1図は本発明に用いる樹脂フィルムと金属膜の一例の
斜視図、第2図a、1)はフィルム上の金属膜を開孔し
た状態の斜視図、第3図a−eは本発明の一実施例の実
装体の製造工程断面図、第4図は第3図eの斜視図、第
5図は本発明に用いる樹脂フィルムと感光性樹脂の斜視
図、第6図a〜dは本発明の他の実施例の実装体の製造
工程断面図、第7図は第6図dの斜視図である。
1.11・・・・・・樹脂フィルム、2,6.6’、1
2・・・・・・開孔部、3,17・・・・・・金属膜、
4,14・・・・・・素子、7,9,13,18・・・
・・・感光性樹脂、9′。
19・・・・・・開孔パターン、10,20・・・・・
・電極IJ−ド。Figure 1 is a perspective view of an example of the resin film and metal film used in the present invention, Figures 2a and 1) are perspective views of the metal film on the film with holes opened, and Figures 3 a-e are the invention. FIG. 4 is a perspective view of FIG. 3e, FIG. 5 is a perspective view of the resin film and photosensitive resin used in the present invention, and FIGS. FIG. 7 is a cross-sectional view of the manufacturing process of a package according to another embodiment of the present invention, and FIG. 7 is a perspective view of FIG. 6d. 1.11...Resin film, 2, 6.6', 1
2...Opening part, 3,17...Metal film,
4, 14... element, 7, 9, 13, 18...
...Photosensitive resin, 9'. 19...hole pattern, 10,20...
- Electrode IJ-do.
Claims (1)
属膜を貼付する工程と、前記第1の金属膜において素子
の電極端子近傍に位置する領域を開孔し第2の開孔部を
形成する工程と、前記素子表面に接着用膜を塗布する工
程と、前記第1の金属膜の第2の開孔部と前記素子の電
極端子とを位置合せして、圧着する事によって前記接着
用膜にて第1の金属膜に前記素子を固定する工程と、前
記第1の金属膜の第2の開孔部より露出した前記接着用
膜を除去する工程と、前記第1の金属膜上に第2の金属
膜を被着させる工程と、前記第2の金属膜上に樹脂膜を
塗布し、この樹脂膜の前記素子の電極端子近傍を含み前
記絶縁性フィルム上に達する領域を光蝕刻法で開孔し、
第3の開孔部を形成する工程と、第1の金属膜もしくは
第2の金属膜を一方の電極として、前記第3の開孔部の
露出した第2の金属膜上にメッキ処理して第3の金属膜
を形成する工程と、前記樹脂膜および第1、第2の金属
膜を除去する工程とを備え、前記素子の電極端子上に前
記第3の金属膜よりなる電極り一部を形成することを特
徴とする実装体の製造方法。 2 第1の開孔部を有する絶縁性フィルム上に第1の樹
脂膜を貼付する工程と、前記フィルムの第1の開発部に
素子を固定する工程と、前記素子の電極端子近傍および
前記フィルム上の樹脂膜の一部に第2の開孔部を形成す
る工程と、前記フィルム上に金属膜を被着する工程と、
前記金属膜上に第2の樹脂を塗布し、前記素子の電極端
子近傍の第2の開孔部を含み前記フィルム上に至る第2
の樹脂の領域を開孔する工程と、前記金属膜を一方の電
極として、第2の樹脂により開孔した領域に金属層をメ
ッキ処理で形成する工程と、前記第1゜第2の樹脂を除
去し、露出した金属膜を除去する工程とを備え、前記素
子の電極端子上に前記金属層よりなる電極リードを形成
することを特徴とする実装体の製造方法。[Claims] 1. A step of pasting a first metal film on an insulating film having a first opening, and opening a region of the first metal film near an electrode terminal of an element. a step of forming a second aperture, a step of applying an adhesive film to the surface of the element, and a step of aligning the second aperture of the first metal film and an electrode terminal of the element. a step of fixing the element to the first metal film with the adhesive film by pressure bonding, and a step of removing the adhesive film exposed from the second opening of the first metal film. a step of depositing a second metal film on the first metal film; and a step of applying a resin film on the second metal film, and covering the area of the resin film in the vicinity of the electrode terminal of the element, including the insulation film. A hole is made in the area that reaches the surface of the film using a photoetching method,
forming a third opening; and plating the second metal film exposed in the third opening using the first metal film or the second metal film as one electrode. a step of forming a third metal film; and a step of removing the resin film and the first and second metal films; 1. A method for manufacturing a mounting body, comprising: forming a mounting body. 2. A step of pasting a first resin film on an insulating film having a first opening, a step of fixing an element to a first development part of the film, and a step of attaching a first resin film to an insulating film having a first opening, and a step of fixing an element to a first developed part of the film, and a step of attaching a first resin film to an insulating film having a first opening, and a step of fixing an element to a first developed part of the film, and a step of attaching a first resin film to an insulating film having a first opening. forming a second opening in a part of the upper resin film; depositing a metal film on the film;
A second resin is applied onto the metal film, and a second resin is applied onto the film, including a second opening near the electrode terminal of the element.
a step of forming holes in the region of the resin using the metal film as one electrode, a step of forming a metal layer in the region of the hole with a second resin by plating, and removing the exposed metal film, and forming an electrode lead made of the metal layer on the electrode terminal of the element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54030366A JPS5824012B2 (en) | 1979-03-14 | 1979-03-14 | Manufacturing method of mounting body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54030366A JPS5824012B2 (en) | 1979-03-14 | 1979-03-14 | Manufacturing method of mounting body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55121663A JPS55121663A (en) | 1980-09-18 |
| JPS5824012B2 true JPS5824012B2 (en) | 1983-05-18 |
Family
ID=12301858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54030366A Expired JPS5824012B2 (en) | 1979-03-14 | 1979-03-14 | Manufacturing method of mounting body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5824012B2 (en) |
-
1979
- 1979-03-14 JP JP54030366A patent/JPS5824012B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55121663A (en) | 1980-09-18 |
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