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JPS5824014B2 - Manufacturing method of mounting body - Google Patents
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JPS5824014B2 - Manufacturing method of mounting body - Google Patents

Manufacturing method of mounting body

Info

Publication number
JPS5824014B2
JPS5824014B2 JP54030761A JP3076179A JPS5824014B2 JP S5824014 B2 JPS5824014 B2 JP S5824014B2 JP 54030761 A JP54030761 A JP 54030761A JP 3076179 A JP3076179 A JP 3076179A JP S5824014 B2 JPS5824014 B2 JP S5824014B2
Authority
JP
Japan
Prior art keywords
resin film
film
electrode
lead
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54030761A
Other languages
Japanese (ja)
Other versions
JPS55123138A (en
Inventor
梶原孝生
畑田賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54030761A priority Critical patent/JPS5824014B2/en
Publication of JPS55123138A publication Critical patent/JPS55123138A/en
Publication of JPS5824014B2 publication Critical patent/JPS5824014B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は実装体の製造方法に関し、とくにIC。[Detailed description of the invention] The present invention relates to a method for manufacturing a package, particularly an IC.

LSI素子の電極端子から外部回路の電極端子への接続
を行なう部分の製造方法に関し、工程が簡単で低コスト
化したリード端子の形成方法を提供するものである。
The present invention relates to a method of manufacturing a portion that connects an electrode terminal of an LSI element to an electrode terminal of an external circuit, and provides a method of forming a lead terminal with simple steps and low cost.

IC,LSI等の素子上に形成された電極端子を外部回
路の電極端子へ電気的に導出する方法として、従来いく
つかの方法が開発されたが、最とも公知な方法として2
5〜37φμmのAu、AI等の極細線で、前記電極端
子同志を熱圧着法もしくは、超音波法によって接続する
、いわゆるワイヤボンディング技術がある。
Several methods have been developed to electrically lead out electrode terminals formed on elements such as ICs and LSIs to electrode terminals of external circuits, but the most well-known method is 2.
There is a so-called wire bonding technique in which the electrode terminals are connected to each other by a thermocompression bonding method or an ultrasonic method using ultrafine wires of Au, AI, etc. having a diameter of 5 to 37 φμm.

この方法では、電極端子数が少ない場合には、接続の信
頼性も高いが、近年のLSIの様に1素子内の機能数が
高まるにつれ、前記電極端子の数も40〜70端子にも
およびこの接続を行なうのに各端子にそれぞれ2回のボ
ンディングを必要とする。
In this method, the reliability of the connection is high when the number of electrode terminals is small, but as the number of functions in one element increases as in recent LSIs, the number of electrode terminals increases to 40 to 70 terminals. Two bondings are required for each terminal to make this connection.

すなわち素子の電極端子数が70端子を有する場合には
、その接続数は140個にも達し極めて多くなる。
That is, when the number of electrode terminals of an element is 70, the number of connections reaches 140, which is extremely large.

このために接続の信頼性を低下させ、かつこの接続工程
での低コスト化の実現は困難であった。
This lowers the reliability of the connection and makes it difficult to reduce the cost of this connection process.

又、外部回路への接続にあたっても、前記IC,LSI
素子を−たん、回路基板に固定する必要があり、かつ極
細線が彎曲した形で持ち上がるため、薄型、小型化した
パッケージの実現は著しるしく困難であった。
Also, when connecting to external circuits, the above-mentioned IC, LSI
It is extremely difficult to realize a thinner and smaller package because the element must be fixed to the circuit board and the ultra-thin wire is lifted up in a curved manner.

この様な欠点をなくするために、前記電極端子たとえば
70個の接続を一度に処理する、いわゆる極細線を用い
ないワイヤレス技術が実用化されてきた。
In order to eliminate such drawbacks, a wireless technology that does not use so-called ultra-fine wires has been put into practical use, which connects, for example, 70 electrode terminals at once.

例えばこのワイヤレス技術におけるビームリード方式は
、前記素子のシリコンのウェハプロセス段階で前記素子
の電極端子に矩形状の電極リードを形成するものである
For example, in the beam lead method in this wireless technology, a rectangular electrode lead is formed on the electrode terminal of the element at the silicon wafer processing stage of the element.

ところが、ビームリード方式では電極端子から伸びた電
極リードの形成されるシリコン面には素子を形成する事
が出来ない。
However, in the beam lead method, elements cannot be formed on the silicon surface where electrode leads extending from electrode terminals are formed.

このため1ウエハー内での素子が形成される有効面積は
、完全に全ウェハー内に素子が形成された場合に較べ5
0〜60%となりウェハーの利用効率が極めて悪くなる
Therefore, the effective area in which elements are formed within one wafer is 55% compared to when elements are formed completely within the entire wafer.
0 to 60%, resulting in extremely poor wafer utilization efficiency.

すなわち、リードの長さは通常0.7〜1.2酊である
から、1素子の周辺のこの長さにひってきするシリコン
領域は完全にリード形成のためにしか存在しない。
That is, since the length of the lead is usually 0.7 to 1.2 mm, the silicon region around this length around one element exists solely for the purpose of forming the lead.

したがって高価なシリコンウェハーを無駄に使用するば
かりか、電極リード形成の製造工程が複雑であるために
かえって、高価となり薄型化、小型化は実現されるが、
低コスト化の実現は田無であった。
Therefore, not only are expensive silicon wafers used in vain, but the manufacturing process for forming electrode leads is complicated, which makes it more expensive and thinner and smaller.
Tanashi was the one who realized the cost reduction.

又フィルムキャリヤ方式では、ウェハプロセス段階で素
子の電極端子上に金属突起物(通常バンプと呼ばれる)
を設け、この金属突起物にポリイミドフィルム上に形成
したSnメッキ処理したCu箔のリードを加圧加熱させ
、Au−8n共晶を形成する事によって、接続を行なう
ものであるが、この方式においては、金属突起物とリー
ドとの接続を行なわなければならないため、接続の箇所
数がワイヤボンジング法と同じくなるためかえって工程
が増え、かつ高価なフィルムを用いるため、量産性には
富むものの、かえって、高価となった。
In addition, in the film carrier method, metal protrusions (usually called bumps) are placed on the electrode terminals of the device during the wafer process stage.
The connection is made by applying pressure and heating to the Sn-plated Cu foil lead formed on the polyimide film on the metal protrusion to form an Au-8n eutectic. Since the metal protrusion and the lead must be connected, the number of connection points is the same as the wire bonding method, which increases the number of steps, and uses expensive film, so although it is suitable for mass production, On the contrary, it became more expensive.

本発明はこのような問題の検討にもとづき、表面に外部
接続用の電極端子が形成されている。
The present invention is based on consideration of such problems, and an electrode terminal for external connection is formed on the surface.

たとえばIC,LSI等の素子にメッキ法を用いて容易
かつ正確に外部取出接続用リード電極を形成する方法に
より、上記問題を解消できる方法を提供するものである
For example, the present invention provides a method that can solve the above problems by easily and accurately forming lead electrodes for external connection using a plating method on elements such as ICs and LSIs.

以下、本発明の一実施例を図面とともに説明する。An embodiment of the present invention will be described below with reference to the drawings.

第1図において、IC2LSI等の素子1は支持基板2
上で分割され(第1図a)、素子1は更に素子間隔を拡
げられる(第1図b)。
In FIG. 1, an element 1 such as an IC2LSI is connected to a supporting substrate 2.
The element 1 is then divided at the top (FIG. 1a), and the element spacing is further increased (FIG. 1b).

この素子1の間隔を拡げる方法としては、素子1のグイ
シングツ−等で切断した後、別の基板上に等間隔に並べ
ても良いし、ダイシングした素子を樹脂シート(商品名
:ミリメツクス)上に置き、加熱膨張させる事により、
素子間隔を自由に拡げる事が出来る。
To increase the spacing between the elements 1, you can cut the elements 1 with a dicing die or the like and then arrange them at equal intervals on another substrate, or place the diced elements on a resin sheet (product name: Millimex). , by heating and expanding,
The element spacing can be expanded freely.

ついで、第1の感光性樹脂3を全面に塗布し、素子1の
電極端子1′近傍のみを光蝕刻法によって4のごとく開
孔する。
Next, a first photosensitive resin 3 is applied to the entire surface, and holes as shown in 4 are made by photoetching only in the vicinity of the electrode terminal 1' of the element 1.

この状態を第1図Cに示すが、1の感光性樹脂3は素子
1の主表面の一部も覆う事が必要である。
This state is shown in FIG. 1C, and it is necessary that the photosensitive resin 1 also covers a part of the main surface of the element 1.

又、基板2に凹部を設けこの凹部の中に素子1を埋設H
固定させれば、第1の感光性樹脂3の膜厚は全体として
薄くする事が出来る。
Further, a recess is provided in the substrate 2, and the element 1 is buried in this recess.
If it is fixed, the film thickness of the first photosensitive resin 3 can be made thinner as a whole.

次に、全面に複数層からなる金属膜5を被着する(第1
図d)。
Next, a metal film 5 consisting of multiple layers is deposited on the entire surface (first
Figure d).

この複数層からなる金属膜5にはCr−Cu 、 Cr
−Cu −Au 、 Cr−Ni 、 Cr −Ag
、Cr−Au、Tn−Cu 、Tn−Au等が用いられ
る。
This metal film 5 consisting of multiple layers contains Cr-Cu, Cr
-Cu-Au, Cr-Ni, Cr-Ag
, Cr-Au, Tn-Cu, Tn-Au, etc. are used.

ここでCr、Tn膜は直接素子面に接し、素子との耐着
強度を得るための材料であり、Cu。
Here, the Cr and Tn films are materials that are in direct contact with the element surface to obtain adhesion strength with the element, and Cu.

Ag、Au 、Nuは導電性を高めるための材料である
Ag, Au, and Nu are materials for increasing conductivity.

金属膜5の上に第2の感光性樹脂膜6を塗布し、素子1
上の開孔部4を含み、素子平面上に細長い矩形状の領域
1を開孔する(第1図e)。
A second photosensitive resin film 6 is applied on the metal film 5, and the element 1 is
An elongated rectangular region 1 is opened on the device plane, including the upper opening 4 (FIG. 1e).

ついで複数層からなる金属膜5を一方のメッキ電極とし
て、矩形状の領域7にAu又はAg、Cu等をメッキに
より10〜50μmの厚さに形成する。
Next, using the metal film 5 consisting of multiple layers as one of the plating electrodes, Au, Ag, Cu, or the like is plated on the rectangular region 7 to a thickness of 10 to 50 μm.

第1図eにおいて、矩形状の領域7は樹脂膜6のパター
ンの存在によりお互いの素子間において、図に見られる
様に分離した状態で形成される。
In FIG. 1e, rectangular regions 7 are formed in a separated state between the elements due to the presence of the pattern of the resin film 6, as shown in the figure.

次に、第2の感光性樹脂6を除去し、露出したメッキ処
理されていない金属膜5をエツチング除去する、更に第
1の感光性樹脂3も除去すれば第1図fの状態を得る。
Next, the second photosensitive resin 6 is removed, the exposed unplated metal film 5 is etched away, and the first photosensitive resin 3 is also removed to obtain the state shown in FIG. 1(f).

すなわち、素子1の電極端子1′上に素子表面と平行で
かつ、外向きに、リード8が形成された素子を得る事が
出来る。
That is, it is possible to obtain an element in which the leads 8 are formed on the electrode terminals 1' of the element 1, parallel to the element surface and facing outward.

第2図は第1図fの斜視図である。FIG. 2 is a perspective view of FIG. 1f.

この様にして作られた素子を回路体に実装するには、基
板2の温度を上げて、基板2と素子1を接着している接
着剤を軟化せしめ、真空ピンセット等で取りはずし、リ
ード8と回路体のパターンとを位置合せし、後、リード
8と回路体のパターンとを熱圧着もしくは共晶・合金化
させる事によって実装する事が出来る。
To mount the element made in this way on a circuit body, the temperature of the board 2 is raised to soften the adhesive bonding the board 2 and the element 1, and the lead 8 is removed using vacuum tweezers or the like. The lead 8 and the pattern of the circuit body are aligned, and then the lead 8 and the pattern of the circuit body are bonded by thermocompression or eutectic/alloyed, thereby mounting can be carried out.

以上の方法では次に述べる効果が得られる。The above method provides the following effects.

■ 既に述べた如くフィルムキャリヤ方式は素子チップ
の取扱いがテープ搬送であるために量産性に富むものの
、ウェハ状態で形成された電極リードとを接続するため
のボンディング工程(通常ILBと呼ばれる)を必要と
する。
■ As mentioned above, the film carrier method is highly suitable for mass production because the element chips are handled by tape transport, but it requires a bonding process (usually called ILB) to connect the electrode leads formed on the wafer. shall be.

このボンディング工程によって熱(400〜500℃)
、圧力(30〜60g/パッド)がバンプおよび素子の
電極上に加わるためにAI電極端子が変形し、前記AI
電極端子上の一部を覆っているCVD5i02膜にクラ
ックが発生する。
This bonding process heats (400-500℃)
, the AI electrode terminal is deformed due to the pressure (30-60 g/pad) applied on the bump and the electrode of the device, and the AI
Cracks occur in the CVD5i02 film covering part of the electrode terminal.

このクラックによりAI電極端子が露出するため、この
部分よりAI電極端子の腐蝕性溶液が浸入し、A1電極
端子を溶解させてしまい、バンプの強度を低下させ、バ
ンプ間の接触抵抗を高くする等、信頼性を低下さす原因
となっていた。
Since the AI electrode terminal is exposed due to this crack, the corrosive solution of the AI electrode terminal enters from this part and dissolves the A1 electrode terminal, reducing the strength of the bump and increasing the contact resistance between the bumps. , which caused a decrease in reliability.

しかしながら本発明の製造方法による電極リードの形成
においては、電極リードの形成が、メッキ法で形成され
る(これは丁度フィルムキャリヤ方式のバンプ形成と同
一な手法で形成される)ため、フィルムキャリヤ方式の
如く、ボンディング工程であるILB工程を必要とせず
、かつCVDSiO2のクラックの発生がないから工数
の削減ならびに信頼性を高める事が出来るものである。
However, in forming electrode leads according to the manufacturing method of the present invention, the electrode leads are formed by a plating method (this is formed by the same method as the bump formation in the film carrier method). As shown in FIG. 2, there is no need for an ILB process, which is a bonding process, and no cracks occur in the CVDSiO2, so it is possible to reduce the number of man-hours and improve reliability.

更にフィルムキャリヤ方式における電極端子上へのバン
プ形成はミメツキ工程がウェハ状態で行なわれるために
、不良チップも含めて全チップの電極端子上にバンプが
形成される。
Furthermore, in forming bumps on electrode terminals in the film carrier method, since the milling process is performed in the wafer state, bumps are formed on the electrode terminals of all chips, including defective chips.

このために不良チップに形成されたバンプ(例えばAu
バンプ)はまったくの無鉄となる。
For this reason, bumps formed on defective chips (e.g. Au
Bump) is completely useless.

しかし、本発明においては、良品のみをあらかじめ選別
し、良品のチップのみに電極リードを形成出来る。
However, in the present invention, only good chips can be selected in advance and electrode leads can be formed only on good chips.

したがって材料の無駄を除く事が出来、製造コストが廉
価になる。
Therefore, waste of materials can be eliminated and manufacturing costs can be reduced.

■ 一方ビームリード方式はビームリードの分だけウェ
ハ面積を占有する必要があるからウェハ当りのチップの
収率は著じるしく悪くなるし、不良チップに対してもビ
ームリードの形成を行なうので、その分だけ材料が無駄
になり、製造コストが高くなる。
■ On the other hand, in the beam lead method, the wafer area must be occupied by the beam lead, so the yield of chips per wafer deteriorates significantly, and beam leads are also formed on defective chips. This wastes material and increases manufacturing costs.

本発明の製造方法においては、ウェッブのみを送別して
、製造プロセスに投入出来るため製造コストを廉価に出
来る。
In the manufacturing method of the present invention, since only the web can be sent separately and input into the manufacturing process, manufacturing costs can be reduced.

以上のように、本発明は従来のビームリード、フィルム
キャリヤ方式のもつ欠点を一掃し、新しい方式の製造方
法であって、低コストで信頼性の高い、薄型、小型化し
たリード端子を有する半導体装置等の電子回路素子の実
装体を得ることができ、高密度実装に大きく寄与するも
のである。
As described above, the present invention eliminates the drawbacks of the conventional beam lead and film carrier methods and provides a new manufacturing method for semiconductors having thinner and smaller lead terminals that are low cost and highly reliable. It is possible to obtain a packaged body of electronic circuit elements such as devices, which greatly contributes to high-density packaging.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a = fは本発明の一実施例にかかる実装体の
製造工程断面図、第2図は第1図fの状態の実装体の斜
視図である。 1・・・・・・素子、1′・・・・・・電極端子、2・
・・・・・支持基板、3.6・・・・・・感光性樹脂膜
、4,7・・・・・・開孔領域、5・・・・・・金属膜
、8・・・・・・リード。
FIG. 1a=f is a cross-sectional view of the manufacturing process of a mounting body according to an embodiment of the present invention, and FIG. 2 is a perspective view of the mounting body in the state shown in FIG. 1f. 1... Element, 1'... Electrode terminal, 2...
... Support substrate, 3.6 ... Photosensitive resin film, 4, 7 ... Opening region, 5 ... Metal film, 8 ... ...Lead.

Claims (1)

【特許請求の範囲】[Claims] 1 分割された素子を基板上に所定間隔をもって設置す
る工程と、前記素子表面を含む基板上に第1樹脂膜を塗
布し、前記素子の電極端子近傍の第1の樹脂膜に開孔部
を形成する工程と、前記樹脂膜ならびに開孔部上に金属
膜を被着せしめる工程と、前記金属膜上に第2の樹脂膜
を塗布し、前記素子の電極端子近傍の第1の樹脂膜の開
孔部を含み端子の周縁部方向に延びた前記第2の樹脂膜
の開孔部を形成する工程と、前記金属膜を一方のメッキ
用電極として、前記第2の樹脂膜の開孔部にメッキ金属
層を形成する工程と、前記第2樹脂膜を除去し、前記メ
ッキ金属層をマスクとして、露出している前記金属膜を
除去し、更に第1の樹脂膜を除去する工程とを備え、前
記素子の電極端子に接し前記メッキ金属層よりなるリー
ド端子を形成することを特徴とする実装体の製造方法。
1. A step of installing the divided elements on a substrate at predetermined intervals, applying a first resin film on the substrate including the surface of the element, and forming an opening in the first resin film near the electrode terminal of the element. a step of depositing a metal film on the resin film and the opening; and a step of applying a second resin film on the metal film, and depositing a second resin film on the first resin film near the electrode terminal of the element. forming an opening in the second resin film that includes the opening and extends toward the peripheral edge of the terminal; and using the metal film as one plating electrode, the opening in the second resin film a step of forming a plating metal layer on the metal layer, and a step of removing the second resin film, using the plating metal layer as a mask, removing the exposed metal film, and further removing the first resin film. A method for manufacturing a mounted body, comprising: forming a lead terminal made of the plated metal layer in contact with an electrode terminal of the element.
JP54030761A 1979-03-15 1979-03-15 Manufacturing method of mounting body Expired JPS5824014B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54030761A JPS5824014B2 (en) 1979-03-15 1979-03-15 Manufacturing method of mounting body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54030761A JPS5824014B2 (en) 1979-03-15 1979-03-15 Manufacturing method of mounting body

Publications (2)

Publication Number Publication Date
JPS55123138A JPS55123138A (en) 1980-09-22
JPS5824014B2 true JPS5824014B2 (en) 1983-05-18

Family

ID=12312661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54030761A Expired JPS5824014B2 (en) 1979-03-15 1979-03-15 Manufacturing method of mounting body

Country Status (1)

Country Link
JP (1) JPS5824014B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62203013A (en) * 1986-03-03 1987-09-07 Nippon Light Metal Co Ltd Method for measuring shape and dimension of external wall of existing building

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857481A (en) * 1989-03-14 1989-08-15 Motorola, Inc. Method of fabricating airbridge metal interconnects

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62203013A (en) * 1986-03-03 1987-09-07 Nippon Light Metal Co Ltd Method for measuring shape and dimension of external wall of existing building

Also Published As

Publication number Publication date
JPS55123138A (en) 1980-09-22

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