JPS5824019B2 - Manufacturing method of electronic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic circuit device in which electronic components are mounted in a high-density and thin manner, and by forming conductor wiring by a lift-off method, it is possible to improve productivity and reduce cost of electronic circuit mounting. It provides the body.

An example of a method for manufacturing a high-density electronic circuit package will be described with reference to FIG.

First, as shown in (a), an adhesive layer 2 is placed on a metal frame 1.
A thin resin film 3 made of polyimide or the like having the following properties is fixed.

Next, as shown in FIG. 3B, chemical etching is performed using the photoresist 4 as a mask to form holes 5 in the resin film 3.

Next, after removing the photoresist 4 as shown in (c),
The LSI chip 6 is fixed to the adhesive layer 2 with the electrodes 7 and the through holes 5 aligned, and the adhesive layer 2 on the electrodes 7 of the chip 6 is removed.

Next, as shown in (d), a metal layer 8 is formed by vapor deposition or the like.

Next, as shown in (e), a photoresist 4 is formed on the metal layer 8 which will later become a conductor wiring.

Finally, as shown in (f), using the photoresist 4 as a mask, unnecessary portions of the metal layer 8 are removed by chemical etching to form fine conductor wiring 9, and the photoresist 4 is removed.

The method described above has the following drawbacks because the conductor wiring is formed by chemical etching using a photoresist as a mask.

[1] Normally, the electrodes of IC and LSI are A[, so mask misalignment and IC, L
If pinholes occur in the photoresist on the electrodes of the SI chip, Al will be etched during chemical etching of the metal layer, resulting in poor electrical continuity, which will lower the yield and also lower reliability.

[2] Furthermore, in order to improve yield, highly accurate mask alignment is required, resulting in very poor workability.

Furthermore, since it is necessary to have a large overlapping portion of the conductor wiring with respect to the electrodes of ICs and LSIs, the conductor wiring density is low, and the design margin is small.

Furthermore, there is a lift-off method as a method for forming conductor wiring without chemically etching the metal layer, but this method requires a very thick photoresist, making it difficult to form fine wiring.

The present invention provides a method for easily forming fine wiring by using a method for reliably performing a photoresist lift-off method.

An embodiment according to the present invention will be described with reference to FIG.

1. First, as shown in FIG. 2A, a resin film 13 made of polyimide or the like having an adhesive layer 12 is fixed to a metal frame 11 made of iron, Ni, or the like.

Here, the thickness of each family is metal frame...100μ ~
500μ, adhesive layer: 2.5 to 10μ, resin film: approximately 12.5 to 25μ.

here. When FEP is used for the adhesive layer 12, since its melting point is 280°C, the adhesive strength can be increased by heating it to 280°C to 350°C and applying pressure.

Next, as shown in b, a photoresist pattern 14 is formed by photoetching technology.

Holes 15 are selectively formed in the resin film 13 by chemical etching.

Here, when polyimide is used for the resin film 13,
By etching with a 50% NaOH solution, holes 15 with a taper of 30° to 45° can be obtained.

The size of the hole 15 is determined by the size of the electrode of the LSI, etc., and is usually about 30 to 100 μm.

Next, as shown in FIG.
It sticks to 3.

Here, as in the case of fixing the metal frame, by heating to 280° C. to 350° C. and applying pressure, a strong adhesive strength can be obtained.

Next, as shown in d, a photoresist pattern 14 is placed on the resin film 13 in an area other than the conductor wiring area to be formed later.
′ is formed.

Next, as shown in e, the adhesive layer 12 (adhesive layer at the bottom of the hole 15) on the electrode of the LS 116 (nap) and later on the part of the metal frame 11 that will become the external lead is removed.

Here, if FEP is used for the adhesive layer 12, it is removed by plasma etching using 0□ gas or N2 gas.

In this step, the resist pattern 14', the adhesive layer 12. Etching progresses on the film 13 as well.

Here, when the resin film 13 is made of polyimide and the adhesive layer 12 is made of FEP, the etching rate of polyimide and FEP can be made faster than the etching rate of the photoresist 14' by appropriately selecting the plasma etching conditions.

Furthermore, by making the polyimide etching rate faster than the photoresist etching rate, the difference in level between the top surface of the photoresist 14' and the top surface of the resin film 13 without photoresist becomes large, making lift-off performed later very easy. Become.

That is, as shown in e, a stepped portion 13' is formed.

Next, as shown in f, Cr/Cu, Ni, AA
A metal layer 18 is formed by vapor deposition on the entire surface opposite to the LS 116.

Finally, as shown in g, the photoresist pattern 14
' is removed, and at the same time, the metal layer 18 thereon is removed to form a conductive wiring pattern 19.

In the method shown in FIG. 2, the adhesive layer on the electrodes of ICs, LSIs, etc. is removed after the photoresist used for lift-off is formed, so that the first effect is obtained.

[1] By appropriately selecting the plasma etching conditions when removing the adhesive layer, the step difference between the top surface of the photoresist and the top surface of the resin film without photoresist can be made larger than the thickness of the photoresist before plasma etching. , lift-off becomes much easier.

(2) Due to the reason in (1), the thickness of the photoresist used for lift-off can be made very thin.
It becomes possible to form fine wiring.

[$] Also, by introducing the lift-off method, which was difficult in the past, the chemical etching process of the metal layer becomes unnecessary, improving productivity and reducing costs.

(4) I due to the etching solution of the metal layer, which was a problem in the past
Etching of AA on C, LSI electrodes is eliminated, electrical conduction defects are no longer generated, and the yield is improved by 1. The accuracy of mask alignment during lift-off photoresist formation can be lowered, and metal frame Mask alignment is possible by just positioning based on the external shape, etc., and productivity is very high.

As described above, the present invention enables accurate and easy mounting of LSIs or other electronic components at high density, and greatly contributes to high-density electronic circuit mounting.

[Brief explanation of the drawing]

Figure 1 a = f is a process diagram of an example of electronic circuit mounting, Figure 2 a
"'-g is a process diagram of electronic circuit mounting according to an embodiment of the present invention. 11...Metal frame body, 12...Adhesive layer,
13...Resin film, 14'...Photoresist pattern. 15...hole, 16...LSI chip,
17... LSI electrode, 18... Metal layer, 19... Conductor wiring pattern.

Claims (1)

[Claims] 1. A step of fixing a resin film having an adhesive layer on the main surface to a metal frame, forming a hole in the resin film, and aligning the reading tag with the electrode of the electronic component. A step of fixing the electronic component to the adhesive layer surface of the resin film, a step of forming a photoresist on the resin film in an area other than the conductor wiring to be formed later, and a step of removing the adhesive layer on the electrodes and unnecessary parts of the electronic component. A step of forming a metal layer on the opposite side to which the electronic component and metal frame are fixed, and removing the photoresist formed on the resin film,
A method for manufacturing an electronic circuit device, comprising the step of forming a conductor wiring made of the metal layer that electrically connects the electrode of the electronic component or the like through a hole formed in the resin film. 2. The method of manufacturing an electronic circuit device according to claim 1, wherein the adhesive layer is removed by dry etching.