JPS6342878B2 - - Google Patents
Info
- Publication number
- JPS6342878B2 JPS6342878B2 JP55094493A JP9449380A JPS6342878B2 JP S6342878 B2 JPS6342878 B2 JP S6342878B2 JP 55094493 A JP55094493 A JP 55094493A JP 9449380 A JP9449380 A JP 9449380A JP S6342878 B2 JPS6342878 B2 JP S6342878B2
- Authority
- JP
- Japan
- Prior art keywords
- metal frame
- resin film
- fixed
- resin
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は電子回路装置の製造方法に関し、IC、
LSIチツプ、チツプ抵抗、チツプコンデンサ等の
電子部品を、樹脂フイルムと金属枠体により形成
された基板に実装した電子回路装置に関するもの
であり、金属枠体を磁石あるいは真空吸着等によ
り保持した後に、電子部品の樹脂封止を行うこと
により、基板の平坦化を行い、微細配線の形成を
容易にしたものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an electronic circuit device, including an IC,
This relates to an electronic circuit device in which electronic components such as LSI chips, chip resistors, and chip capacitors are mounted on a board formed of a resin film and a metal frame.After the metal frame is held by magnets or vacuum suction, By sealing electronic components with resin, the substrate is flattened and fine wiring can be easily formed.
高密度な電子回路実装体の従来の一例を第1図
と共に説明する。まず始めに、ニツケル等の金属
枠体1に熱可ソ性の接着層3を有した樹脂フイル
ム2を固着する。次に、後に固着する電子部品た
とえばチツプコンデンサ5の電極5′と一致する
部分の樹脂フイルム2に貫通孔4を形成する。次
に、貫通孔4とチツプコンデンサ5の電極5′と
を一致させて、チツプコンデンサ5を接着層3に
固着する。この時、熱圧着により固着する為、樹
脂フイルム2にのびが生じ、チツプコンデンサ5
は金属枠体1より突出する。次に、チツプコンデ
ンサ5を、エポキシ樹脂あるいはシリコン樹脂等
の樹脂11により封止する。最後に、チツプコン
デンサ5の電極5′上の接着層3をドライエツチ
ング等により除去した後、樹脂フイルム2上に
Cr/Cu、Al等の金属膜を形成し、フオトエツチ
ングにより導体配線6を形成する。 A conventional example of a high-density electronic circuit package will be described with reference to FIG. First, a resin film 2 having a thermoplastic adhesive layer 3 is fixed to a metal frame 1 made of nickel or the like. Next, a through hole 4 is formed in the resin film 2 at a portion corresponding to an electrode 5' of an electronic component such as a chip capacitor 5 to be fixed later. Next, the chip capacitor 5 is fixed to the adhesive layer 3 by aligning the through hole 4 with the electrode 5' of the chip capacitor 5. At this time, since the resin film 2 is fixed by thermocompression bonding, the resin film 2 is stretched, and the chip capacitor 5
protrudes from the metal frame 1. Next, the chip capacitor 5 is sealed with a resin 11 such as epoxy resin or silicone resin. Finally, after removing the adhesive layer 3 on the electrode 5' of the chip capacitor 5 by dry etching etc., the adhesive layer 3 is removed on the resin film 2.
A metal film of Cr/Cu, Al, etc. is formed, and conductive wiring 6 is formed by photoetching.
本従来例では、チツプコンデンサ等の電子部品
が金属枠体より突出した状態で、樹脂封止を行つ
ている為に次に示す欠点がある。 In this conventional example, since electronic components such as chip capacitors are sealed with resin while protruding from the metal frame, there are the following drawbacks.
(1) 導体配線形成時のフエトエツチ工程におい
て、レジストを回転塗布した場合、突出してい
る部分は、レジストが付かない。(1) When resist is spin-coated during the fet-etch process when forming conductor wiring, the resist will not stick to the protruding parts.
(2) (1)の理由により、レジスト膜厚を厚くする必
要がある為、解像度が低下し、微細な配線の形
成が困難になり、高密度化が図れない。(2) Due to the reason in (1), it is necessary to increase the thickness of the resist film, which reduces the resolution and makes it difficult to form fine wiring, making it impossible to achieve high density.
(3) 密着露光を行う場合、第1図のギヤツプ7に
より、レジストパターンが太る為、導体配線8
と9は、エツチングにより分離されず、エツチ
ング残りにより生じた導体層10により電気的
に短絡する。(3) When performing close exposure, the resist pattern becomes thicker due to the gap 7 in Figure 1, so the conductor wiring 8
and 9 are not separated by etching and are electrically short-circuited by the conductor layer 10 caused by the etching residue.
本発明はかかる問題に鑑みてなされたもので、
本発明の一実施例を第2図と共に説明する。 The present invention was made in view of such problems,
An embodiment of the present invention will be described with reference to FIG.
まず初めに、第2図aに示す如く、ニツケル、
コバール、ステンレス等の金属枠体21に、熱可
塑性の接着層23を有した樹脂フイルム22を固
着する。金属枠体21の厚みは通常100〜200μ程
度である。本実施例では、接着層23はFEP、
樹脂フイルム22はポリイミドの場合について述
べる。通常それぞれの厚みは、FEP23は2.5〜
12.5μ、ポリイミド22は7.5〜25μ程度である。
またFEPの融点は、290℃程度である為、280℃
〜340℃程度に加熱し加圧することにより、金属
枠体21と強固な固着を得る。 First of all, as shown in Figure 2a, nickel,
A resin film 22 having a thermoplastic adhesive layer 23 is fixed to a metal frame 21 made of Kovar, stainless steel, or the like. The thickness of the metal frame 21 is usually about 100 to 200 μm. In this embodiment, the adhesive layer 23 is FEP,
The case where the resin film 22 is made of polyimide will be described. Usually the thickness of each is 2.5~2.5 for FEP23
12.5μ, and polyimide 22 has a thickness of about 7.5 to 25μ.
Also, the melting point of FEP is around 290℃, so 280℃
By heating to about 340° C. and applying pressure, a strong adhesion to the metal frame 21 is obtained.
次に、第2図bに示す如く、フオトレジストを
マスクとし、ケミカルエツチングあるいはドライ
エツチング等により、ポリイミド22に貫通孔2
4を形成する。ここで、ケミカルエツチングを行
う場合は、NaOH溶液により行う。またドライ
エツチングの場合は、O2ガス、N2ガス等により
行う。貫通孔24の大きさは、通常60〜100μ□
程度である。 Next, as shown in FIG. 2b, using a photoresist as a mask, through holes 2 are formed in the polyimide 22 by chemical etching or dry etching.
form 4. When chemical etching is performed here, a NaOH solution is used. In the case of dry etching, O 2 gas, N 2 gas, etc. are used. The size of the through hole 24 is usually 60 to 100 μ□
That's about it.
次に、第2図cに示す如く、チツプコンデンサ
25の電極25′と貫通孔24とを一致させて、
チツプコンデンサ25をFEP23を接着剤とし、
ポリイミドフイルム22に固着する。この時も、
金属枠体21の固着時と同様280℃〜340℃に加熱
し、加圧することにより強固な固着が得られる。
この時熱圧着により固着することと、ポリイミド
フイルム22が非常に薄いこと等の理由により、
ポリイミドフイルム22に伸びが生じ、チツプコ
ンデンサ25は金属枠体21より突出する。 Next, as shown in FIG. 2c, the electrode 25' of the chip capacitor 25 and the through hole 24 are aligned,
Chip capacitor 25 with FEP23 as adhesive,
It is fixed to the polyimide film 22. At this time too,
As in the case of fixing the metal frame 21, strong fixation can be obtained by heating to 280° C. to 340° C. and applying pressure.
At this time, due to the fact that it is fixed by thermocompression bonding and the polyimide film 22 is very thin,
The polyimide film 22 stretches, and the chip capacitor 25 protrudes from the metal frame 21.
次に、第2図dに示す如く、磁石32にポリイ
ミドフイルム22を介して、金属枠体21を保持
する。この時、金属枠体21はニツケル等の磁性
体を用いる。また、ポリイミドフイルム22は非
常に薄い為、磁石32が金属枠体21を保持する
力については、ポリイミドフイルム22の影響は
ほとんどない。 Next, as shown in FIG. 2d, the metal frame 21 is held by the magnet 32 with the polyimide film 22 interposed therebetween. At this time, the metal frame 21 is made of a magnetic material such as nickel. Furthermore, since the polyimide film 22 is very thin, the polyimide film 22 has almost no effect on the force with which the magnet 32 holds the metal frame 21 .
その後、エポキシ樹脂あるいはシリコン樹脂3
1等により、チツプコンデンサ25を樹脂封止す
る。ここで、金属枠体21は磁石32によつて保
持されしかも樹脂フイルム22非常に薄く柔軟性
がある為金属枠体21とチツプコンデンサ25は
平坦な表面となる。すなわち、フイルム22の表
面が、フイルム22と枠体の固着面より突出して
いない平坦な状態を得ることができる。 After that, epoxy resin or silicone resin 3
1 or the like, the chip capacitor 25 is sealed with resin. Here, the metal frame 21 is held by a magnet 32, and since the resin film 22 is very thin and flexible, the metal frame 21 and the chip capacitor 25 have flat surfaces. That is, it is possible to obtain a flat state in which the surface of the film 22 does not protrude from the surface to which the film 22 and the frame are fixed.
なお、金属枠体21が磁性体でない場合は、第
2図eに示すように、真空吸着台23にフイル
ム、枠体21を設置し、吸着孔34から真空吸引
して金属枠体21を真空吸着台33に保持するこ
とにより、金属枠体21とチツプコンデンサ25
表面をほぼ完全に平坦とすることができる。さら
に、磁石、真空吸引に代えて、機械的加圧にて平
坦な状態を得てもよい。 In addition, if the metal frame 21 is not a magnetic material, as shown in FIG. By holding the suction table 33, the metal frame 21 and the chip capacitor 25 are
The surface can be made almost completely flat. Furthermore, instead of using a magnet or vacuum suction, mechanical pressure may be used to obtain a flat state.
最後に、チツプコンデンサ25の電極25′上
のFEPをO2ガスあるいはN2ガスによるドライエ
ツチングより除去する。その後、ポリイミドフイ
ルム22上に蒸着、メツキ等の方法により、
Cr/Cu、Ni等の金属膜を形成し、第2図fのご
とくフオトエツチングにより導体配線26,2
8,29を形成する。導体配線26,28,29
にCr/Cuの二層膜を用いた場合、通常それぞれ
の厚みは、Cr:0.1μ、Cu:3μ程度である。また、
エツチングにおいて、Crは塩酸によるケミカル
エツチングあるいは四塩炭素等によるドライエツ
チング、Cuは塩化第二鉄溶液、塩化第二銅溶液
等によるケミカルエツチングにより行う。 Finally, the FEP on the electrode 25' of the chip capacitor 25 is removed by dry etching using O 2 gas or N 2 gas. Thereafter, by a method such as vapor deposition or plating on the polyimide film 22,
A metal film such as Cr/Cu, Ni, etc. is formed, and conductor wirings 26, 2 are formed by photoetching as shown in Fig. 2f.
Form 8, 29. Conductor wiring 26, 28, 29
When a two-layer film of Cr/Cu is used, the respective thicknesses are usually about 0.1μ for Cr and 3μ for Cu. Also,
Etching is performed for Cr by chemical etching using hydrochloric acid or dry etching using carbon tetrachloride, etc., and for Cu by chemical etching using a ferric chloride solution, cupric chloride solution, etc.
また本実施例では、電子部品を樹脂封止した後
に導体配線を形成しているが、導体配線を形成し
た後に、電子部品を樹脂封止してもよい。なお電
子部品としてはチツプコンデンサ以外のIC、LSI
チツプ、抵抗等であつてもよいことは当然であ
る。 Further, in this embodiment, the conductor wiring is formed after the electronic component is sealed with resin, but the electronic component may be sealed with resin after the conductor wiring is formed. Electronic components include ICs and LSIs other than chip capacitors.
Of course, it may also be a chip, a resistor, etc.
以上のように、本発明ではチツプコンデンサ等
の電子部品と金属枠体表面をほぼ平坦にした状態
で、電子部品の樹脂封止を行つている為、次に示
す効果がある。 As described above, in the present invention, since the electronic component such as a chip capacitor and the surface of the metal frame are made substantially flat, the electronic component is sealed with resin, so that the following effects can be obtained.
(1) 樹脂フイルム面が平坦になる為、導体配線形
成時のレジスト塗布工程において、非常に均一
な膜厚が得られ、従来のようにレジストの付か
ない部分がなくなり、膜厚を非常に薄くするこ
とができる。(1) Since the resin film surface is flat, a very uniform film thickness can be obtained during the resist application process when forming conductor wiring, and there are no areas where resist does not stick as in the conventional method, making the film extremely thin. can do.
(2) (1)の理由により、レジストの解像度が非常に
向上する為、微細な導体配線を形成することが
でき、高密化が容易に行える。(2) Due to the reason in (1), the resolution of the resist is greatly improved, so fine conductor wiring can be formed and high density can be easily achieved.
(3) 密着露光の場合、従来問題であつたギヤツプ
が生じない為、レジストパターンはマスクパタ
ーンに忠実に形成でき、第2図fに示す導体配
線38と39間は完全に独立し、電気的短絡不
良は発生しない。(3) In the case of contact exposure, the gap that was a problem in the past does not occur, so the resist pattern can be formed faithfully to the mask pattern, and the conductor wirings 38 and 39 shown in FIG. No short circuit defects occur.
以上のように、本発明によれば高精度に正確に
高密度実装を行うことが可能となる。 As described above, according to the present invention, it is possible to accurately and accurately perform high-density mounting.
第1図は従来の電子部品実装体の断面図、第2
図a〜fは本発明の一実施例にかかる電子回路実
装体の製造工程図である。
21……金属枠体、22……樹脂フイルム、2
3……接着層、24……貫通孔、25……チツプ
コンデンサ、25′……チツプコンデンサの電極、
26,28,29……導体配線、31……封止用
樹脂、32……磁石、33……真空吸着台。
Figure 1 is a cross-sectional view of a conventional electronic component mounting body;
Figures a to f are manufacturing process diagrams of an electronic circuit package according to an embodiment of the present invention. 21...Metal frame body, 22...Resin film, 2
3... Adhesive layer, 24... Through hole, 25... Chip capacitor, 25'... Chip capacitor electrode,
26, 28, 29... Conductor wiring, 31... Sealing resin, 32... Magnet, 33... Vacuum adsorption stand.
Claims (1)
と、前記樹脂フイルムに微細孔を形成する工程
と、前記樹脂フイルムの金属枠体が固着された面
に電子部品を固着する工程と、前記樹脂フイルム
の金属枠体が固着された逆の面が、前記金属枠体
上の樹脂フイルム面より突出している部分がない
状態で、前記樹脂フイルムの金属枠体が固着され
た面に前記電子部品を覆うように樹脂層を形成す
る工程と、前記樹脂フイルムの金属枠体が固着さ
れた逆の面に導体配線を形成し前記微細孔を介し
て、前記導体配線と前記電子部品の電極及び金属
枠体を電気的に接続する工程とを備えたことを特
徴とする電子回路装置の製造方法。 2 樹脂フイルムの金属枠体が固着された逆の面
が、金属枠体上の樹脂フイルム面より突出してい
る部分がない状態を、磁石により形成することを
特徴とする特許請求の範囲第1項に記載の電子回
路装置の製造方法。 3 樹脂フイルムの金属枠体が固着された逆の面
が、金属枠体上の樹脂フイルム面より突出してい
る部分がない状態を、真空吸着により形成するこ
とを特徴とする特許請求の範囲第1項に記載の電
子回路装置の製造方法。 4 樹脂フイルムの金属枠体が固着された逆の面
が、金属枠体上の樹脂フイルム面より突出してい
る部分がない状態を、機械的加圧により形成する
ことを特徴とする特許請求の範囲第1項に記載の
電子回路装置の製造方法。[Claims] 1. A step of fixing a resin film to a thin metal frame, a step of forming micropores in the resin film, and a step of fixing an electronic component to the surface of the resin film to which the metal frame is fixed. step, and the surface of the resin film to which the metal frame is fixed, with the opposite side of the resin film to which the metal frame is fixed, with no part protruding from the resin film surface on the metal frame; forming a resin layer to cover the electronic component; forming a conductor wiring on the opposite side of the resin film to which the metal frame is fixed; and connecting the conductor wiring and the electronic component through the micro holes; A method of manufacturing an electronic circuit device, comprising the step of electrically connecting the electrode and the metal frame. 2. Claim 1, characterized in that the opposite side of the resin film to which the metal frame is fixed has no part protruding from the surface of the resin film on the metal frame using a magnet. A method for manufacturing an electronic circuit device according to. 3. Claim 1, characterized in that the opposite side of the resin film to which the metal frame is fixed has no part protruding from the surface of the resin film on the metal frame by vacuum suction. A method for manufacturing an electronic circuit device according to paragraph 1. 4. Claims characterized in that the opposite side of the resin film to which the metal frame is fixed has no part protruding from the surface of the resin film on the metal frame by mechanical pressure. A method for manufacturing an electronic circuit device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9449380A JPS5718349A (en) | 1980-07-09 | 1980-07-09 | Manufacture of electronic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9449380A JPS5718349A (en) | 1980-07-09 | 1980-07-09 | Manufacture of electronic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5718349A JPS5718349A (en) | 1982-01-30 |
| JPS6342878B2 true JPS6342878B2 (en) | 1988-08-25 |
Family
ID=14111816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9449380A Granted JPS5718349A (en) | 1980-07-09 | 1980-07-09 | Manufacture of electronic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5718349A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6164187A (en) * | 1984-09-06 | 1986-04-02 | 松下電器産業株式会社 | Method of producing electronic circuit device |
| JPH0697710B2 (en) * | 1990-10-22 | 1994-11-30 | 国際電気株式会社 | Electronic component mounting method |
-
1980
- 1980-07-09 JP JP9449380A patent/JPS5718349A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5718349A (en) | 1982-01-30 |
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