JPS5826206B2 - Tuning display control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning display control circuit, such as FM, AM
In a receiver, when the tuning state, tuning direction, etc. are displayed using a plurality of optical display elements, the present invention relates to something that controls the display form of the display elements.

Generally, FM and AM receivers are provided with a tuning indicator and a signal strength meter (S meter) in order to obtain an optimal tuning state when receiving broadcasts.

Separate indicators are sometimes used for these tuning indicators and signal strength meters, but recently, one indicator is often used in common to simplify the display, secure space, etc.

Conventionally, this type of indicator has been used with a pointer, but this type of indicator was originally used to check the state of synchronization, not the measurement value. It does not have to be a pointer-based indicating instrument.

Therefore, a plurality of display elements such as light emitting diodes (LE
D) A method of displaying the tuning state and signal strength by changing the display format has been proposed.

If the above-mentioned display is performed using this type of display element, it will be extremely easy to confirm it, and as a result, it will be easy to ensure optimal tuning, but unlike conventional indicating instruments, special considerations are required. It is something.

An object of the present invention is to provide a tuning display control circuit suitable for achieving reliable display form control of a plurality of display elements and ensuring an optimal tuning state.

The present invention includes a clock signal generator that generates a clock signal, a frequency divider that divides the output clock signal of the clock signal generator to generate a predetermined number of code pulses, and an S-curve signal input and a reference voltage. Detect the synchronized state by comparing
A tuning detection circuit that outputs a tuning point signal when the tuning state is within a tuning point range near the tuning point, and outputs a tuning direction signal when it is out of the tuning point range; and a tuning detection circuit that detects the tuning state. a control means for setting a tuning direction control range, and outputting a tuning direction signal of the tuning detection circuit within this range; a decoder that outputs a tuning direction display control signal that is inputted and sequentially changed in response to a tuning direction signal, and a logic circuit that outputs an output of the decoder or an output tuning point signal of the tuning detection circuit; The present invention is characterized in that the tuned display elements configured as a set of display elements are controlled in different display forms depending on the tuned state.

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

FIG. 1 shows a preferred embodiment of the tuning display control circuit of the present invention.

In the figure, a display element 2 configured of a plurality of elements as one set.
L22. ...2N are arranged and installed on the front panel surface of an FM/AM receiver (not shown), and the display format can be changed to display the level when receiving an AM signal, or to display the level when receiving an FM signal.
In the case of signal reception, it is also used to display the tuning state and tuning direction.

Since two types of display are possible in this way, the area occupied by the front panel surface can be reduced.

A light emitting diode, a fluorescent display tube, or the like is used for the display elements 21, 22.2N.

According to such a display element, the display can be performed using constant colored light, making it easy to confirm the display, and since the display element itself is small, it can be arranged compactly on the front panel surface.

For example, display element 2L22. ...2N is composed of five elements.

These display elements 21, 22 . . . . The control of the display form of 2N is performed by the tuning display control circuit 4, which is a characteristic part of the present invention.
The control output is performed at the output terminal 6L62. ...
6N to each display element 21.22°...2N.

In order to control the display form, this tuning display control circuit 4 includes an AM level display control □□ circuit 8 that takes charge of level display control when receiving an AM signal, and a tuning display control circuit 8 that controls the level display when receiving an FM signal. An FM tuning display control circuit 10 is provided which is responsible for state and tuning direction control.

The former AM level display control circuit 8 sequentially outputs high level outputs corresponding to the AM signal human power level supplied to the input terminal 12 to the output terminals 14L142. ...This is a circuit that occurs at 14N.

Further, the latter FM tuning display control circuit 10 has an input terminal 1
The tuning state is detected based on the comparison voltage and S curve signal input applied to 6A and 16B, the FM signal input applied to the input terminal 18, and the muting signal input applied to the input terminal 20. If it is within the tuning point range near the tuning point, a tuning point signal is output, and if it is out of the tuning point range and within a predetermined tuning range, a tuning direction signal is output from the output terminals 221, 222°...22N. This is a circuit that does this.

Note that the former circuit 8 uses the output terminal 141 when there is no AM signal input, and the latter circuit 10 uses the output terminal 141 when there is no FM signal input.
゜142,...14N, 221.222. ...22
The output voltage appearing at N will be at a low level.

And output terminal 141°142.1 of each circuit 8, 10
4N...221,222. ...22N, each output is sent to the drive circuit 261.262..22N via an OR circuit 24L242°...24N. . . 26N, and is input to drive circuits 261, 262 . ...26N to output terminals 61, 62. . . 6N, a display control output is generated and supplied to each display element 21 , 22 , . . . 2N.

With the above configuration, when receiving an AM signal, the number of display elements 2L22. ...
If you feed 2N, if it is composed of 5 pieces, it will be lit in the range of 0 to 5 pieces.

In addition, in the case of FM signal reception, if the tuning state is within the tuning point range, each display element 21, 22 . °...2N is displayed on the entire surface, and if the tuning state is out of the tuning point range but still within the predetermined range, each button will indicate the tuning direction corresponding to the direction of the tuning deviation. Display element 2L22. . . . At least one of 2N is selected and sequentially lit and displayed.

The so-called display format is a running type or a display transition type in which the tuning direction is instructed.

The tuning display control circuit 4 for obtaining the above-mentioned effects is composed of one integrated circuit, and as a result, the circuit can be made compact, operation reliability is ensured, and it can be provided at low cost. be.

Next, FIG. 2 shows a specific configuration of the AM level display control circuit 8.

In the figure, a power supply terminal 27 is a terminal to which a power supply voltage VCC is applied from a stabilized power supply (not shown), and dividing resistors 281, 282, . ...28
A reference voltage setting circuit is constituted by N and 28 N o.

The reference voltage set by the reference voltage setting circuit 30 and the AM signal output applied to the input terminal 12 are determined by a comparator 321.
, 322. ...32N, each comparator 321,
322. . . . The output voltage that gradually increases from 32N to a high level corresponding to the AM signal level is output to the output terminal 141,
142. ...taken out from 14N.

Since the AM level display control circuit 8 is configured as described above, a control output corresponding to an extremely reliable AM signal level can be obtained, and each display element 21, 22, . ...2N
The level display control is accurate and stable.

Next, FIG. 3 shows a specific configuration of the FM tuning display control circuit 10.

In the figure, the tuning detection circuit 34 that detects the tuning state is S
Comprised of a curve comparison circuit, the comparison voltage and S curve signal input to input terminals 16A and 16B, and the input terminal 20
This circuit generates the tuning point signal or the display direction signal from the muting signal input to the output terminal 361.
The latter signals are respectively output.

The frequency divider 38 is a circuit that counts the output clock signal of the clock signal generator 40, converts it into a binary code, and outputs it, and outputs the output terminals 421, 422 . . . . The code pulse appearing at 42N is input to the decoder 44.

This decoder 44 has output terminals 421, 422, . . .
This circuit converts the code pulse from 2N into a high level display direction control signal in the direction determined by the output display direction signal of the tuning detection circuit 34, and this display direction control signal is sent to the output terminals 461, 462°...46N. It is output from

The display direction control signal appearing at the output terminals 461, 462, . . . , 46N is the output terminal 3 of the tuning detection circuit 34.
OR circuit 481, 4 along with the tuning point signal appearing at 61
82°...It is input to 48N.

The FM signal input to the input terminal 18 is compared with a reference voltage set by a reference power source 50 by a voltage comparator 52, and the comparison output is the OR circuit 48L482.・・・
・With output of 48N, N■ circuit 54L542. ...
54N, output terminals 221, 222,...
A tuning display control output is generated from 22N.

The operating principle of the FM tuning display control circuit 10 described above will be explained with reference to FIGS. 4A, B, and C.

FIG. 4A shows an S-curve signal, which is inputted to the input terminals 16A and 16B of the tuning detection circuit 34 together with the comparison voltage VREF.

Detection of the tuning point range aa' that includes the tuning point O as the center is performed by detecting the difference (Vsc
-VREF) is within the range of the reference setting level ±■1.

In this case, since the ranges of points b and b' are also the same, it is necessary to set the condition that the muting shown in B is canceled, and in this embodiment, the level of muting human power is set to the standard setting level v3. The judgment is made based on the following conditions.

Further, the tuning display direction is determined by the comparison voltage V RE as described above.
It is determined by comparing F and the S curve signal voltage Vsc.

For example, when Vsc>VREF, the tuning direction shifts to the direction of increasing frequency, and when Vsc<VREF, the tuning direction shifts to the opposite direction.

The tuning direction display range is such that when the FM signal level shown in B exceeds the reference setting level 2, the tuning direction display is executed.

This operation is performed by voltage comparator 52.

Putting the following together, E shown in the lower part of Figure 4C is the tuning point range where the display element is fully lit, and F excluding the range E.
The range indicated by is the transition display range for displaying the tuning direction.

Further, arrows D and H indicate the tuning direction.

In principle, the same display format can be achieved even if either the FM signal or the muting signal is omitted, but the difference is that the transition display range is narrower.

Next, the display elements 21, 22 . ...2N display format will be explained with reference to FIGS. 5 and 6.

The display form shown in FIGS. 5 and 6 has five display elements 21.
．． 22. ...25 is used.

The display shown in FIG. 5 is when an FM signal is received, and A is a case where the tuning is out of the range shown by F in FIG. 4, and each element 21, 22, . ...25 is off.

When the tuning state is shifted to receive a certain broadcasting station and the range shown by F in Figure 4C is reached, the tuning direction is displayed and B
As shown in F, five display elements 2L22. ...
One of the 25 is selectively selected and its display shifts sequentially.
That is, the tuning direction is displayed by the lighting moving from the display element 21 toward the display element 25.

Then, when the tuning reaches the range shown by E in Figure 4C,
As shown in FIG. 5G, five display elements 21, 22.・・・
・All 25 are lit to indicate that they are within the tuning point range.

Further, when the tuning is shifted toward a higher frequency, the display form shifts from the display element 25 toward the display element 21, and the tuning direction is displayed.

In this way, since the tuning state and its direction during FM reception are clearly displayed optically, it becomes easy to check and the optimum tuning state can be ensured extremely efficiently.

The display shown in FIG. 6 shows a display form according to the AM signal strength during AM reception, and the display elements 21, 22, . . .
The intensity level is confirmed by the number of lighted lights of 2N.

The display formats shown in FIGS. 5 and 6 described above are automatically selected when each AM or FM signal is received, without using any switching means such as a switch.
The only operation required to ensure optimal reception conditions is the tuning operation, which is extremely simplified.

Next, FIG. 7 shows a specific embodiment of the tuning display control circuit 4.

In FIG. 7, the same parts as the circuits shown in FIGS. 1 to 3 are given the same reference numerals, and the explanation thereof will be simplified.

In FIG. 7, the tuning detection circuit 34 includes a constant current circuit 56
2,564,566.568, comparator 570.572,
574, transistor 576°578.580,582
, 584, diode 586, 588, and resistor 590
,592.594゜596.598,600,602,
It is composed of 604,606°608.610.

A reference voltage setting circuit 620 is configured with the resistors 590゜592, 594, 596, and 598 to set the comparison voltage. Each is set.

A resistor 590 is an external variable resistor connected to external terminals 612 and 613, and is used for fine adjustment of the tuning point display range, thereby achieving high display accuracy.

The transistor 580°582.584 is the comparator 570,
Constant current circuit 566 is a switching transistor that switches depending on the output (H, L level) of 572 and 574.
A collector is connected to the output terminal side of 568 to form a wired OR circuit.

The output of the constant voltage circuit 616 is supplied to the constant current circuits 566 and 568 via the control transistor 614, and a constant current circuit 617 is inserted between the pace collectors of the transistor 612 to stabilize the operation. It is being

The constant voltage circuit 616 is a circuit that maintains a constant voltage output even if the voltage CC applied to the power supply terminal 618 fluctuates.
It is composed of transistors 622, 623, 624, 626, a Zener diode 628, and resistors 630, 632.

The muting detection circuit 634 is a circuit that detects the muting signal level, and includes a transistor 636 and a resistor 63.
The collector of the transistor 636 is connected to the output side of the constant current circuit 566 to form a wired OR circuit.

The tuning point signal output of the constant current circuit 566 is input to OR circuits 241, 242, . . . 245.

Therefore, the output of the constant current circuit 566 is supplied to the OR circuits 241, 242, .

A capacitor 644 and a resistor 646 are connected to the clock signal generator 40 via an external terminal 642, and the generation period of the clock signal generated is adjusted by the values of the capacitor 644 and resistor 646.

This clock signal generator 40 is driven by the constant voltage circuit 616, but its operation is controlled by the FM signal level detection circuit 64.
Controlled by 8 switching outputs.

Note that this output also controls the switching of the transistor 614.

The FM signal level detection circuit 648 is connected to the voltage comparator 52.
, transistors 652, 654 and resistors 656, 658
, 660, 662, 664, 666, and resistor 6
56 and 658 constitute a reference voltage setting power supply 50 that sets the reference setting level (2).

Transistors 652 and 654 are transistors that are switched by the output of the comparator 650, and the transistor 65
The operation of the clock signal generating circuit 40 is ensured by switching off the transistor 65.
4 by switching off the transistor 6.
14 operation is ensured.

Therefore, when the FM signal level becomes below the reference setting level 2 shown in FIG. At the same time, when the transistor 614 is on, the power supply to the constant current circuits 566 and 568 is stopped, and the power supply to the decoder 44 is also stopped.

Since stopping the power supply to the decoder 44 is controlled by the FM signal level, it is essentially an AND circuit 541 shown in FIG.
, 542...545 have been achieved.

The decoder 44 consists of eight AND circuits 668, 670°67
2.674, 676.678, 680, 682 degrees, and the tuning direction signal output of the constant current circuit 568 is input to this decoder 44, and the inverter 684
, and the code pulse of the frequency divider 38 is also input.

The frequency divider 38 consists of three flip-flop circuits 686°68
8.690 and an AND circuit 692.

Five display elements 2L22. ...Since hexadecimal counter output is used for 25, it will turn on once, pause once, and then turn on again, and there will be an interval between one display and the next display. Clarity is being sought.

And output terminals 61, 62 . . . 65 have display elements 21, 22, .・
...25 cathodes are connected.

Note that the terminal 706 is a ground terminal. With the above configuration, the display elements 21, 22, . . . 25, for example, LE
D is the number of L corresponding to the signal strength when receiving AM signals.
The ED will be lit, and the tuning state and tuning direction will be displayed when an FM signal is received.

Therefore, it is extremely easy to operate the dial while checking the display to ensure optimal tuning.

In particular, even if the area occupied is smaller than that of an indicator, it is easy to see because it is an optical display.

In addition, its operation is extremely reliable, preventing malfunctions and enabling highly accurate form display.

As explained above, according to the present invention, extremely reliable display control can be achieved and an optimal synchronization state can be ensured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the tuning display control circuit of the present invention, FIG. 2 is a circuit diagram showing a specific configuration of the AM level display control circuit, and FIG. 3 is a block diagram of the FM tuning display control circuit. FIG. 4 is an explanatory diagram showing the operating principle, FIGS. 5 and 6 are explanatory diagrams showing the display form, and FIG. 7 is a circuit diagram showing a specific example of the tuning display control circuit. 21.22. ...2N...Display element, 4...
... Tuning display control circuit, 34... Tuning detection circuit, 38... Frequency divider, 40... Clock signal generator, 44... decoder.

Claims (1)

[Claims] 1. A clock signal generator that generates a clock signal, a frequency divider that divides the output clock signal of the clock signal generator to generate a predetermined number of code pulses, and an S-curve signal input. The tuning state is detected by comparing with the reference voltage, and if the tuning state is within the tuning point range near the tuning point, a tuning point signal is output, and if it is out of the tuning point range, a tuning direction signal is output. A tuning detection circuit outputs a tuning direction signal, and a tuning direction signal is inputted from the tuning detection circuit, and an output code pulse of the frequency divider is inputted, and a tuning direction display control signal is sequentially changed in response to the tuning direction signal. A decoder that outputs an output, a logic circuit that outputs an output of the decoder or an output tuning point signal of the tuning detection circuit, and a control means that detects the tuning state and sets a control range in which the logic circuit generates an output. What is claimed is: 1. A tuning display control circuit comprising: a tuning display control circuit for controlling tuning display elements configured as a set of a plurality of tuning display elements in different display forms depending on a tuning state. 2. The tuning display control circuit according to claim 1, wherein the control means for setting the control range is constituted by a switching circuit that switches when the level of the muting signal is at a predetermined level. 3. According to claim 1, the control means for setting the control range is constituted by an FM signal level detection circuit that switches when the FM signal level is at a predetermined value based on the FM signal level input. Tuning display control circuit to be described. 4. The tuning detection circuit includes a reference voltage setting circuit that divides a constant voltage by a resistor to set reference voltages corresponding to a tuning point range and tuning ranges on both sides thereof, and a setting standard output from this reference voltage setting circuit. The tuning display control circuit according to claim 1, comprising a comparator that compares the voltage and the S-curve signal input, detects a tuning state, and generates an output.