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JPS5826659B2 - Electrode formation method for semiconductor devices - Google Patents
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JPS5826659B2 - Electrode formation method for semiconductor devices - Google Patents

Electrode formation method for semiconductor devices

Info

Publication number
JPS5826659B2
JPS5826659B2 JP52015676A JP1567677A JPS5826659B2 JP S5826659 B2 JPS5826659 B2 JP S5826659B2 JP 52015676 A JP52015676 A JP 52015676A JP 1567677 A JP1567677 A JP 1567677A JP S5826659 B2 JPS5826659 B2 JP S5826659B2
Authority
JP
Japan
Prior art keywords
film
insulating film
contact hole
forming
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52015676A
Other languages
Japanese (ja)
Other versions
JPS5399873A (en
Inventor
博哲 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP52015676A priority Critical patent/JPS5826659B2/en
Publication of JPS5399873A publication Critical patent/JPS5399873A/en
Publication of JPS5826659B2 publication Critical patent/JPS5826659B2/en
Expired legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置、特に2種類の絶縁膜を使用する半
導体装置の電極形成法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a method for forming electrodes in a semiconductor device using two types of insulating films.

一般に各種の半導体装置に於てはその表面保護の為に、
半導体基板表面に酸化シリコン膜を形成し、更にその膜
上に異種の保護絶縁膜、例えば窒化シリコン膜を形成し
ている。
Generally, in order to protect the surface of various semiconductor devices,
A silicon oxide film is formed on the surface of a semiconductor substrate, and a different type of protective insulating film, such as a silicon nitride film, is further formed on the film.

一方このような2層保護膜構成の半導体装置に於ても電
極取り出しの為に両保護膜を貫通するコンタクト孔が必
要である。
On the other hand, even in a semiconductor device having such a two-layer protective film structure, a contact hole passing through both protective films is required to take out an electrode.

ところがこの両保護絶縁膜を貫通するコンタクト孔を設
けるにはその材質が異っているので、1種類のエツチン
グ液で一蝕刻工程で形成する事は出来ない。
However, in order to form a contact hole penetrating both protective insulating films, since the materials are different, it is impossible to form the contact hole in one etching process using one type of etching solution.

従って通常は上層の保護膜、例えば窒化シリコン膜上に
コンタクト孔に対応するフォトレジスト膜を設け、燐酸
等に依って窒化シリコン膜を蝕刻し、更にこの窒化シリ
コン膜をマスクとして弗酸に依る下層保護膜の酸化シリ
コン膜の蝕刻を行いこの窒化、酸化両シリコン膜を貫通
するコンタクト孔を得ている。
Therefore, usually a photoresist film corresponding to the contact hole is provided on the upper protective film, such as a silicon nitride film, the silicon nitride film is etched with phosphoric acid, and then the lower layer is etched with hydrofluoric acid using this silicon nitride film as a mask. The silicon oxide film of the protective film is etched to obtain a contact hole penetrating both the nitride and oxide silicon films.

このようにして得られたコンタクト孔を第1図に示す。The contact hole thus obtained is shown in FIG.

同図に於て1はシリコン基板、2は酸化シリコン膜、3
は窒化シリコン膜、4はこの窒化シリコン膜3上に設け
られた金属配線パターン、5はコンタクト孔である。
In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, and 3 is a silicon substrate.
4 is a silicon nitride film, 4 is a metal wiring pattern provided on this silicon nitride film 3, and 5 is a contact hole.

この図から明らかな如く、酸化シリコン2の蝕刻の際に
マスクとなった窒化シリコン3のコンタクト孔5側には
サイドエツチング現象に依って庇状体6,6が形成され
ており、この庇状体6,6の存在に依ってその後にコン
タクト孔5を介して基板1と金属配線パターン4とを連
結する為に実施する電極形成時に箔切れ等の不所望な接
触不良事故が発生する恐れがある。
As is clear from this figure, eaves-like bodies 6, 6 are formed on the side of the contact hole 5 of the silicon nitride 3, which served as a mask during the etching of the silicon oxide 2, due to the side etching phenomenon. Due to the presence of the bodies 6, 6, there is a risk that an undesirable contact failure such as foil breakage may occur during electrode formation which is subsequently performed to connect the substrate 1 and the metal wiring pattern 4 via the contact hole 5. be.

本発明はこのような庇状体6,6に起因する接触不良事
故の発生を防止する事を目的として為されたものであっ
て、第2図以降を参照しつつ詳述する。
The present invention has been made for the purpose of preventing the occurrence of poor contact accidents caused by such eaves-like bodies 6, 6, and will be described in detail with reference to FIG. 2 and subsequent figures.

本発明の第1の工程は、半導体基板10表面に比較的膜
犬なる第1の絶縁膜、例えば約5000人の酸化シリコ
ン膜11を形成するところにある(第2図)。
The first step of the present invention is to form a relatively thin first insulating film, for example, a silicon oxide film 11 of about 5,000 layers, on the surface of the semiconductor substrate 10 (FIG. 2).

この酸化シリコン膜11はシリコン基板10の熱酸化に
依って形成しても良く、その他の方法でも良く、選ぶと
ころではない。
This silicon oxide film 11 may be formed by thermal oxidation of the silicon substrate 10, or may be formed by other methods, and is not a matter of choice.

第2の工程は、第3図に示す如く、酸化シリコン膜11
上に第2の絶縁膜、例えば1000人程度0窒化シリコ
ン膜12を形成するもので、この第2の絶縁膜は窒化シ
リコン膜12に限る事なく、酸化シリコン膜11に対す
る選択エツチングのマスクと成り得るものであれば良い
In the second step, as shown in FIG.
A second insulating film, for example, a silicon nitride film 12 of about 1,000 layers, is formed on top of the silicon oxide film 12. It's fine as long as it's something you can get.

第3の工程は、窒化シリコン膜12に酸化シリコン膜1
1のコンタクト孔を設ける位置に該当するエツチング孔
13を形成する点にある(第4図)。
In the third step, a silicon oxide film 1 is applied to a silicon nitride film 12.
The first step is to form an etching hole 13 corresponding to the position where the first contact hole is to be provided (FIG. 4).

この工程はフォトレジスト法に依り、熱燐酸等を用いて
実施される。
This step is carried out by a photoresist method using hot phosphoric acid or the like.

次に第5図に示す如く、窒化シリコン膜12のエツチン
グ孔13をマスクとして弗酸を用いて酸化シリコン膜1
1にコンタクト孔14を形成するのが第4の工程である
Next, as shown in FIG. 5, the silicon oxide film 1 is etched using hydrofluoric acid using the etching hole 13 of the silicon nitride film 12 as a mask.
The fourth step is to form a contact hole 14 in 1.

この時この第5図からも明白な如く、酸化シリコン膜1
1のサイドエツチングに依って窒化シリコン膜12に庇
状体15゜15が形成されている。
At this time, as is clear from FIG. 5, the silicon oxide film 1
Eaves-like bodies 15.degree. 15 are formed on the silicon nitride film 12 by the side etching of step 1.

第5の工程は、上記各工程を経たシリコン基板10の全
面にC,V、D法等に依って後に配線パターンとして用
い得るモリブデン膜16を付着させる点にある(第6図
)。
The fifth step consists in depositing a molybdenum film 16, which can be used later as a wiring pattern, on the entire surface of the silicon substrate 10 that has gone through each of the above steps using the C, V, D method, etc. (FIG. 6).

このモリブデン膜16の厚みは約300OAである。The thickness of this molybdenum film 16 is approximately 300 OA.

次にこのモリブデン膜16上に上記コンタクト孔14と
同じか、或いはそれより僅かに大きな孔を有する金属配
線パターンのフォトレジスト膜17を形成するのが第6
の工程である(第7図)。
Next, in the sixth step, a photoresist film 17 having a metal wiring pattern having holes the same as or slightly larger than the contact holes 14 is formed on this molybdenum film 16.
This is the process (Figure 7).

第7の工程は、第8図に示す如く、第6の工程で得たフ
ォトレジスト膜17をマスクとしてフレオンガス(CF
4)のプラズマエツチングに依ってモリブデン膜16を
金属配線パターン状に残存させると同時に、このフレオ
ンガスのプラズマエツチングに依ってコンタクト孔14
の上端部に形成されていた窒化シリコン膜12の庇状体
15゜15をも蝕刻除去するところにある。
In the seventh step, as shown in FIG. 8, Freon gas (CF) is applied using the photoresist film 17 obtained in the sixth step as a mask.
The molybdenum film 16 is left in the form of a metal wiring pattern by the plasma etching in step 4), and at the same time, the contact holes 14 are formed by the Freon gas plasma etching.
The eaves 15.15 of the silicon nitride film 12 formed at the upper end of the silicon nitride film 12 are also removed by etching.

ここで用いられるフレオンガスのプラズマエツチングと
は、0、3 Torrのフレオンガス圧下に約30MH
zの高周波を印加する事に依って放電が起こり、その放
電中に置かれているシリコン基板10表面の露出モリブ
デン膜16並びに窒化シリコン膜12の庇状体15.1
5が蝕刻されるもので、常温中で実施されるが、プラズ
マ放電が起こると、基板10表面は200〜300℃に
昇温する事が確認されており、このような温度では約3
分間のプラズマエツチングが行われる。
The Freon gas plasma etching used here is about 30MH under a Freon gas pressure of 0.3 Torr.
By applying a high frequency wave of z, a discharge occurs, and during the discharge, the exposed molybdenum film 16 on the surface of the silicon substrate 10 and the eaves-like body 15.1 of the silicon nitride film 12 are exposed.
5 is etched and is carried out at room temperature, but it has been confirmed that when plasma discharge occurs, the temperature of the surface of the substrate 10 rises to 200 to 300 degrees Celsius.
Plasma etching is performed for 1 minute.

本発明の最終工程は、第9図に示す如く、コンタクト孔
14を介して基板10と金属配線パターン化されたモリ
ブデン膜16とをアルミニウム電極材料18に依って連
結するところにある。
The final step of the present invention, as shown in FIG. 9, is to connect the substrate 10 and the molybdenum film 16 patterned with metal wiring through the contact hole 14 using an aluminum electrode material 18.

この電極形成は1.2μ程度のアルミニウム蒸着とフォ
トレジスト法に依って実施される。
This electrode formation is performed by aluminum vapor deposition of about 1.2 μm and a photoresist method.

本発明は以上の説明から明らかな如く、コンタクト孔の
周縁に形成きれる庇状体がモリブデン膜をフレオンガス
のプラズマエツチングに依って金属配線パターン化され
る時に同時に除去されるので、基板と配線パターンとの
連結の為の電極形成時に箔切れに依る接触不良は一切発
生せず、半導体装置の信頼性を極めて高いものとする事
が出来る。
As is clear from the above description, in the present invention, the eaves-like body formed around the periphery of the contact hole is removed at the same time when the molybdenum film is patterned into a metal wiring pattern by plasma etching with Freon gas. There is no contact failure due to foil breakage when forming electrodes for connection, and the reliability of the semiconductor device can be made extremely high.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体装置の現状を示す要部の断面図、第2図
〜第9図は夫々本発明法を工程順に示した要部の断面図
であって、10は基板、11は酸化シリコン膜、12は
窒化シリコン膜、14はコンタクト孔、15は庇状体、
16はモリブテン膜、18は電極材料、を夫々示してい
る。
FIG. 1 is a cross-sectional view of the main part showing the current state of a semiconductor device, and FIGS. 2 to 9 are cross-sectional views of the main part showing the method of the present invention in order of process, in which 10 is a substrate, 11 is a silicon oxide 12 is a silicon nitride film, 14 is a contact hole, 15 is an eave-shaped body,
Reference numeral 16 indicates a molybdenum film, and reference numeral 18 indicates an electrode material.

Claims (1)

【特許請求の範囲】 1 下記する工程を順々に実施する半導体装置の電極形
成法; イ)半導体基板表面に比較的膜厚大なる第1の絶縁膜を
形成する工程、 口)該絶縁膜上にこの絶縁膜の選択蝕刻に際してマスク
と成り得る第2の絶縁膜を形成する工程、ノ\)上記第
1の絶縁膜のコンタクト孔を設ける位置に該当する箇所
の第2の絶縁膜にエツチング孔を形成する工程、 二)該エツチング孔に依って第1の絶縁膜を選択蝕刻し
てコンタクト孔を形成する工程、 ホ)上記の各工程を経た基板の全表面に後に配線パター
ンとして用いられるモリブデン膜を付着させる工程、 へ)該モリブデン膜上に上記コンタクト孔と同じか或い
はそれより僅かに大きな孔を有する金属配線パターンを
フォトレジスト膜で形成する工程、 ト)該フォトレジスト膜パターンをマスクとしてCF4
ガスのプラズマエツチングに依ってモリブデン膜を金属
配線パターンに応じて残存させると同時にこのCF4ガ
スのプラズマエツチングに依ってコンタクト孔の上端部
に存在する第2の絶縁膜の庇状体をも除去する工程、 チ)上記コンタクト孔を介して基板とモリブデン金属配
線パターンとを金属電極材料に依って連結する工程。 2 上記第1の絶縁膜は酸化シリコン膜から成り、第2
の絶縁膜は窒化シリコン膜で構成された事を特徴とする
特許請求の範囲第1項記載の半導体装置の電極形成法。
[Scope of Claims] 1. A method for forming electrodes of a semiconductor device, which comprises sequentially carrying out the following steps: (a) forming a relatively thick first insulating film on the surface of a semiconductor substrate; and (b) the insulating film. a step of forming a second insulating film on top of the insulating film that can serve as a mask during selective etching of the insulating film; \) etching the second insulating film at a location corresponding to a position where a contact hole is to be provided in the first insulating film; 2) forming a contact hole by selectively etching the first insulating film using the etched hole; e) forming a contact hole on the entire surface of the substrate that has gone through each of the above steps, which will later be used as a wiring pattern. a step of attaching a molybdenum film, f) forming a metal wiring pattern on the molybdenum film with a photoresist film having a hole the same as or slightly larger than the contact hole, g) masking the photoresist film pattern as CF4
The molybdenum film is left in accordance with the metal wiring pattern by gas plasma etching, and at the same time, the eaves-like body of the second insulating film existing at the upper end of the contact hole is also removed by this CF4 gas plasma etching. Step h) Connecting the substrate and the molybdenum metal wiring pattern through the contact hole using a metal electrode material. 2 The first insulating film is made of a silicon oxide film, and the second insulating film is made of a silicon oxide film.
2. The method of forming an electrode for a semiconductor device according to claim 1, wherein the insulating film is made of a silicon nitride film.
JP52015676A 1977-02-14 1977-02-14 Electrode formation method for semiconductor devices Expired JPS5826659B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52015676A JPS5826659B2 (en) 1977-02-14 1977-02-14 Electrode formation method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52015676A JPS5826659B2 (en) 1977-02-14 1977-02-14 Electrode formation method for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5399873A JPS5399873A (en) 1978-08-31
JPS5826659B2 true JPS5826659B2 (en) 1983-06-04

Family

ID=11895342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52015676A Expired JPS5826659B2 (en) 1977-02-14 1977-02-14 Electrode formation method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5826659B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137215A (en) * 1982-02-08 1983-08-15 Sanyo Electric Co Ltd Etching method of insulating film for semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS526597B2 (en) * 1972-06-14 1977-02-23
JPS5099278A (en) * 1973-12-28 1975-08-06

Also Published As

Publication number Publication date
JPS5399873A (en) 1978-08-31

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