JPS5823939B2 - integrated circuit manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to integrated circuits, and more particularly to a highly reliable electrode connection method.

(2) Prior Art Conventionally, in micro integrated circuits such as silicon integrated circuits, connections between electrodes are generally made as shown in FIG.

As shown in FIG. 1A, a first electrode 3 is selectively deposited on a substrate 1 on which a first insulating film 2 is deposited for insulation from the substrate 1. As shown in FIG.

For selective deposition, the generally widely used photoetching method or lift-off method may be used.

Thereafter, a second insulating film 4 is deposited on the entire surface or a part thereof in order to insulate it from the second electrode.

After that, in order to form a connection hole 6 between the first electrode 3 and the second electrode in the second insulating film 4, an etching resist 5 is applied and the connection hole 6 is formed by a widely used photo-etching method or the like. remove parts.

Thereafter, as shown in the figure, a connection hole 6 to the first electrode is formed in the second insulating film 4 by etching.

At this time, if the connection hole 6 and the first electrode 3 are minute, it will be difficult to maintain the alignment accuracy between the connection hole 6 and the first electrode 3, and the position of the connection hole 6 will shift, causing the second insulating film to When the etching solution No. 4 corrodes the first insulating film 2, an undercut I occurs.

When the second electrode 8 is placed on top of this as shown in FIG. This may result in thinning of the film, or may even interfere with the uniformity of the film deposited thereon.

Furthermore, the first insulating film 2 is thinner at the undercut 7, which not only lowers the electric withstand voltage, but also causes leakage when the first insulating film 2 is thin to begin with, causing the substrate 1 to This causes a short circuit with the second electrode 8.

Therefore, conventionally, the formation of such electrode connection holes on the thin first insulating film has been avoided as much as possible.

Taking an MO8 integrated circuit using silicon as an example, the substrate 1
is a silicon single crystal wafer, and the first and second insulating films are a substrate 1.
The first and second electrodes are made of polycrystalline silicon or A7. Cr, Ti.

It is often a metal such as Mo or W.

Therefore, the drawbacks of the conventional method mentioned above arise3.
In addition, in this conventional method, as shown in the plan view in Figure d, the first
The contact portion 10 between the electrode 3 and the second electrode 8 is the overlapped portion between the first electrode and the connection hole 6 (indicated by diagonal lines in the figure d), and the position of the first electrode 3 and the connection hole 6 is The more the contact portion 10 is deviated, the smaller the contact portion 10 becomes, which not only increases the contact resistance with the second electrode 8 but also reduces reliability.

(3) Object of the Invention The object of the present invention is to solve the above-mentioned drawbacks of the conventional method and to provide a novel method for manufacturing an integrated circuit which has a larger contact area than the conventional method even with the same positioning accuracy.

(4) Detailed explanation of the invention Before forming the contact hole by etching, an oxidation prevention film is formed in advance on the part that will become the connection hole, and then the first electrode is selectively left. Even if there is, not only the remaining portion of the original first electrode but also the connecting hole portion between the first electrode and the second electrode remain,
This is due to an increase in the number of contact areas.

(5) Examples Hereinafter, the present invention will be explained in detail with reference to Examples.

First, as shown in FIG. 2a, a thermal oxide film 2 of the substrate 1 as a first insulating film is formed on a silicon substrate 1 by a normal thermal oxidation method.

Usually, in order to reduce the parasitic capacitance between the substrate 1 and the wiring electrode, the thermal oxide film 2 is often made to have a thickness of 1 μm or more.

For example, in order to increase the oxidation rate, oxidation is often carried out in oxygen containing water vapor.
A thermal oxide film with a thickness of about 1.0 μm can be formed by oxidation for 5 hours.

When the pressure of the oxidizing atmosphere is increased, the oxidation rate also increases, and the oxidation time can be shortened to obtain a predetermined oxide film thickness.

Further, on this thermal oxide film 2, a polycrystalline silicon thin film 3', which will become a first electrode, is deposited with a film thickness of 100 to 50
Deposit to a thickness of 0 nm.

Impurities such as phosphorus are added to this to lower the resistivity.

After this, 100
An oxidation prevention film 11 of S x a N4 film with a thickness of about nm is applied.

This Si3N4 film can be deposited using a CVD method typified by the usual SiH4 + NH3 reaction, or it can be deposited by ion-implanting N2 over the entire surface of the polycrystalline Si to a surface concentration of approximately 1021/layer. Heat treated to coat the entire surface with Si3
An N4 film can also be formed.

Thereafter, as shown in FIG. 3B, a resist 5 left in a predetermined portion of the polycrystalline silicon film 3' or SiO□ left in a predetermined portion by etching is used as an etching mask for the polycrystalline silicon film 3'. The pattern of the first electrode 3 is formed by etching with CF4 plasma or HF+HN03 solution.

After that, as shown in FIG.
The exposed surface of the first electrode 3 is thermally oxidized using the mask as a mask.

For example, 1000°C DryO□ oxidation, 70°C in 1 hour
An oxide film 12 with a thickness of approximately nm is formed.

Also Wet. In 0□ oxidation, a faster oxidation rate can be obtained than in dry oxidation, and the thickness of the oxide film 12 can be formed as desired.

Thereafter, SiO was formed on the Sl3N4 film 11, which was a slight oxidation prevention film.

After removing, plasma etching using CF4 and 1
S used as an oxidation prevention film with phosphoric acid heated to around 80℃
After removing the i3 N4 film 11, the second electrode 8 is deposited on a predetermined portion as shown in FIG.

When the present invention is applied as described above, the first electrode 3 made of polycrystalline silicon remains in the connection hole 6 as shown in FIG. The contact portion 10 with the second electrode 8 represented by is clearly enlarged when compared with the explanatory diagram of the conventional method in FIG.
Not only is contact resistance reduced, but undercuts do not occur.

Therefore, since the second electrode 8 does not become disconnected, highly reliable electrode wiring can be formed.

Furthermore, if the first insulating film 2 is a thin gate oxide film of about 100 nm for a MOS transistor, undercuts do not occur in the present invention, so conventionally the connection hole 6 is formed directly on the gate oxide film. However, in the present invention, it is possible to form a contact hole in the gate on the gate oxide film, which can have a great effect on reducing the planar area of the integrated circuit.

(6) Summary As explained above, according to the present invention, the connection between the first electrode and the second electrode can be formed with higher reliability than before, and since the number of contact areas increases, finer wiring can be formed. can be formed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a conventional method, and FIG. 2 is a diagram showing an embodiment of the present invention.

Claims (1)

[Claims] 1. A step of depositing a thin film for the first electrode on the semiconductor substrate via an insulating film, and applying an oxidation prevention film on the surface of the thin film at the connection hole between the first electrode and the second electrode to be formed later. a step of forming the first electrode by including the oxidation prevention film portion in a part of the thin film for the first electrode, and then oxidizing the exposed surface of the first electrode. An integrated circuit manufacturing method comprising the steps of: removing the oxidation prevention film; and then forming a second electrode so as to include at least a portion of the connection hole.